Manual / Guide · 2021
NXP UM10204 I²C-bus Specification and User Manual, Rev. 7.0
The I²C specification; rise-time limits and the pull-up resistor formula used for the camera bus.
- i2c
- pull-up
- rise time
Manual / Guide · 2021
The I²C specification; rise-time limits and the pull-up resistor formula used for the camera bus.
UM10204 2 I C-bus specification and user manual Rev. 7.0 — 1 October 2021 User manual Document information Information Content Keywords I C, I C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+, UltraFastmode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple 2 bidirectional 2-wire bus for efficient inter-IC control, called the Inter-IC or I Cbus. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in Standard-mode, up to 400 kbit/s in Fast-mode, up to 1 Mbit/s in Fast-mode Plus (Fm+), or up to 3.4 Mbit/s in High-speed mode. Ultra Fast-mode is a unidirectional mode with data transfers of up to 5 Mbit/s. 2 2 NXP Semiconductors 2 UM10204 I C-bus specification and user manual Table 1. Revision history Rev Date Description v.7 20211001 User manual; seventh release Modifications: • Updated Table 5 • Updated the terms "master/slave" to "controller/target" throughout to align with MIPI I3C specification and NXP's Inclusive Language Project • Added Section 9 v.6 User manual; sixth release 20140404 Modifications: • Figure 41 updated (recalculated) • Figure 42 updated (recalculated) v.5 20121009 User manual; fifth release v.4 20120213 User manual Rev. 4 v.3 20070619 Many of today’s applications require longer buses and/or faster speeds. Fast-mode Plus was introduced to meet this need by increasing drive strength by as much as 10× and increasing the data rate to 1 Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode speeds and software commands. v2.1 2000 Version 2.1 of the I C-bus specification v2.0 1998 The I C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher 2 bus speeds and lower supply voltages. This updated version of the I C-bus specification meets those requirements. v1.0 1992 Version 1.0 of the I C-bus specification Original 1982 first release UM10204 User manual 2 2 2 All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 2 / 62 NXP Semiconductors 2 UM10204 I C-bus specification and user manual 1 Introduction 2 The I C-bus is a de facto world standard that is now implemented in over 1000 different 2 ICs manufactured by more than 50 companies. Additionally, the versatile I C-bus is used in various control architectures such as System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA). 2 This document assists device and system designers to understand how the I C-bus works and implement a working application. Various operating modes are described. It 2 contains a comprehensive introduction to the I C-bus data transfer, handshaking and bus arbitration schemes. Detailed sections cover the timing and electrical specifications for 2 the I C-bus in each of its operating modes. 2 Designers of I C-compatible chips should use this document as a reference and ensure that new devices meet all limits specified in this document. Designers of systems that 2 include I C devices should review this document and also refer to individual component data sheets. 2 Readers looking to develop I C based solutions may also be interested in I3C, introduced by the MIPI Alliance in 2017, with NXP's involvement and contributions. MIPI I3C offers 2 backward compatibility with I C, increased speed and low power consumption, and a royalty-free version is available for implementers. More information is included at the end of this document in Section 9. 2 2 I C-bus features In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes: • Some intelligent control, usually a single-chip microcontroller • General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM, EEPROM, real-time clocks or A/D and D/A converters • Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, temperature sensors, and smart cards To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire 2 2 bus for efficient inter-IC control. This bus is called the Inter IC or I C-bus. All I C-bus compatible devices incorporate an on-chip interface which allows them to communicate 2 directly with each other via the I C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. 2 Here are some of the features of the I C-bus: • Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). • Each device connected to the bus is software addressable by a unique address and simple controller/target relationships exist at all times; controllers can operate as controller-transmitters or as controller-receivers. • It is a true multi-controller bus including collision detection and arbitration to prevent data corruption if two or more controllers simultaneously initiate data transfer. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 3 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. • Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode • On-chip filtering rejects spikes on the bus data line to preserve data integrity. • The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance may be allowed under some conditions. Refer to Section 7.2. 2 Figure 1 shows an example of I C-bus applications. I2 C A/D or D/A Converters I2 C General Purpose I/O Expanders I2C LED Controllers I2C DIP Switches VDD4 I2C Target VDD5 I2C Repeaters/ Hubs/Extenders VDD0 I2C Port via HW or Bit Banging VDD2 PCA9541 I2 C Controller Selector/ Demux I2 C Multiplexers and Switches I2C Serial EEPROMs MCUs VDD1 I2C Bus Controllers 8 I2C Real Time Clock/ Calendars LCD Drivers (with I2C) MCUs I2C Temperature Sensors VDD3 Bridges (with I2C) SPI UART USB 002aac858 2 Figure 1. Example of I C-bus applications 2.1 Designer benefits 2 I C-bus compatible ICs allow a system design to progress rapidly directly from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the 2 I C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus. 2 Here are some of the features of I C-bus compatible ICs that are particularly attractive to designers: • Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic. 2 • No need to design bus interfaces because the I C-bus interface is already integrated on-chip. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 4 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual • Integrated addressing and data-transfer protocol allow systems to be completely software-defined. • The same IC types can often be used in many different applications. • Design-time reduces as designers quickly become familiar with the frequently used 2 functional blocks represented by I C-bus compatible ICs. • ICs can be added to or removed from a system without affecting any other circuits on the bus. • Fault diagnosis and debugging are simple; malfunctions can be immediately traced. • Software development time can be reduced by assembling a library of reusable software modules. 2 In addition to these advantages, the CMOS ICs in the I C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems. They all have: • Extremely low current consumption • High noise immunity • Wide supply voltage range • Wide operating temperature range. 2.2 Manufacturer benefits 2 I C-bus compatible ICs not only assist designers, they also give a wide range of benefits to equipment manufacturers because: 2 • The simple 2-wire serial I C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result — smaller and less expensive PCBs. 2 • The completely integrated I C-bus protocol eliminates the need for address decoders and other ‘glue logic’. 2 • The multi-controller capability of the I C-bus allows rapid testing and alignment of enduser equipment via external connections to an assembly line. 2 • The availability of I C-bus compatible ICs in various leadless packages reduces space requirements even more. 2 These are just some of the benefits. In addition, I C-bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around a basic model. Upgrades for new equipment, or enhanced-feature models (that is, extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter of selecting a microcontroller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it is easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor. 2.3 IC designer benefits Designers of microcontrollers are frequently under pressure to conserve output pins. 2 The I C protocol allows connection of a wide variety of peripherals without the need for separate addressing or chip enable signals. Additionally, a microcontroller that includes 2 an I C interface is more successful in the marketplace due to the wide variety of existing peripheral devices available. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 5 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual 3 2 The I C-bus protocol 2 3.1 Standard-mode, Fast-mode and Fast-mode Plus I C-bus protocols Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. An LCD driver may be only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as controllers or targets when performing data transfers (see Table 2). A controller is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a target. 2 Table 2. Definition of I C-bus terminology Term Description Transmitter the device which sends data to the bus Receiver the device which receives data from the bus Controller the device which initiates a transfer, generates clock signals and terminates a transfer Target the device addressed by a controller Multi-controller more than one controller can attempt to control the bus at the same time without corrupting the message Arbitration procedure to ensure that, if more than one controller simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Synchronization procedure to synchronize the clock signals of two or more devices 2 The I C-bus is a multi-controller bus. This means that more than one device capable of controlling the bus can be connected to it. As controllers are usually microcontrollers, let us consider the case of a data transfer between two microcontrollers connected to the 2 I C-bus (see Figure 2). MICRO CONTROLLER A LCD DRIVER STATIC RAM OR EEPROM SDA SCL GATE ARRAY MICRO CONTROLLER B ADC mbc645 2 Figure 2. Example of an I C-bus configuration using two microcontrollers This example highlights the controller-target and receiver-transmitter relationships found 2 on the I C-bus. Note that these relationships are not permanent, but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows: UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 6 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual 1. Suppose microcontroller A wants to send information to microcontroller B: • microcontroller A (controller), addresses microcontroller B (target) • microcontroller A (controller-transmitter), sends data to microcontroller B (targetreceiver) • microcontroller A terminates the transfer. 2. If microcontroller A wants to receive information from microcontroller B: • microcontroller A (controller) addresses microcontroller B (target) • microcontroller A (controller-receiver) receives data from microcontroller B (targettransmitter) • microcontroller A terminates the transfer. Even in this case, the controller (microcontroller A) generates the timing and terminates the transfer. 2 The possibility of connecting more than one microcontroller to the I C-bus means that more than one controller could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event, an arbitration procedure has been 2 developed. This procedure relies on the wired-AND connection of all I C interfaces to the 2 I C-bus. If two or more controllers try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ loses the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the controllers using the wired-AND connection to the SCL line (for more detailed information concerning arbitration see Section 3.1.8). 2 Generation of clock signals on the I C-bus is always the responsibility of controller devices; each controller generates its own clock signals when transferring data on the bus. Bus clock signals from a controller can only be altered when they are stretched by a slow target device holding down the clock line or by another controller when arbitration occurs. 2 Table 3 summarizes the use of mandatory and optional portions of the I C-bus specification and which system configurations use them. 2 Table 3. Applicability of I C-bus protocol features M = mandatory; O = optional; n/a = not applicable. Feature User manual [1] Single controller Multi-controller Target START condition M M M STOP condition M M M Acknowledge M M M Synchronization n/a M n/a Arbitration n/a M n/a [2] O 7-bit target address M M M 10-bit target address O O O General Call address O O O Software Reset O O n/a O [2] Clock stretching START byte UM10204 Configuration O O [3] All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 O n/a © NXP B.V. 2021. All rights reserved. 7 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual 2 Table 3. Applicability of I C-bus protocol features...continued M = mandatory; O = optional; n/a = not applicable. Feature Configuration Device ID [1] [2] [3] [1] Single controller Multi-controller Target n/a n/a O Also refers to a controller acting as a target. Clock stretching is a feature of some targets. If no targets in a system can stretch the clock (hold SCL LOW), the controller need not be designed to handle this procedure. ‘Bit banging’ (software emulation) multi-controller systems should consider a START byte. See Section 3.1.15. 3.1.1 SDA and SCL signals Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Figure 3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or 2 open-collector to perform the wired-AND function. Data on the I C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The bus capacitance limits the number of interfaces connected to the bus. For a single controller application, the controller’s SCL output can be a push-pull driver design if there are no devices on the bus which would stretch the clock. VDD1 = 5 V ± 10 % CMOS SDA Rp CMOS VDD2 VDD3 NMOS BIPOLAR Rp SCL 002aac860 VDD2, VDD3 are device-dependent (for example, 12 V). Figure 3. Devices with various supply voltages sharing the same bus 3.1.2 SDA and SCL logic levels Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be 2 connected to the I C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD. Input reference levels are set as 30 % and 70 % of VDD; VIL is 0.3VDD and VIH is 0.7VDD. See Figure 38, timing diagram. Some legacy device input levels were fixed at VIL = 1.5 V and VIH = 3.0 V, but all new devices require this 30 %/70 % specification. See Section 6 for electrical specifications. 3.1.3 Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Figure 4). One clock pulse is generated for each data bit transferred. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 8 / 62 NXP Semiconductors 2 UM10204 I C-bus specification and user manual SDA SCL data line stable; data valid change of data allowed mba607 2 Figure 4. Bit transfer on the I C-bus 3.1.4 START and STOP conditions All transactions begin with a START (S) and are terminated by a STOP (P) (see Figure 5). A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. SDA SCL S P START condition STOP condition mba608 Figure 5. START and STOP conditions START and STOP conditions are always generated by the controller. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is specified in Section 6. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. For the remainder of this document, therefore, the S symbol is used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition. 3.1.5 Byte format Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first (see Figure 6). If a target cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the controller into a wait state. Data transfer then continues when the target is ready for another byte of data and releases clock line SCL. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 9 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual P SDA acknowledgment signal from target MSB SCL S or Sr 1 2 7 8 9 acknowledgment signal from receiver 1 2 3 to 8 ACK START or repeated START condition byte complete, interrupt within target 9 ACK clock line held LOW while interrupts are serviced Sr Sr or P STOP or repeated START condition 002aac861 2 Figure 6. Data transfer on the I C-bus 3.1.6 Acknowledge (ACK) and Not Acknowledge (NACK) The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. The controller generates all clock pulses, including the acknowledge ninth clock pulse. The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse (see Figure 4). Set-up and hold times (specified in Section 6) must also be taken into account. When SDA remains HIGH during this ninth clock pulse, this is defined as the Not Acknowledge signal. The controller can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. There are five conditions that lead to the generation of a NACK: 1. No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge. 2. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the controller. 3. During the transfer, the receiver gets data or commands that it does not understand. 4. During the transfer, the receiver cannot receive any more data bytes. 5. A controller-receiver must signal the end of the transfer to the target transmitter. 3.1.7 Clock synchronization Two controllers can begin transmitting on a free bus at the same time and there must be a method for deciding which takes control of the bus and complete its transmission. This is done by clock synchronization and arbitration. In single controller systems, clock synchronization and arbitration are not needed. 2 Clock synchronization is performed using the wired-AND connection of I C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the controllers concerned to start counting off their LOW period and, once a controller clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see Figure 7). However, if another clock is still within its LOW period, the LOW to HIGH transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the controller with the longest LOW period. Controllers with shorter LOW periods enter a HIGH wait-state during this time. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 10 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual wait state start counting HIGH period CLK 1 CLK 2 counter reset SCL mbc632 Figure 7. Clock synchronization during the arbitration procedure When all controllers concerned have counted off their LOW period, the clock line is released and goes HIGH. There is then no difference between the controller clocks and the state of the SCL line, and all the controllers start counting their HIGH periods. The first controller to complete its HIGH period pulls the SCL line LOW again. In this way, a synchronized SCL clock is generated with its LOW period determined by the controller with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. 3.1.8 Arbitration Arbitration, like synchronization, refers to a portion of the protocol required only if more than one controller is used in the system. Targets are not involved in the arbitration procedure. A controller may start a transfer only if the bus is free. Two controllers may generate a START condition within the minimum hold time (tHD;STA) of the START condition which results in a valid START condition on the bus. Arbitration is then required to determine which controller will complete its transmission. Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each controller checks to see if the SDA level matches what it has sent. This process may take many bits. Two controllers can actually complete an entire transaction without error, as long as the transmissions are identical. The first time a controller tries to send a HIGH, but detects that the SDA level is LOW, the controller knows that it has lost the arbitration and turns off its SDA output driver. The other controller goes on to complete its transaction. No information is lost during the arbitration process. A controller that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and must restart its transaction when the bus is free. If a controller also incorporates a target function and it loses arbitration during the addressing stage, it is possible that the winning controller is trying to address it. The losing controller must therefore switch over immediately to its target mode. Figure 8 shows the arbitration procedure for two controllers. More may be involved depending on how many controllers are connected to the bus. The moment there is a difference between the internal data level of the controller generating DATA1 and the actual level on the SDA line, the DATA1 output is switched off. This does not affect the data transfer initiated by the winning controller. UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 11 / 62 NXP Semiconductors 2 UM10204 I C-bus specification and user manual controller 1 loses arbitration DATA 1 SDA DATA 1 DATA 2 SDA SCL S msc609 Figure 8. Arbitration procedure of two controllers 2 Since control of the I C-bus is decided solely on the address and data sent by competing controllers, there is no central controller, nor any order of priority on the bus. There is an undefined condition if the arbitration procedure is still in progress at the moment when one controller sends a repeated START or a STOP condition while the other controller is still sending data. In other words, the following combinations result in an undefined condition: • Controller 1 sends a repeated START condition and controller 2 sends a data bit. • Controller 1 sends a STOP condition and controller 2 sends a data bit. • Controller 1 sends a repeated START condition and controller 2 sends a STOP condition. 3.1.9 Clock stretching Clock stretching pauses a transaction by holding the SCL line LOW. The transaction cannot continue until the line is released HIGH again. Clock stretching is optional and in fact, most target devices do not include an SCL driver so they are unable to stretch the clock. On the byte level, a device may be able to receive bytes of data at a fast rate, but needs more time to store a received byte or prepare another byte to be transmitted. Targets can then hold the SCL line LOW after reception and acknowledgment of a byte to force the controller into a wait state until the target is ready for the next byte transfer in a type of handshake procedure (see Figure 7). On the bit level, a device such as a microcontroller with or without limited hardware for 2 the I C-bus, can slow down the bus clock by extending each clock LOW period. The speed of any controller is adapted to the internal operating rate of this device. In Hs-mode, this handshake feature can only be used on byte level (see Section 5.3.2). 3.1.10 The target address and R/W bit Data transfers follow the format shown in Figure 9. After the START condition (S), a target address is sent. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ) (refer to Figure 10). A data transfer is always terminated by UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 12 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual a STOP condition (P) generated by the controller. However, if a controller still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another target without first generating a STOP condition. Various combinations of read/ write formats are then possible within such a transfer. SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 P S START condition ADDRESS R/W ACK DATA ACK DATA ACK STOP condition mbc604 Figure 9. A complete data transfer MSB LSB R/W target address mbc608 Figure 10. The first byte after the START procedure Possible data transfer formats are: • Controller-transmitter transmits to target-receiver. The transfer direction is not changed (see Figure 11). The target receiver acknowledges each byte. • Controller reads target immediately after first byte (see Figure 12). At the moment of the first acknowledge, the controller-transmitter becomes a controller-receiver and the target-receiver becomes a target-transmitter. This first acknowledge is still generated by the target. The controller generates subsequent acknowledges. The STOP condition is generated by the controller, which sends a not-acknowledge (A) just before the STOP condition. • Combined format (see Figure 13). During a change of direction within a transfer, the START condition and the target address are both repeated, but with the R/W bit reversed. If a controller-receiver sends a repeated START condition, it sends a notacknowledge (A) just before the repeated START condition. Notes: 1. Combined formats can be used, for example, to control a serial memory. The internal memory location must be written during the first data byte. After the START condition and target address is repeated, data can be transferred. 2. All decisions on auto-increment or decrement of previously accessed memory locations, etc., are taken by the designer of the device. 3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the sequence. 2 4. I C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a target UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 13 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual address, even if these START conditions are not positioned according to the proper format. 5. A START condition immediately followed by a STOP condition (void message) is an illegal format. Many devices however are designed to operate properly under this condition. 6. Each device connected to the bus is addressable by a unique address. Normally a simple controller/target relationship exists, but it is possible to have multiple identical targets that can receive and respond simultaneously, for example in a group broadcast. This technique works best when using bus switching devices like the PCA9546A where all four channels are on and identical devices are configured at the same time, understanding that it is impossible to determine that each target acknowledges, and then turn on one channel at a time to read back each individual device’s configuration to confirm the programming. Refer to individual component data sheets. S TARGET ADDRESS R/W A DATA A DATA A/A P data transferred (n bytes + acknowledge) '0' (write) from controller to target A = acknowledge (SDA LOW) from target to controller A = not acknowledge (SDA HIGH) S = START condition P = STOP condition mbc605 Figure 11. A controller-transmitter addressing a target receiver with a 7-bit address (the transfer direction is not changed) 1 S TARGET ADDRESS R/W A (read) DATA A DATA A P data transferred (n bytes + acknowledge) mbc606 Figure 12. A controller reads a target immediately after the first byte S TARGET ADDRESS R/W A read or write * not shaded because transfer direction of data and acknowledge bits depends on R/W bits. DATA A/A Sr TARGET ADDRESS R/W (n bytes + ack.)* A DATA A/A P (n bytes + ack.)* read or write Sr = repeated START condition direction of transfer may change at this point. mbc607 Figure 13. Combined format UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 14 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual 3.1.11 10-bit addressing 10-bit addressing expands the number of possible addresses. Devices with 7-bit and 2 10-bit addresses can be connected to the same I C-bus, and both 7-bit and 10-bit addressing can be used in all bus speed modes. Currently, 10-bit addressing is not being widely used. The 10-bit target address is formed from the first two bytes following a START condition (S) or a repeated START condition (Sr). The first seven bits of the first byte are the combination 1111 0XX of which the last two bits (XX) are the two Most-Significant Bits (MSB) of the 10-bit address; the eighth bit of the first byte is the R/W bit that determines the direction of the message. Although there are eight possible combinations of the reserved address bits 1111 XXX, only the four combinations 1111 0XX are used for 10-bit addressing. The remaining four 2 combinations 1111 1XX are reserved for future I C-bus enhancements. All combinations of read/write formats previously described for 7-bit addressing are possible with 10-bit addressing. Two are detailed here: • Controller-transmitter transmits to target-receiver with a 10-bit target address. The transfer direction is not changed (see Figure 14). When a 10-bit address follows a START condition, each target compares the first seven bits of the first byte of the target address (1111 0XX) with its own address and tests if the eighth bit (R/W direction bit) is 0. It is possible that more than one device finds a match and generate an acknowledge (A1). All targets that found a match compare the eight bits of the second byte of the target address (XXXX XXXX) with their own addresses, but only one target finds a match and generates an acknowledge (A2). The matching target remains addressed by the controller until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different target address. • Controller-receiver reads target-transmitter with a 10-bit target address. The transfer direction is changed after the second R/W bit (Figure 15). Up to and including acknowledge bit A2, the procedure is the same as that described for a controllertransmitter addressing a target-receiver. After the repeated START condition (Sr), a matching target remembers that it was addressed before. This target then checks if the first seven bits of the first byte of the target address following Sr are the same as they were after the START condition (S), and tests if the eighth (R/W) bit is 1. If there is a match, the target considers that it has been addressed as a transmitter and generates acknowledge A3. The target-transmitter remains addressed until it receives a STOP condition (P) or until it receives another repeated START condition (Sr) followed by a different target address. After a repeated START condition (Sr), all the other target devices will also compare the first seven bits of the first byte of the target address (1111 0XX) with their own addresses and test the eighth (R/W) bit. However, none of them will be addressed because R/W = 1 (for 10-bit devices), or the 1111 0XX target address (for 7-bit devices) does not match. 1 1 1 1 0 X X 0 TARGET ADDRESS TARGET ADDRESS S R/W A1 A2 DATA 1st 7 BITS 2nd BYTE A DATA A/A P mbc613 (write) Figure 14. A controller-transmitter addresses a target-receiver with a 10-bit address UM10204 User manual All information provided in this document is subject to legal disclaimers. Rev. 7.0 — 1 October 2021 © NXP B.V. 2021. All rights reserved. 15 / 62 UM10204 NXP Semiconductors 2 I C-bus specification and user manual 1 1 1 1 0 X X 0 1 1 1 1 0 X X TARGET ADDRESS TARGET ADDRESS S R/W A1 A2 1st 7 BITS 2nd BYTE 1 TARGET ADDRESS Sr R/W A3 DATA 1st 7 BITS (write) A (read) DATA A P mbc614 Figure 15. A controller-receiver addresses a target-transmitter with a 10-bit address Target devices with 10-bit addressing react to a ‘general call’ in the same way as target devices with 7-bit addressing. Hardware controllers can transmit their 10-bit address after a ‘general call’. In this case, the ‘general call’ address byte is followed by two successive bytes containing the 10-bit address of the controller-transmitter. The format is as shown in Figure 15 where the first DATA byte contains the eight least-significant bits of the controller address. The START byte 0000 0001 (01h) can precede the 10-bit addressing in the same way as for 7-bit addressing (see Section 3.1.15). 3.1.12 Reserved addresses Two groups of eight addresses (0000 XXX and 1111 XXX) are reserved for the purposes shown in Table 4. Table 4. Reserved addresses X = don’t care; 1 = HIGH; 0 = LOW. Target address R/W bit Description 0000 000 0 general call address 0000 000 1 START byte 0000 001 X CBUS address 0000 010 X reserved for different bus format 0000 011 X reserved for future purposes 0000 1XX X Hs-mode controller code 1111 1XX 1 device ID 1111 0XX X 10-bit target addressing [1] [2] [3] [4] [1] [2] [3] [4] The general call address is used for several functions including software reset. No device is allowed to acknowledge at the reception of the START byte. 2 The CBUS address has been reserved to enable the inter-mixing of CBUS compatible and I C-bus compatible devices in 2 the same system. I C-bus compatible devices are not allowed to respond on reception of this address. 2 2 The address reserved for a different bus format is included to enable I C and other protocols to be mixed. Only I C-bus compatible devices that can work with such formats and protocols are allowed to respond to this address. Assignment of addresses within a local system is up to the system architect who must take into account the devices being used on the bus and any future interaction with other 2 conventional I C-buses. For example, a device with seven user-assignable address pins allows all 128 addresses to be assigned. If it is known that the reserved address is never going to be used f