Datasheet · 2015

TI UCC27517A Single-Channel High-Speed Low-Side Gate Driver — Datasheet (SLUSBQ0C)

4 A peak low-side gate driver; the gate driver of the reference solenoid stage.

Author: Texas Instruments
Year: 2015
Type: Datasheet
Credit: Texas Instruments (ti.com)

gate driver
mosfet
solenoid driver

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 UCC27517A Single-Channel High-Speed Low-Side Gate Driver with Negative Input Voltage Capability (with 4-A Peak Source and Sink) 1 Features 3 Description • The UCC27517A single-channel, high-speed, lowside gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27517A is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns. 1 • • • • • • • • • • • • • Low-Cost Gate-Driver Device Offering Superior Replacement of NPN and PNP Discrete Solutions 4-A Peak-Source and Sink Symmetrical Drive Ability to Handle Negative Voltages (-5 V) at Inputs Fast Propagation Delays (13-ns typical) Fast Rise and Fall Times (9-ns and 7-ns typical) 4.5 to 18-V Single-Supply Range Outputs Held Low During VDD UVLO (ensures glitch-free operation at power up and power down) TTL and CMOS Compatible Input-Logic Threshold (independent of supply voltage) Hysteretic-Logic Thresholds for High-Noise Immunity Dual Input Design (choice of an inverting (IN- pin) or non-inverting (IN+ pin) driver configuration) – Unused Input Pin can be Used for Enable or Disable Function Output Held Low when Input Pins are Floating Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage Operating Temperature Range of –40°C to +140°C 5-Pin DBV (SOT-23) Package Option • • The UCC27517A provides 4-A source and 4-A sink (symmetrical drive) peak-drive current capability at VDD = 12 V. The UCC27517A is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –40°C to 140°C. Internal Undervoltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN power semiconductor devices. Device Information(1) PART NUMBER PACKAGE UCC27517A BODY SIZE (NOM) SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • The UCC27517A device is capable of handling –5 V at input. Switch-Mode Power Supplies DC-to-DC Converters Companion Gate-Driver Devices for Digital-Power Controllers Solar Power, Motor Control, UPS Gate Driver for Emerging Wide Band-Gap Power Devices (such as GaN) Typical Application Diagrams Inverting Input Non-Inverting Input Q1 Q1 UCC27517A UCC27517A 4.5 V to 18 V V+ 4.5 V to 18 V R1 1 VDD OUT 5 C1 V+ R1 1 VDD 2 GND 3 IN+ OUT 5 IN- 4 C1 IN+ 2 GND 3 IN+ IN- 4 VIN- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Description (continued)......................................... 3 Device Comparison Table..................................... 3 Pin Configuration and Functions ......................... 4 Specifications......................................................... 4 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics........................................... 6 Switching Characteristics .......................................... 7 Typical Characteristics .............................................. 8 Detailed Description ............................................ 11 9.1 Overview ................................................................. 11 9.2 Functional Block Diagram ....................................... 12 9.3 Feature Description................................................. 12 9.4 Device Functional Modes........................................ 15 10 Application and Implementation........................ 16 10.1 Application Information.......................................... 16 10.2 Typical Application ............................................... 16 11 Power Supply Recommendations ..................... 20 12 Layout................................................................... 21 12.1 12.2 12.3 12.4 Layout Guidelines ................................................. 21 Layout Example .................................................... 22 Thermal Considerations ........................................ 22 Power Dissipation ................................................. 23 13 Device and Documentation Support ................. 24 13.1 13.2 13.3 13.4 Community Resources.......................................... 24 Trademarks ........................................................... 24 Electrostatic Discharge Caution ............................ 24 Glossary ................................................................ 24 14 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 2013) to Revision C • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision A (August 2013) to Revision B • 2 Page Page Changed marketing status from Product Preview to Final. .................................................................................................... 1 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 5 Description (continued) UCC27517A features a dual input design which offers flexibility of implementing both inverting (IN- pin) and noninverting (IN+ pin) configurations with the same device. Either the IN+ or IN- pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable function. For protection purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation. The input pin threshold of the UCC27517A device is based on TTL and CMOS compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. 6 Device Comparison Table The UCC2751x family of gate-driver products (Table 1) represent Texas Instruments’ latest generation of singlechannel, low-side high-speed gate driver devices featuring high-source and sink current capability, industry bestin-class switching characteristics, and a host of other features (Table 3) all of which combine to ensure efficient, robust, and reliable operation in high-frequency switching power circuits. Table 1. UCC2751x Product Family Summary (1) PART NUMBER (1) PACKAGE UCC27511DBV UCC27511ADBVQ1 SOT-23, 6 pin UCC27512DRS 3-mm × 3-mm WSON, 6 pin UCC27516DRS 3-mm × 3-mm WSON, 6 pin UCC27517DBV UCC27517ADBVQ1 UCC27517ADBV SOT-23, 5 pin UCC27518DBV UCC27518ADBVQ1 SOT-23, 5 pin UCC27519DBV UCC27519ADBVQ1 SOT-23, 5 pin PEAK CURRENT (SOURCE, SINK) INPUT THRESHOLD LOGIC 4-A, 8-A (Asymmetrical Drive) CMOS and TTL-Compatible (low voltage, independent of VDD bias voltage) 4-A, 4-A (Symmetrical Drive) CMOS (follows VDD bias voltage) Visit www.ti.com for the latest product datasheet. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 3 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com 7 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View VDD 1 GND 2 IN+ 3 5 OUT 4 IN- Pin Functions PIN NO. NAME I/O DESCRIPTION 1 VDD I Bias supply input. 2 GND — Ground. All signals reference to this pin. 3 IN+ I Non-inverting input. Apply PWM control signal to this pin when driver is desired to be operated in non-inverting configuration. When the driver is used in inverting configuration, connect IN+ to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating 4 IN- I Inverting input. Apply PWM control signal to this pin when driver is desired to be operated in inverting configuration. When the driver is used in non-inverting configuration, connect IN– to GND in order to enable output, OUT held LOW if IN– is unbiased or floating 5 OUT O Sourcing/Sinking current output of driver. 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN Supply voltage OUT voltage MAX UNIT V VDD –0.3 20 DC –0.3 VDD + 0.3 Repetitive pulse less than 200 ns (4) –2 VDD + 0.3 Output continuous current IOUT_DC (source/sink) 0.3 Output pulsed current (0.5 µs) IOUT_pulsed(source/sink) 4 Input voltage IN+, IN- (5) Operating virtual junction temperature, TJ Lead temperature (1) (2) (3) (4) (5) 4 A –6 20 V –40 150 °C Soldering, 10 sec. 300 Reflow 260 Storage temperature, Tstg V –65 150 °C °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Packaging Section of the datasheet for thermal limitations and considerations of packages. These devices are sensitive to electrostatic discharge; follow proper device-handling procedures. Values are verified by characterization on bench. Maximum voltage on input pins is not restricted by the voltage on the VDD pin. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 8.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP Supply voltage, VDD 4.5 12 18 V Operating junction temperature –40 140 °C 0 18 V Input voltage, IN+ and IN- MAX UNIT 8.4 Thermal Information UCC27517A THERMAL METRIC (1) (2) DBV (SOT-23) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 217.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 85.8 °C/W RθJB Junction-to-board thermal resistance 44 °C/W ψJT Junction-to-top characterization parameter 4 °C/W ψJB Junction-to-board characterization parameter 43.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Under identical power dissipation conditions, the DRS package will allow to maintain a lower die temperature than the DBV. θJA metric should be used for comparison of power dissipation capability between different packages (Refer to the Application Information section). Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 5 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com 8.5 Electrical Characteristics VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal. PARAMETER TEST CONDITION MIN TYP MAX IN+ = VDD, IN- = GND 40 100 160 IN+ = IN- = GND or IN+ = IN- = VDD 25 75 145 IN+ = GND, IN- = VDD 20 60 115 TA = 25°C 3.91 4.20 4.5 TA = -40°C to 140°C 3.70 4.20 4.65 UNIT BIAS CURRENTS IDD(off) Startup current VDD = 3.4 V µA UNDER VOLTAGE LOCKOUT (UVLO) VON Supply start threshold V VOFF Minimum operating voltage after supply start 3.45 3.9 4.35 V VDD_H Supply voltage hysteresis 0.2 0.3 0.5 V 2.2 2.4 V INPUTS (IN+, IN-) VIN_H Input signal high threshold Output high for IN+ pin, Output low for IN- pin VIN_L Input signal low threshold Output low for IN+ pin, Output high for IN- pin 1.0 1.2 V 1.0 V CLOAD = 0.22 µF, FSW = 1 kHz ±4 A VDD = 12 V IOUT = -10 mA 50 90 VDD = 4.5 V IOUT = -10 mA 60 130 VDD = 12 IOUT = 10 mA 5 10 VDD = 4.5 V IOUT = 10 mA 6 12 VDD = 12 V IOUT = -10 mA 5.0 7.5 VDD = 4.5 V IOUT = -10 mA 5.0 11.0 VDD = 12 V IOUT = 10 mA 0.5 1.0 VDD = 4.5 V IOUT = 10 mA 0.6 1.2 VIN_HYS Input signal hysteresis SOURCE/SINK CURRENT ISRC/SNK Source/sink peak current (1) OUTPUTS (OUT) VDDVOH VOL ROH ROL (1) (2) 6 High output voltage Low output voltage Output pullup resistance (2) Output pulldown resistance mV mV Ω Ω Ensured by Design. ROH represents on-resistance of P-Channel MOSFET in pull-up structure of the UCC27517A's output stage. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 8.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER tR tF tD1 tD2 (1) TEST CONDITIONS Rise time (1) Fall time (1) IN+ to output propagation delay IN- to output propagation delay (1) (1) MIN TYP MAX VDD = 12 V CLOAD = 1.8 nF 8 12 VDD = 4.5 V CLOAD = 1.8 nF 16 22 VDD = 12 V CLOAD = 1.8 nF 7 11 VDD=4.5V CLOAD = 1.8 nF 7 11 UNIT ns ns VDD = 12 V 5-V input pulse CLOAD = 1.8 nF 4 13 23 VDD = 4.5 V 5-V input pulse CLOAD = 1.8 nF 4 13 26 VDD = 12 V CLOAD = 1.8 nF 4 13 23 VDD = 4.5 V CLOAD = 1.8 nF 4 19 30 ns ns See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4. High INPUT (IN+ pin) Low High INPUT (IN- pin) Low High IN- pin Low High IN+ pin 90% OUTPUT 90% OUTPUT 10% 10% Low tD1 t r tD1 tf tD2 tf Figure 1. Non-Inverting Configuration (PWM Input to IN+ pin (IN- pin tied to GND)) Figure 2. Inverting Configuration (PWM input to IN- pin (IN+ pin tied to VDD)) High INPUT (IN- pin) Low High INPUT (IN+ pin) Low High ENABLE (IN+ pin) Low High ENABLE (IN- pin) Low 90% OUTPUT 90% OUTPUT 10% 10% tD1 tr tD1 tf tD2 t f Figure 3. Enable and Disable Function Using IN+ Pin (Enable and disable signal applied to IN+ pin, PWM input to IN- pin) tD2 tr tD2 tr Figure 4. Enable and Disable Function Using INPin (Enable and disable signal applied to IN- pin, PWM input to IN+ pin) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 7 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com 8.7 Typical Characteristics 0.12 3.5 0.1 IDD (mA) Startup Current (mA) 0.11 4 IN+=Low,IN−=Low IN+=High, IN−=Low 0.09 0.08 0.07 VDD = 3.4 V 0 50 Temperature (°C) 100 2 −50 150 100 150 G013 4.6 IN+=Low,IN−=Low IN+=High, IN−=Low UVLO Rising UVLO Falling 4.4 0.4 UVLO Threshold (V) Operating Supply Current (mA) 50 Temperature (°C) Figure 6. Operating Supply Current vs Temperature (Output Switching) 0.5 0.3 0.2 4.2 4 3.8 VDD = 12 V 0.1 −50 0 50 Temperature (°C) 100 3.6 −50 150 50 Temperature (°C) 100 150 G003 Figure 8. UVLO Threshold Voltage vs Temperature 3.5 8 VDD = 12 V CLoad = 1.8 nF RoH Output Pull−Up Resistance (Ω) Turn−On Turn−Off 3 2.5 2 1.5 1 −50 0 G002 Figure 7. Supply Current vs Temperature (Output in DC ON/OFF Condition) Input Threshold (V) 0 G001 Figure 5. Start-Up Current vs Temperature 0 50 Temperature (°C) 100 150 7 6 5 4 −50 G014 Figure 9. Input Threshold vs Temperature 8 VDD = 12 V CLoad = 500 pF fsw = 500 kHz 2.5 0.06 0.05 −50 3 VDD = 12 V Iout = 10 mA 0 50 Temperature (°C) 100 150 G004 Figure 10. Output Pullup Resistance vs Temperature Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 Typical Characteristics (continued) 1 8 VDD = 12 V CLoad = 1.8 nF 0.8 7 Rise Time (ns) Pull−Down Resistance (Ω) ROL 0.6 0.4 6 5 0.2 −50 0 50 Temperature (°C) 100 4 −50 150 Figure 11. Output Pulldown Resistance vs Temperature 150 G000 Propagation Delay (ns) Turn−On Turn−Off 9 Fall Time (ns) 100 20 VDD = 12 V CLoad = 1.8 nF 8 7 6 −50 0 50 Temperature (°C) 100 15 10 VDD = 12 V 5 −50 150 0 G000 Figure 13. Fall Time vs Temperature 50 Temperature (°C) 100 150 G006 Figure 14. Input to Output Propagation Delay vs Temperature 20 20 VDD=4.5V VDD=12V VDD=15V 16 18 Propagation Delay (ns) 18 Supply Current (mA) 50 Temperature (°C) Figure 12. Rise Time vs Temperature 10 14 12 10 8 6 4 0 100 200 300 400 Frequency (kHz) 500 600 16 14 12 10 8 CLoad = 1.8 nF 2 0 0 G000 700 6 Turn−On Turn−Off 0 G010 Figure 15. Operating Supply Current vs Frequency 4 8 12 Supply Voltage (V) 16 20 G007 Figure 16. Propagation Delays vs Supply Voltage Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 9 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) 20 10 Fall Time (ns) Rise Time (ns) 8 15 10 6 4 5 0 4 8 12 Supply Voltage (V) 16 20 2 0 G008 Figure 17. Rise Time vs Supply Voltage 10 Submit Documentation Feedback 4 8 12 Supply Voltage (V) 16 20 G009 Figure 18. Fall Time vs Supply Voltage Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 9 Detailed Description 9.1 Overview The UCC2751xA single-channel, high-speed, low-side gate-driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC2751x device is capable of sourcing and sinking high peak-current pulses into capacitive loads offering railto-rail drive capability and extremely small propagation delay of 13 ns (typical). The UCC2751xA family of devices provides 4-A source, 4-A sink (symmetrical drive) peak-drive current capability. The device is designed to operate over a wide VDD range of 4.5 to 18 V, and a wide temperature range of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the VDD pin holds the output low outside VDD operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-in- class switching characteristics, is especially suited for driving emerging wide bandgap power-switching devices such as GaN powersemiconductor devices. The UCC27517A device features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and non-inverting (IN+ pin) configuration with the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For system robustness, internal pull-up and pull-down resistors on the input pins ensure that outputs are held low when the input pins are in floating condition. Therefore the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation. The input pin threshold of the UCC27517A device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity. Table 2. UCC27517A Summary PART NUMBER PACKAGE PEAK CURRENT (SOURCE, SINK) INPUT THRESHOLD LOGIC UCC27517ADBVQ1 SOT-23, 5 pin 4-A, 4-A (Symmetrical Drive) CMOS and TTL-Compatible (low voltage, independent of VDD bias voltage) Table 3. UCC27517A Features and Benefits FEATURE BENEFIT High Source, Sink Current Capability 4 A, 4 A (Symmetrical) High current capability offers flexibility in employing the UCC27517A to drive a variety of power switching devices at varying speeds Best-in-class 13-ns (typ) Propagation delay Extremely low-pulse transmission distortion Expanded VDD Operating range of 4.5 V to 18 V Expanded Operating Temperature range of –40°C to 140°C (See Recommended Operating Conditions table) Flexibility in system design Low VDD operation ensures compatibility with emerging widebandgap power devices such as GaN VDD UVLO Protection Outputs are held low in UVLO condition, which ensures predictable glitch-free operation at power up and power down Outputs held low when input pins (INx) in floating condition Protection feature, especially useful in passing abnormal condition tests during protection certification Ability of input pins to handle voltage levels not restricted by VDD pin bias voltage System simplification, especially related to auxiliary bias supply architecture Enhanced noise immunity, while retaining compatibility with CMOS and TTL compatible input threshold logic with wide hysteresis microcontroller logic-level input signals (3.3 V, 5 V) optimized for in UCC27517A digital power Ability to handle –5 VDC at input pins Increased robustness in noisy environments Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 11 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com 9.2 Functional Block Diagram IN+ VDD 3 VDD 1 VDD 5 OUT 230 kW 200 kW IN- 4 VDD GND 2 UVLO 9.3 Feature Description 9.3.1 VDD and Undervoltage Lockout The UCC27517A has internal Undervoltage Lockout (UVLO) protection feature on the VDD-pin supply-circuit blocks. Whenever the driver is in UVLO condition (for example when VDD voltage is less than VON during power up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent chatter when low VDD – supply voltages have noise from the power supply and also when there are droops in the VDD-bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide-bandgap power-semiconductor devices. For example, at power up, the UCC27517A driver output remains LOW until the VDD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the non-inverting operation (PWM signal applied to IN+ pin) shown in Figure 19, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN– pin) shown in Figure 20 the output remains LOW until the UVLO threshold is reached, and then the output is outphase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high-state only if IN+ pin is high and IN– pin is low after the UVLO threshold is reached. Because the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application. VDD VDD Threshold VDD Threshold IN - IN+ IN+ IN- OUT OUT Figure 19. Power-Up (Non-Inverting Drive) 12 Figure 20. Power-Up (Inverting Drive) Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 Feature Description (continued) 9.3.2 Operating Supply Current The UCC27517A features very low quiescent IDD currents. The typical operating-supply current in UndervoltageLockout (UVLO) state and fully-on state (under static and switching conditions) are summarized in Figure 6, Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 5) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to switching and finally any current related to pullup resistors on the unused input pin. For example when the inverting input pin is pulled low additional current is drawn from VDD supply through the pull-up resistors (refer to Detailed Description for the device Block Diagram). Knowing the operating frequency (fSW) and the MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG and fSW. A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages under 1.8-nF switching load is provided in Figure 15. The strikingly-linear variation and close correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device attesting to the high-speed characteristics of IOUT. 9.3.3 Input Stage The input pins of the UCC27517A are based on a TTL and CMOS compatible input-threshold logic that is independent of the VDD supply voltage. With typical high threshold = 2.2 V and typ low threshold = 1.2 V, the logic-level thresholds can be conveniently driven with PWM-control signals derived from 3.3-V and 5-V digitalpower controllers. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTLlogic implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control of the input-pin threshold-voltage levels which eases system-design considerations and ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and increases switching speed. The device features an important protection function wherein, whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This is achieved using VDD-pullup resistors on all the inverting inputs (IN– pin) or GND-pulldown resistors on all the non-inverting input pins (IN+ pin), (refer to Functional Block Diagram section). The device also features a dual-input configuration with two input pins available to control the state of the output. The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin (IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. Refer to the input/output logic truth table (Table 4) and the Typical Application Diagrams, (Figure 22 and Figure 23), for additional clarification. Once an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating condition because, whenever any input pin is left in a floating condition, the output is disabled for protection purposes. Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as explained below. • In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In this case, the unused input pin, IN–, must be biased low (eg. tied to GND) in order to enable the output. – Alternately, the IN– pin can be used to implement the enable/disable function using an external logic signal. OUT is disabled when IN– is biased high and OUT is enabled when IN– is biased low. • In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN– pin. In this case, the unused input pin, IN+, must be biased high (eg. tied to VDD) in order to enable the output. – Alternately, the IN+ pin can be used to implement the enable/disable function using an external logic signal. OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high. • Finally, note that the output pin is driven into a high state only when IN+ pin is biased high and IN– input is biased low. The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be exercised whenever the driver is used with slowly-varying input signals, especially in situations where the device is located in a mechanical socket or PCB layout is not optimal: • High dI/dt current from the driver output coupled with board layout parasitics causes ground bounce. Because Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 13 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com Feature Description (continued) • • the device features just one GND pin, which may be referenced to the power ground, the differential voltage between input pins and GND is modified and triggers an unintended change of output state. Because of fast 13-ns propagation delay, high-frequency oscillations ultimately occur, which increases power dissipation and poses risk of damage. 1-V input-threshold hysteresis boosts noise immunity compared to most other industry-standard drivers. In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1 nF) between input pin and ground very close to the driver device is necessary. This helps to convert the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid unintended change of output state. If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate charge related power dissipation in the gate-driver device package and transferring the gate driver into the external resistor. 9.3.4 Enable Function As mentioned earlier, an enable or disable function is easily implemented in the UCC27517A using the unused input pin. When IN+ is pulled down to GND or IN– is pulled down to VDD, the output is disabled. Thus IN+ pin is used like an enable pin that is based on active-high logic, while IN– can be used like an enable pin that is based on active-low logic. 9.3.5 Output Stage The UCC27517A is capable of delivering 4-A source, 4-A sink (symmetrical drive) at VDD = 12 V. The output stage of the UCC27517A device is illustrated in Figure 21. The UCC27517A features a unique architecture on the output stage which delivers the highest peak-source current when most needed during the Miller-plateau region of the power-switch turnon transition (when the power-switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-Channel and PChannel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device delivers a brief boost in the peak-sourcing current enabling fast turnon. VCC ROH RNMOS, Pull Up Input Signal Anti ShootThrough Circuitry Gate Voltage Boost OUT Narrow Pulse at each Turn On ROL Figure 21. UCC27517A Gate Driver Output Structure The ROH parameter (see Electrical Characteristics) is a DC measurement and is representative of the onresistance of the P-Channel device only, since the N-Channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by ROH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The ROL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC27517A, the effective resistance of the hybrid pullup structure is approximately 1.4 × ROL. 14 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 Feature Description (continued) The driver-output voltage swings between VDD and GND providing rail-to-rail operation because of the MOS output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots. This means that in many cases, external Schottky-diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction. 9.3.6 Low Propagation Delays The UCC27517A features best-in-class input-to-output propagation delay of 13 ns (typ) at VDD = 12 V. This promises the lowest level of pulse-transmission distortion available from industry-standard gate-driver devices for high-frequency switching applications. As seen in Figure 14, there is very little variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns propagation delays across the entire range of application conditions. 9.4 Device Functional Modes The device operates in normal mode and UVLO mode. See the VDD and Undervoltage Lockout section for information on UVLO operation mode. In the normal mode the output state is dependent on states of the IN+ and IN– pins. Table 4 below lists the output states for different input pin combinations. Table 4. Device Logic Table (1) IN+ PIN IN– PIN OUT PIN L L L L H L H L H H H L x (1) Any L Any x (1) L x = Floating Condition Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A 15 UCC27517A SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power-semiconductor devices. Further, gate drivers are indispensable when there are times that the PWM controller cannot directly drive the gates of the switching devices. With advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which is not capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Because traditional buffer-drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, lack level-shifting capability, the circuits prove inadequate with digital power. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate-charge power losses into itself. Finally, emerging wide-bandgap power-device technologies, such as GaN based switches, which are capable of supporting very high switching frequency operation, are driving very special requirements in terms of gate-drive capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance packages with good thermal capability. In summary gate-driver devices are extremely important components in switching power combining benefits of high-performance, low cost, component count and board space reduction with a simplified system design. 10.2 Typical Application Typical application diagrams for the UCC27517A device are shown in Figure 22 and Figure 23 to illustrate use in non-inverting and inverting driver configurations. Non-Inverting Input Q1 UCC27517A-Q1 4.5 V to 18 V V+ R1 1 VDD 2 GND 3 IN+ OUT 5 IN- 4 C1 IN+ Figure 22. Using Non-Inverting Input (IN– is grounded to the enable output) 16 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: UCC27517A UCC27517A www.ti.com SLUSBQ0C – AUGUST 2013 – REVISED AUGUST 2015 Typical Application (continued) Inverting Input Q1 UCC27517A-Q1 4.5 V to 18 V V+ R1 1 VDD 2 GND 3 IN+ OUT 5 IN- 4 C1 VIN- Figure 23. Using Inverting Input (IN+ is tied to VDD enable output) 10.2.1 Design Requirements When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink cu