Datasheet · 2024

TI TPS26750 USB Type-C and USB PD (EPR) Controller — Datasheet (SLVSH67)

EPR controller; the on-board charger reference.

Author: Texas Instruments
Year: 2024
Type: Datasheet
Credit: Texas Instruments (ti.com)

usb pd
epr
controller

TPS26750 SLVSH67 – SEPTEMBER 2024 TPS26750 USB Type-C® and USB PD Controller With Integrated Power Switches Optimized for Power Applications 1 Features 3 Description • The TPS26750 is a highly integrated stand-alone USB Type-C and Power Delivery (PD) controller optimized for applications supporting USB-C PD Power. The TPS26750 integrates fully managed power paths with robust protection for a complete USB-C PD solution. The TPS26750 also integrates control for external battery charger ICs for added ease of use and reduced time to market. The intuitive web based GUI asks the user a few simple questions on the applications needs using clear block diagrams and simple multiple-choice questions. As a result, the GUI will create the configuration image for the user’s application, reducing much of the complexity associated with competitive USB PD solutions. • • • • • • This device is certified by the USB-IF for PD3.1 – PD3.1 silicon is required for certification of new USB PD designs – TPS26750 TID#: 11450 – Article on PD2.0 vs. PD3.0 Optimized for USB Type-C PD power applications – Integrated I2C control for TI battery chargers • Ex: In Development – Web-based GUI and pre-configured firmware – For a more extensive selection guide and getting started information, please refer to www.ti.com/usb-c and E2E guide Extended Power Range (EPR) – Supports EPR source and sink – EPR 28V, 36V, 48V, and AVS Programmable Power Supply(PPS) – Supports PPS source and sink – Standalone PPS source control TI battery chargers – Programmable interface for PPS sink Liquid Detection – Measures directly at the Type-C connector – Integrated error handling and protection Integrated fully managed power path & protection – Integrated 5V, 3A, and 36mΩ sourcing switch – Integrated undervoltage and overvoltage protection and current limiting for inrush current protection for the 5V and 3A source power path – 26V tolerant CC pins for robust protection when connected to non-compliant devices USB Type-C® Power Delivery (PD) controller – 10 configurable GPIOs – BC1.2 charging support – 3.3V LDO output for dead battery support – Power supply from 3.3V or VBUS source – 1 I2C primary port – 1 I2C secondary port Package Information PACKAGE(1) PART NUMBER TPS26750 (1) (2) RSM (QFN, 32) PACKAGE SIZE(2) 4mm × 4mm For all available packages, see the orderable addendum at the end of the data sheet. The package size (length × width) is a nominal value and includes pins, where applicable. 5A SW 5-48 V GPIO 3.3V LDO TPS26750 VBUS 5V 3A 3.3V TPD4S480 Optional Embedded Controller I2C Target BQ Battery Charger I2C Controller Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer 2 CC CC1/2 VCONN GND 10 GPIO Simplified Schematic 2 Applications • • • Power tools, power banks, retail automation and payment Wireless speakers, headphones Other personal electronics and industrial applications An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 5 5.1 Absolute Maximum Ratings........................................ 5 5.2 ESD Ratings............................................................... 5 5.3 Recommended Operating Conditions.........................6 5.4 Recommended Capacitance.......................................6 5.5 Thermal Information....................................................7 5.6 Power Supply Characteristics..................................... 7 5.7 Power Consumption....................................................7 5.8 PP_5V Power Switch Characteristics......................... 8 5.9 POWER_PATH_EN Characteristics - TPS26750 ...... 9 5.10 Power Path Supervisory........................................... 9 5.11 CC Cable Detection Parameters...............................9 5.12 CC VCONN Parameters......................................... 10 5.13 CC PHY Parameters............................................... 11 5.14 Thermal Shutdown Characteristics......................... 11 5.15 ADC Characteristics................................................12 5.16 Input/Output (I/O) Characteristics........................... 12 5.17 BC1.2 Characteristics............................................. 12 5.18 I2C Requirements and Characteristics................... 13 2 5.19 Typical Characteristics ........................................... 15 6 Parameter Measurement Information.......................... 16 7 Detailed Description......................................................17 7.1 Overview................................................................... 17 7.2 Functional Block Diagram......................................... 18 7.3 Feature Description...................................................19 7.4 Device Functional Modes..........................................33 7.5 Thermal Shutdown....................................................35 8 Application and Implementation.................................. 36 8.1 Application Information............................................. 36 8.2 Typical Application.................................................... 36 8.3 Power Supply Recommendations.............................51 8.4 Layout....................................................................... 52 9 Device and Documentation Support............................60 9.1 Device Support......................................................... 60 9.2 Documentation Support............................................ 60 9.3 Support Resources................................................... 60 9.4 Trademarks............................................................... 60 9.5 Electrostatic Discharge Caution................................60 9.6 Glossary....................................................................60 10 Revision History.......................................................... 60 11 Mechanical, Packaging, and Orderable Information.................................................................... 60 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS CC2 32 31 30 29 28 27 26 25 4 Pin Configuration and Functions LDO_3V3 1 24 CC1 ADCIN1 2 23 GPIO5/USB_N/LD2 ADCIN2 3 22 GPIO4/USB_P/LD1 21 NC 20 POWER_PATH_EN Thermal Pad (GND) 15 16 GND I2Cc_SDA I2Cc_SCL I2Cc_IRQ 14 17 13 8 GND I2Ct_SDA GPIO11 GPIO3 12 GND 18 11 19 7 GND 6 GPIO2 I2Ct_IRQ GPIO1 10 5 9 4 GPIO0 I2Ct_SCL LDO_1V5 Not to Scale Figure 4-1. TPS26750 RSM Package, 32-Pin QFN (Top View) Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 3 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 Table 4-1. TPS26750 Pin Functions PIN TYPE(1) RESET 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 24 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 25 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). POWER_PATH_EN 20 O Hi-Z Power path enable for external load switch. Leave floating when unused. This is NOT a logic voltage level output. GND 11, 12, 14 — — Ground. Connect to ground plane. GPIO0 5 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO1 6 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO2 7 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO3 18 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO4/USB_P/LD1 22 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. This can be connected to D+ for BC1.2 support. GPIO5/USB_N/LD2 23 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. This can be connected to D- for BC1.2 support. GPIO6 31 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO7 30 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Ct_SCL 9 I Hi-Z I2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_SDA 8 I/O Hi-Z I2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_IRQ 10 O Hi-Z I2C target interrupt. Active low. Connect to external voltage through a pull-up resistor. This can be re-configured to GPIO10. Tie to ground when unused. I2Cc_SCL 16 O Hi-Z I2C controller serial clock. Open-drain output. Tie to pullup voltage through a resistor when used or unused. GPIO11 13 O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Cc_SDA 15 I/O Hi-Z I2C controller serial data. Open-drain input/output. Tie to pullup voltage through a resistor when used or unused. I2Cc_IRQ 17 I Hi-Z I2C controller interrupt. Active low. Connect to external voltage through a pull-up resistor. Do NOT tie to GND when unused. This can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. NAME NO. ADCIN1 ADCIN2 DESCRIPTION PP5V 28, 29 I — 5V System Supply to VBUS, supply for CCy pins as VCONN. VSYS 19 I — Tie to GND. Used as a reference for POWER_PATH_EN. VBUS 26, 27 I/O VIN_3V3 32 I 5V to 20V input. Bypass with capacitance CVBUS to GND. — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. (1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5 Specifications 5.1 Absolute Maximum Ratings 5.1.1 TPS26750 - Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) Input voltage range(2) Output voltage range(2) MIN MAX PP5V –0.3 6 VIN_3V3 –0.3 4 ADCIN1, ADCIN2 –0.3 4 VBUS_IN, VBUS(4) –0.3 28 CC1, CC2(4) –0.5 26 GPIOx –0.3 6.0 I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ, I2Ct_SCL, I2Ct_SDA –0.3 4 LDO_1V5(3) –0.3 2 LDO_3V3(3) –0.3 4 Source or sink current VBUS Source current Source current UNIT V V V internally limited Positive source current on CC1, CC2 1 Positive sink current on CC1, CC2 while VCONN switch is enabled 1 Positive sink current for I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ, I2Ct_SCL, I2Ct_SDA internally limited Positive source current for LDO_3V3, LDO_1V5 internally limited GPIOx A 0.005 A TJ Operating junction temperature –40 175 °C TSTG Storage temperature –55 150 °C (1) (2) (3) (4) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Do not apply voltage to these pins. A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200. 5.1.2 TPS26750 - Absolute Maximum Ratings POWER_PATH_EN VVSYS = GND MIN MAX –0.5 12 TEST CONDITIONS VALUE UNIT V 5.2 ESD Ratings PARAMETER V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) ±1000 Charged-device model (CDM), per ANSI/ ESDA/JEDEC JS-002, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 5 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.3.1 TPS26750 - Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) Input voltage range(1) VI I/O voltage range(1) VIO MAX 3.0 3.6 PP5V 4.9 5.5 VBUS 4 22 VSYS 0 22 I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 GPIOx 0 5.5 CC1, CC2 0 5.5 VBUS IO Output current (from PP5V) IO Output current (from LDO_3V3) IO Output current (from VBUS LDO) TA Ambient operating temperature TJ Operating junction temperature (1) MIN VIN_3V3 UNIT V V 3 A 315 mA GPIOx 1 mA sum of current from LDO_3V3 and GPIOx 5 mA CC1, CC2 IPP_5V ≤ 1.5A, IPP_CABLE ≤ 315mA –40 105 IPP_5V ≤ 3A, IPP_CABLE ≤ 315mA –40 85 –40 125 °C °C All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. 5.4 Recommended Capacitance over operating free-air temperature range (unless otherwise noted) PARAMETER(1) MIN NOM 5 10 6.3V 5 10 4V 4.5 Capacitance on VIN_3V3 6.3V CLDO_3V3 Capacitance on LDO_3V3 CLDO_1V5 Capacitance on LDO_1V5 CVBUS Capacitance on VBUS(4) 25V 1 CPP5V Capacitance on PP5V 10V 120(2) CCCy Capacitance on CCy pins(3) 6.3V 200 (1) (2) (3) (4) 6 VOLTAGE RATING CVIN_3V3 4.7 MAX UNIT µF 25 µF 12 µF 10 µF µF 400 480 pF Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by 50% at the required operating voltage, then the required external capacitor value would be 10 µF. This is a requirement from USB PD (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V. This includes all external capacitance to the Type-C receptacle. The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a capacitance on the higher side of this range is recommended. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.5 Thermal Information 5.5.1 TPS26750 - Thermal Information TPS26750 THERMAL METRIC(1) QFN (RSM) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 30.5 °C/W RθJC (top) Junction-to-case (top) thermal resistance 24.5 °C/W RθJC Junction-to-board (bottom) thermal resistance 2 °C/W RθJB Junction-to-board thermal resistance 9.8 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 5.6 Power Supply Characteristics Operating under these conditions unless otherwise noted: 3.0V ≤ VVIN_3V3 ≤ 3.6V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN_3V3, VBUS VVBUS_UVLO VBUS UVLO threshold rising 3.6 falling 3.5 3.9 3.8 hysteresis rising, VVBUS = 0 Voltage required on VIN_3V3 for falling, VVBUS = 0 power on hysteresis VVIN3V3_UVLO V 0.1 2.56 2.66 2.76 2.44 2.54 2.64 V 3.6 V 1.4 Ω 1.65 V 0.12 LDO_3V3, LDO_1V5 VLDO_3V3 Voltage on LDO_3V3 VVIN_3V3 = 0V, 10µA ≤ ILOAD ≤ 18mA, VBUS ≥ 3.9V RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50mA Voltage on LDO_1V5 up to maximum internal loading condition VLDO_1V5 3.0 3.4 1.49 1.5 5.7 Power Consumption Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVIN_3V3,ActSrc Current into VIN_3V3 Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 3 IVIN_3V3,ActSnk Current into VIN_3V3 Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 3 mA IVIN_3V3,IdlSrc Current into VIN_3V3 Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 1.0 mA IVIN_3V3,IdlSnk Current into VIN_3V3 Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 1.0 mA PMstbySnk Power drawn into PP5V CCm floating, VCCn = 0.4 V, VPP5V = 5 V, VVIN_3V3 = 3.3 V, and VIN_3V3 in Modern VVBUS = 5.0 V, POWER_PATH_EN disabled, and TJ = 25°C Standby Sink Mode 4.1 mW PMstbySrc Power drawn into PP5V CCm floating, CCn tied to GND through 5.1 kΩ, VPP5V = 5 and VIN_3V3 in Modern V, VVIN_3V3 = 3.3 V, IVBUS = 0, TJ = 25°C Standby Source Mode 4.5 mW IPP5V,Sleep Current into PP5V Sleep mode: VPA_VBUS = 0 V, VVIN_3V3 = 3.3 V 2 µA IVIN_3V3,Sleep Current into VIN_3V3 Sleep mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 56 µA 6 mA Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 7 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.8 PP_5V Power Switch Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER 8 TEST CONDITIONS MIN TYP MAX UNIT RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A, TJ = 25°C 36 38 mΩ RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A,TJ = 125°C 36 53 mΩ IPP5V_REV VBUS to PP5V leakage current VPP5V = 0 V, VVBUS = 5.5 V, PP_5V disabled, TJ ≤ 85°C, measure IPP5V 5 µA IPP5V_FWD PP5V to VBUS leakage current VPP5V = 5.5 V, VVBUS = 0 V, PP_5V disabled, TJ ≤ 85°C, measure IVBUS 15 µA ILIM5V Current limit setting Configure to setting 0 1.15 1.36 A ILIM5V Current limit setting Configure to setting 1 1.61 1.90 A ILIM5V Current limit setting 2.3 2.70 A ILIM5V Current limit setting Configure to setting 3 3.04 3.58 A ILIM5V Current limit setting Configure to setting 4 3.22 3.78 A IVBUS PP5V to VBUS current sense accuracy 3.64 A ≥ IVBUS ≥ 1 A 3.05 3.75 A/V VPP_5V_RCP RCP clears and PP_5V starts turning on when VVBUS – VPP5V < VPP_5V_RCP. Measure VVBUS – VPP5V 20 mV tiOS_PP_5V Response time to VBUS short circuit VBUS to GND through 10 mΩ, CVBUS = 0 1.15 µs tPP_5V_ovp Response time to VVBUS > VOVP4RCP Enable PP_5V, IRpDef being drawn from PP5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4V to 20 V at 100 V/ms, CPP5V = 2.5 µF, measure time from OVP detection until reverse current < 100 mA 4.5 µs tPP_5V_uvlo Response time to VPP5V < R = 100 Ω, no external VPP5V_UVLO, PP_VBUS is deemed off L capacitance on VBUS when VVBUS < 0.8 V 4 µs 0.7 µs 5.1 ms 3.5 10 VPP5V = 5.5 V, IRpDef being drawn from PP5V, enable PP_5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4 V to 21.5 V at 10 V/µs, measure VPP5V. CPP5V = 104 µF, CVBUS=10 µF, measure time from RCP detection until reverse current < 100 mA tPP_5V_rcp Response time to VPP5V < VVBUS + VPP_5V_RCP tILIM Current clamping deglitch time tON From enable signal to VBUS at 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 2.3 3.3 4.3 ms tOFF From disable signal to VBUS at 10% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.30 0.45 0.6 ms tRISE VBUS from 10% to 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 1.2 1.7 2.2 ms tFALL VBUS from 90% to 10% of initial value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.06 0.1 0.14 ms Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.9 POWER_PATH_EN Characteristics - TPS26750 Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPOWER_PATH_EN Sourcing current VGATE_VSYS = 0 V 8.5 11.5 µA VPOWER_PATH_EN Sourcing voltage (ON) VVSYS = 0 V, 6 12 V IPOWER_PATH_EN Sinking strength VVSYS = 0 V 13 µA 5.10 Power Path Supervisory Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VPP5V_UVLO TEST CONDITIONS Voltage required on PP5V MIN TYP MAX rising 3.9 4.1 4.3 falling 3.8 4.0 4.2 V 15 mA MAX UNIT hysteresis IDSCH VVBUS = 22 V, measure IVBUS VBUS discharge current UNIT 0.1 4 5.11 CC Cable Detection Parameters Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP Type-C Source (Rp pullup) VOC_3.3 Unattached CCy open circuit voltage while Rp enabled, no load VLDO_3V3 > 2.302 V, RCC = 47 kΩ 1.85 V VOC_5 Attached CCy open circuit voltage while Rp enabled, no load VPP5V > 3.802 V, RCC = 47 kΩ 2.95 V IRev Unattached reverse current on CCy VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 3.8 V, measure current into CCy 10 VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 0, TJ ≤ 85°C, measure current into CCy 10 µA IRpDef Current source - USB Default 0 < VCCy < 1.0 V, measure ICCy 64 80 96 µA IRp1.5 Current source - 1.5 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 1.5 V, measure ICCy 166 180 194 µA IRp3.0 Current source - 3.0 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 2.45 V, measure ICCy 304 330 356 µA Type-C Sink (Rd pulldown) VSNK1 Open/Default detection threshold when Rd applied to CCy rising 0.2 0.24 V VSNK1 Open/Default detection threshold when Rd applied to CCy falling 0.16 0.20 V Default/1.5-A detection threshold falling 0.62 Default/1.5-A detection threshold rising 0.63 Hysteresis VSNK2 VSNK2 VSNK3 0.04 Hysteresis 0.66 V 0.68 V 0.69 V 0.01 1.5-A/3.0-A detection threshold when Rd applied to CCy falling 1.17 V 1.25 V Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 9 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.11 CC Cable Detection Parameters (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VSNK3 TEST CONDITIONS 1.5-A/3.0-A detection threshold when Rd applied to CCy MIN rising TYP 1.22 Hysteresis MAX UNIT 1.3 V 0.05 V RSNK Rd pulldown resistance 0.25 V ≤ VCCy ≤ 2.1 V, measure resistance on CCy 4.6 5.6 kΩ RVCONN_DIS VCONN discharge resistance 0V ≤ VCCy ≤ 5.5 V, measure resistance on CCy 4.0 6.12 kΩ VVIN_3V3 = 0 V, 64 µA < ICCy < 96 µA 0.25 1.32 VVIN_3V3 = 0 V, 166 µA < ICCy < 194 µA 0.65 1.32 VVIN_3V3 = 0 V, 304 µA < ICCy < 356 µA 1.20 2.18 VVBUS = 0, VVIN_3V3 = 3.3 V, VCCy = 5 V, measure resistance on CCy 500 kΩ VVBUS = 5 V, VVIN_3V3 = 0, VCCy = 5 V, measure resistance on CCy 500 kΩ VCLAMP ROpen Dead battery Rd clamp Resistance from CCy to GND when configured as open V 5.12 CC VCONN Parameters Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 Ω RPP_CABLE Rdson of the VCONN path VPP5V = 5 V, IL = 250 mA, measure resistance from PP5V to CCy ILIMVC Short circuit current limit Setting 0, VPP5V = 5 V, RL=10 mΩ, measure ICCy 350 410 470 mA ILIMVC Short circuit current limit Setting 1, VPP5V = 5 V, RL=10 mΩ, measure ICCy 540 600 660 mA ICC2PP5V Reverse leakage current through VCONN FET VCONN disabled, TJ ≤ 85°C, VCCy = 5.5 V, VPP5V = 0 V, VVBUS = 5 V, LDO forced to draw from VBUS, measure ICCy 10 µA VVC_OVP Overvoltage protection threshold for PP_CABLE VPP5V rising 5.6 5.9 6.2 V VPP5V ≥ 4.9 V, VCCy = VPP5V, VCCx rising 60 200 340 mV VVC_RCP Reverse current protection threshold for PP_CABLE, sourcing VCONN through CCx VPP5V ≥ 4.9 V, VCCy ≤ 4 V, VCCx rising 210 340 470 mV tVCILIM Current clamp deglitch time 1.3 ms tPP_CABLE_FSD Time to disable PP_CABLE after VPP5V > VVC_OVP or VCCx - CL = 0 VPP5V > VVC_RCP 0.5 µs tPP_CABLE_off From disable signal to CCy at 10% of final value IL = 250 mA, VPP5V = 5 V, CL = 0 tiOS_PP_CABLE Response time to short circuit VPP5V = 5 V, for short circuit RL = 10 mΩ 10 Submit Document Feedback 100 200 2 300 µs µs Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.13 CC PHY Parameters Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.125 1.2 V 75 mV 75 Ω Transmitter VTXHI Transmit high voltage on CCy Standard External load 1.05 VTXLO Transmit low voltage on CCy Standard External load –75 ZDRIVER Transmit output impedance while driving the CC line using CCy measured at 750 kHz 33 tRise Rise time. 10 % to 90 % amplitude points on CCy, minimum is under CCCy = 520 pF an unloaded condition. Maximum set by TX mask 300 ns tFall Fall time. 90 % to 10 % amplitude points on CCy, minimum is under an unloaded condition. Maximum set by TX mask CCCy = 520 pF 300 ns VPHY_OVP OVP detection threshold for USB PD PHY 0 ≤ VVIN_3V3 ≤ 3.6 V, 0 ≤ VPP5V ≤ 5.5 V, VVBUS ≥ 4 V. Initially VCC1 ≤ 5.5 V and VCC2 ≤ 5.5 V, then VCCx rises 5.5 54 8.5 V Receiver ZBMCRX Does not include pullup or Receiver input impedance on CCy pulldown resistance from cable detect. Transmitter is Hi-Z CCC Receiver capacitance on CCy VRX_SNK_R Rising threshold on CCy for receiver comparator Sink mode (rising) 499 VRX_SRC_R Rising threshold on CCy for receiver comparator Source mode (rising) VRX_SNK_F Falling threshold on CCy for receiver comparator VRX_SRC_F Falling threshold on CCy for receiver comparator (1) (1) 1 MΩ Capacitance looking into the CC pin when in receiver mode 120 pF 525 551 mV 784 825 866 mV Sink mode (falling) 230 250 270 mV Source mode (falling) 523 550 578 mV CCC includes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding CCCy externally. 5.14 Thermal Shutdown Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Temperature rising TSD_MAIN Temperature shutdown threshold TSD_PP5V Temperature controlled shutdown Temperature rising threshold. The power paths for each port sourcing from PP5V and PP_CABLE power paths have Hysteresis local sensors that disables them when the temperature is exceeded MIN TYP MAX UNIT 145 160 175 °C 135 150 Hysteresis 15 10 °C 165 °C °C Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 11 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.15 ADC Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER LSB TEST CONDITIONS Least significant bit MIN TYP 14 mV 25.2-V max scaling, voltage divider of 21 98 mV 16.5 mA 0.05 V ≤ VADCINx ≤ 3.6 V, VADCINx ≤ VLDO_3V3 –2.7 2.7 2.7 V ≤ VLDO_3V3 ≤ 3.6 V –2.4 2.4 0.6 V ≤ VVBUS ≤ 22 V –2.1 2.1 1 A ≤ IVBUS ≤ 3 A –2.1 2.1 –4.1 4.1 0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx ≤ VLDO_3V3 Gain error 0.05 V ≤ VADCINx ≤ 3.6 V, VADCINx ≤ VLDO_3V3 VOS_ERR (1) Offset error 0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx ≤ VLDO_3V3 (1) UNIT 3.6-V max scaling, voltage divider of 3 4.07-A max scaling GAIN_ERR MAX % mV 2.7 V ≤ VLDO_3V3 ≤ 3.6 V –4.5 4.5 0.6 V ≤ VVBUS ≤ 22 V –4.1 4.1 1 A ≤ IVBUS ≤ 3 A –4.5 4.5 mA MAX UNIT The offset error is specified after the voltage divider. 5.16 Input/Output (I/O) Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP USB_P, USB_N GPIO_VIH GPIOx high-Level input voltage VLDO_3V3 = 3.3 V GPIO_VIL GPIOx low-level input voltage VLDO_3V3 = 3.3 V 1.3 GPIO_HYS GPIOx input hysteresis voltage VLDO_3V3 = 3.3 V 0.09 GPIO_ILKG GPIOx leakage current VGPIOx = 3.45 V –1 GPIO_RPU GPIOx internal pullup Pullup enabled 50 GPIO_RPD GPIOx internal pulldown Pulldown enabled 50 GPIO_DG GPIOx input deglitch V 0.54 V 1 µA 100 150 kΩ 100 150 kΩ 20 50 ns V GPIO0-7 (Outputs) GPIO_VOH GPIOx output high voltage VLDO_3V3 = 3.3 V, IGPIOx= -2 mA GPIO_VOL GPIOx output low voltage VLDO_3V3 = 3.3 V, IGPIOx = 2 mA ADCIN_ILKG ADCINx leakage current VADCINx ≤ VLDO_3V3 tBOOT Time from LDO_3V3 going high until ADCINx is read for configuration 2.9 V 0.4 V 1 µA ADCIN1, ADCIN2 –1 10 ms 5.17 BC1.2 Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 7 10 13 µA DATA CONTACT DETECT IDP_SRC 12 DCD source current VLDO_3V3 = 3.3 V Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.17 BC1.2 Characteristics (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V MIN TYP MAX UNIT RDM_DWN DCD pulldown resistance PARAMETER VUSB_N = 3.6 V TEST CONDITIONS 14.25 20 24.8 kΩ RDP_DWN DCD pulldown resistance VUSB_P = 3.6 V 14.25 20 24.8 kΩ VLGC_HI Threshold for no connection VUSB_P ≥ VLGC_HI, VLDO_3V3 = 3.3 V, RUSB_P = 300 kΩ 2 3.6 V VLGC_LO Threshold for connection VUSB_N ≤ VLGC_LO, VLDO_3V3 = 3.3 V, RUSB_P = 24.8 kΩ 0 0.8 V Advertisement and Detection VDX_ILIM VDX_SRC current limit 400 µA IDX_SNK Sink Current VUSB_P ≥ 250 mV 25 75 125 µA IDX_SNK Sink Current VUSB_N ≥ 250 mV 25 75 125 µA Dedicated Charging Port Resistance 0.5 V ≤ VUSB_P ≤ 0.7 V, 25 µA ≤ IUSB_N ≤ 175 µA 200 Ω MAX UNIT 0.4 V 1 µA RDCP_DAT 250 5.18 I2C Requirements and Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP I2Ct_IRQ OD_VOL_IRQ Low level output voltage IOL = 2 mA OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45 V IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3 V 1.3 IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3 V 0.72 IRQ_VIL low-level input voltage VLDO_3V3 = 3.3 V IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3 V 0.54 IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3 V 0.09 IRQ_DEG input deglitch IRQ_ILKG I2Cc_IRQ leakage current –1 I2Cc_IRQ V 1.3 V 0.54 V 1.08 V V 20 VI2Cc_IRQ = 3.45 V –1 ns 1 µA SDA and SCL Common Characteristics (Controller, Target) VIL Input low signal VLDO_3V3 = 3.3 V IOL Max output low current VOL = 0.4 V 15 0.54 V IOL Max output low current VOL = 0.6 V 20 tf Fall time from 0.7 × VDD to 0.3 × VDD VDD = 1.8 V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns VDD = 3.3 V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns tSP I2C pulse width suppressed 50 ns Cb Capacitive load for each bus line (external) 400 pF mA mA SDA and SCL Standard Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 kHz tVD;DAT Valid data time Transmitting Data, VDD = 1.8 V or 3.3 V, SCL low to SDA output valid 3.45 µs tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8 V or 3.3 V, ACK signal from SCL low to SDA (out) low 3.45 µs 400 kHz SDA and SCL Fast Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8 V or 3.3 V 100 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 13 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 5.18 I2C Requirements and Characteristics (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.9 µs 0.9 µs 800 kHz tVD;DAT Valid data time Transmitting data, VDD = 1.8 V, SCL low to SDA output valid tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or 3.3 V, ACK signal from SCL low to SDA (out) low fSCLS Clock frequency for Fast Mode Plus(1) VDD = 1.8 V or 3.3 V tVD;DAT Valid data time Transmitting data, VDD = 1.8 V or 3.3 V, SCL low to SDA output valid 0.55 µs tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8 V or 3.3 V, ACK signal from SCL low to SDA (out) low 0.55 µs tLOW Clock low time VDD = 3.3 V 1.3 µs tHIGH Clock high time VDD = 3.3 V 0.6 µs (1) Controller must control fSCLS to ensure tLOW > tVD; ACK. 14 Submit Document Feedback 400 Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 50 1.05 48 1 46 0.95 44 RPP_CABLE (:) RPP_5V (m:) 5.19 Typical Characteristics 42 40 38 0.9 0.85 0.8 0.75 36 0.7 34 0.65 32 -20 0 20 40 60 TJ (oC) 80 100 120 140 TypG Figure 5-1. PP_5V Rdson vs Temperature 0.6 -20 0 20 40 60 TJ (oC) 80 100 120 140 TypG Figure 5-2. PP_CABLE Rdson vs Temperature Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 15 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 6 Parameter Measurement Information tf SDA tr tSU;DAT 70 % 30 % 70 % 30 % cont. tHD;DAT tf tVD;DAT tHIGH tr 70 % 30 % SCL 70 % 30 % 70 % 30 % tHD;STA 70 % 30 % cont. tLOW 9th clock 1 / fSCL S 1st clock cycle tBUF SDA tSU;STA tHD;STA tVD;ACK tSP tSU;STO 70 % 30 % SCL Sr P 9th clock S 002aac938 Figure 6-1. I2C Target Interface Timing ILIM5V, ILIMVC tiOS_PP_5V, tiOS_PP_CABLE Figure 6-2. Short-circuit Response Time for Internal Power Paths PP_5V and PP_CABLE 16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 7 Detailed Description 7.1 Overview The TPS26750 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for USB Type-C and PD receptacles. The TPS26750 communicates with the cable and another USB Type-C and PD device at the opposite end of the cable. The device also enables integrated port power switch for sourcing, and controls a high current port power switch for sinking. The TPS26750 is divided into several main sections: • • • • • USB-PD controller Cable plug and orientation detection circuitry Port power switches Power management circuitry Digital core The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the CC1 pin or the CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features, and more detailed circuitry, see USB-PD Physical Layer. The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features, and more detailed circuitry, see Cable Plug and Orientation Detection. The port power switches provide power to the VBUS pin and CC1 or CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its features, and more detailed circuitry, see Power Paths. The power management circuitry receives and provides power to the TPS26750 internal circuitry and LDO_3V3 output. See Power Management for more information. The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as handling control of all other TPS26750 functionality. A portion of the digital core contains ROM memory, which contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the ROM, called boot code, is capable of initializing the TPS26750, loading of the device configuration information, and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the digital core, a description of its features, and more detailed circuitry, see Digital Core. The TPS26750 has one I2C controller to write to and read from external target devices such as a battery charger or an optional external EEPROM memory (see I2C Interface). The TPS26750 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the integrated oscillator. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 17 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 POWER_PATH_EN 7.2 Functional Block Diagram VBUS PP5V LDO_3V3 VSYS LDO_1V5 Power Supervisor VIN_3V3 GND ADCIN1 ADCIN2 I2Ct_SDA/SCL/IRQ Core & Other Digital CC1 I2Cc_SDA/SCL/IRQ GPIOx 18 Cable Detect, Cable Power, & USB PD PHY Submit Document Feedback CC2 Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 7.3 Feature Description 7.3.1 USB-PD Physical Layer Figure 7-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. Fast current limit IVCON PP5V CC1 Gate Control and Current Limit LDO_3V3 IRp RSNK CC1 Digital Core USB-PD PHY (Rx/Tx) CC2 LDO_3V3 IRp RSNK CC1 Gate Control and Current Limit Fast current limit Figure 7-1. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS26750 19 TPS26750 www.ti.com SLVSH67 – SEPTEMBER 2024 USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output on the same pin (CC1 or CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism. 7.3.1.1 USB-PD Encoding and Signaling Figure 7-2 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 7-3 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Encoder Data BMC Encoder to PD_TX CRC Figure 7-2. USB-PD Baseband Transmitter Block Diagram BMC Decoder from PD_RX SOP Detect Data 4b5b Decoder CRC Figure 7-3. USB-PD Baseband Receiver Block Diagram 7.3.1.2 USB-PD Bi-Phase Marked Coding The USB-PD physical layer implemented in the TPS26750 is compliant to the USB-PD Specifications. The encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity (limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 7-4 illustrates Biphase Mark Coding. 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 Data in BMC Figure 7-4. Biphase Mark Coding Example The USB PD baseband signal is driven onto the CC1 or CC2 pin with a tri-state driver. The tri-state driver is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the loss of the first edge. The transmitt