Datasheet · 2024

TI TPS25751 USB Type-C and USB PD Controller with Integrated Power Switches — Datasheet (SLVSH93A)

The proposed in-gun sink (UP-6).

Author: Texas Instruments
Year: 2024
Type: Datasheet
Credit: Texas Instruments (ti.com)

usb pd
controller

TPS25751 SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 TPS25751 USB Type-C® and USB PD Controller with Integrated Power Switches Optimized for Power Applications 1 Features 2 Applications • • • • • • • • • • • PD Controller is certified by the USB-IF for PD3.1 – PD3.1 silicon is required for certification of new USB PD designs – TPS25751 TID#: 10306 – Article on PD2.0 vs. PD3.0 Optimized for USB Type-C PD power applications – Integrated I2C control for TI battery chargers • BQ25756, BQ25756E, BQ25790, BQ25792 • BQ25798, BQ25713, BQ25731 – Web-based GUI and pre-configured firmware – Optimized for power consumer only (sink) (UFP) applications – Optimized for power provider/power consumer (DRP) applications – For a more extensive selection guide and getting started information, please refer to www.ti.com/usb-c and E2E guide Programmable Power Supply (PPS) – Supports PPS source & sink – Standalone PPS source control TI battery chargers – Programmable interface for PPS sink Liquid Detection – Measures directly at the Type-C connector – Integrated error handling and protection Integrated fully managed power paths – Integrated 5V, 3A, 36mΩ sourcing switch (TPS25751S and TPS25751D) – Integrated 20V, 5A, 16mΩ bi-directional load switch (TPS25751D only) Integrated robust power path protection – Integrated reverse current protection, undervoltage protection, overvoltage protection, and slew rate control the high-voltage bidirectional power path – Integrated undervoltage and overvoltage protection and current limiting for inrush current protection for the 5V/3A source power path – 26V tolerant CC pins for robust protection when connected to non-compliant devices USB Type-C® Power Delivery (PD) controller – 10 configurable GPIOs – BC1.2 advertisement/detection support – 3.3V LDO output for dead battery support – Power supply from 3.3V or VBUS source – 1 I2C controller port – 1 I2C target port Power tools, power banks, retail and payment Wireless speakers, Cordless vacuum cleaner personal electronics and industrial applications Home health care and Personal care and fitness 3 Description The TPS25751 is a highly integrated stand-alone USB Type-C and Power Delivery (PD) controller optimized for applications supporting USB-C PD Power. The TPS25751 integrates fully managed power paths with robust protection for a complete USB-C PD solution. The TPS25751 also integrates control for external battery charger ICs for added ease of use and reduced time to market. The intuitive web based GUI asks the user a few simple questions on the applications needs using clear block diagrams and simple multiple-choice questions. As a result, the GUI creates the configuration image for the user’s application, reducing much of the complexity associated with competitive USB PD solutions. Package Information PACKAGE(1) PART NUMBER PACKAGE SIZE(2) TPS25751D QFN (REF) 4.0mm x 6.0mm TPS25751S QFN (RSM) 4.0mm x 4.0mm (1) For all available packages, see the orderable addendum at the end of the data sheet. The package size (length × width) is a nominal value and includes pins, where applicable. (2) 5A 5-20 V LDO 3.3V TPS25751D VBUS 5V 3A 3.3V Optional Embedded Controller I2C Target BQ Battery Charger I2C Controller Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer CC1/2 CC VCONN 2 GND 10 GPIO 5-20 V PP_EXT Control 3.3V LDO TPS25751S VBUS 5V 3A 3.3V Optional Embedded Controller I2C Target BQ Battery Charger I2C Controller Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer CC1/2 CC VCONN 2 GND 10 GPIO An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Device Comparison Table...............................................3 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 7 6.1 Absolute Maximum Ratings........................................ 7 6.2 ESD Ratings............................................................... 8 6.3 Recommended Operating Conditions.........................8 6.4 Recommended Capacitance.......................................9 6.5 Thermal Information..................................................10 6.6 Power Supply Characteristics................................... 11 6.7 Power Consumption..................................................11 6.8 PP_5V Power Switch Characteristics....................... 11 6.9 PPHV Power Switch Characteristics - TPS25751D..12 6.10 PP_EXT Power Switch Characteristics TPS25751S................................................................. 13 6.11 Power Path Supervisory..........................................14 6.12 CC Cable Detection Parameters.............................14 6.13 CC VCONN Parameters......................................... 15 6.14 CC PHY Parameters...............................................16 6.15 Thermal Shutdown Characteristics......................... 17 6.16 ADC Characteristics................................................17 6.17 Input/Output (I/O) Characteristics........................... 17 6.18 BC1.2 Characteristics............................................. 18 2 6.19 I2C Requirements and Characteristics................... 18 6.20 Typical Characteristics ........................................... 20 7 Parameter Measurement Information.......................... 22 8 Detailed Description......................................................23 8.1 Overview................................................................... 23 8.2 Functional Block Diagram......................................... 23 8.3 Feature Description...................................................26 8.4 Device Functional Modes..........................................44 8.5 Thermal Shutdown....................................................46 9 Application and Implementation.................................. 47 9.1 Application Information............................................. 47 9.2 Typical Application.................................................... 47 9.3 Power Supply Recommendations.............................59 9.4 Layout....................................................................... 60 10 Device and Documentation Support..........................74 10.1 Device Support....................................................... 74 10.2 Documentation Support.......................................... 74 10.3 Receiving Notification of Documentation Updates..74 10.4 Support Resources................................................. 74 10.5 Trademarks............................................................. 74 10.6 Electrostatic Discharge Caution..............................74 10.7 Glossary..................................................................74 11 Revision History.......................................................... 75 12 Mechanical, Packaging, and Orderable Information.................................................................... 75 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 4 Device Comparison Table DEVICE NUMBER 5-V SOURCE LOAD SWITCH INTEGRATED HIGH VOLTAGE BI-DIRECTIONAL LOAD SWITCH (PPHV) HIGH VOLTAGE GATE DRIVER FOR BI-DIRECTIONAL EXTERNAL PATH (PP_EXT) TPS25751D Yes Yes No TPS25751S Yes No Yes Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 3 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 5 Pin Configuration and Functions VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS GND DRAIN CC2 CC1 GPIO5/USB_N/ LD2 GPIO4/USB_P/ LD1 38 37 36 35 34 33 32 31 30 29 28 27 26 LDO_3V3 1 25 VBUS_IN ADCIN1 2 24 VBUS_IN ADCIN2 3 23 VBUS_IN LDO_1V5 4 22 PPHV GPIO0 5 21 PPHV GPIO1 6 20 PPHV Thermal Pad (DRAIN) Thermal Pad (GND) 7 8 9 10 11 12 13 14 15 16 17 18 19 GPIO2 I2Ct_SDA I2Ct_SCL I2Ct_IRQ GND GND GPIO11 GND DRAIN I2Cc_SDA I2Cc_SCL I2Cc_IRQ GPIO3 Not to Scale VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS CC2 32 31 30 29 28 27 26 25 Figure 5-1. Top View of the TPS25751D 38-pin QFN Package LDO_3V3 1 24 CC1 ADCIN1 2 23 GPIO5/USB_N/LD2 22 GPIO4/USB_P/LD1 21 GATE_VBUS ADCIN2 3 LDO_1V5 4 GPIO0 5 20 GATE_VSYS GPIO1 6 19 VSYS GPIO2 7 18 GPIO3 I2Ct_SDA 8 17 I2Cc_IRQ 16 I2Cc_SCL 13 GND GPIO11 15 12 GND GND 11 I2Ct_IRQ I2Cc_SDA 10 14 9 I2Ct_SCL Thermal Pad (GND) Not to Scale Figure 5-2. Top View of the TPS25751S 32-pin QFN Package 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 Table 5-1. TPS25751D Pin Functions PIN TYPE(1) RESET 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 28 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 29 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). NAME NO. ADCIN1 ADCIN2 DESCRIPTION GND 11, 12, 14, 31 — — Ground. Connect to ground plane. GPIO0 5 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO1 6 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO2 7 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO3 19 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO4/USB_P/LD1 26 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D+ for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO5/USB_N/LD2 27 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D- for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO6 37 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO7 36 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Ct_SCL 9 I Hi-Z I2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_SDA 8 I/O Hi-Z I2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_IRQ 10 O Hi-Z I2C target interrupt. Active low. Connect to external voltage through a pull-up resistor. Pin can be re-configured to GPIO10. Tie to ground if unused. I2Cc_SCL 17 O Hi-Z I2C controller serial clock. Open-drain output. Tie to pullup voltage through a resistor. Can be grounded if unused. GPIO11 13 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Cc_SDA 16 I/O Hi-Z I2C controller serial data. Open-drain input/output. Tie to pullup voltage through a resistor. Can be grounded if unused. I2Cc_IRQ 18 I Hi-Z I2C controller interrupt. Active low. Connect to external voltage through a pull-up resistor. Do NOT tie to GND when unused. Pin can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. Pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. DRAIN 15, 30 N/A — Connects to drain of internal FET. PP5V 34, 35 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN. (1) PPHV 20, 21, 22 I/O High-voltage sinking node in the system. VBUS_IN 23, 24, 25 I/O 5-V to 20-V input. VBUS 32, 33 O 5-V output from PP5V input to LDO. Bypass with capacitance CVBUS to GND. VIN_3V3 38 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 5 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 Table 5-2. TPS25751S Pin Functions PIN TYPE(1) RESET 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 24 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 25 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). NAME NO. ADCIN1 ADCIN2 DESCRIPTION GATE_VSYS 20 O Hi-Z Connect to the N-ch MOSFET that has source tied to VSYS. GATE_VBUS 21 O Hi-Z Connect to the N-ch MOSFET that has source tied to VBUS. GND 11, 12, 14 — — Ground. Connect to ground plane. GPIO0 5 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO1 6 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO2 7 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO3 18 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO4/USB_P/LD1 22 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D+ for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO5/USB_N/LD2 23 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. Pin can be connected to D- for BC1.2 support. Pin can be connected for liquid detection on the Type-C connector. Tie to ground when pin is unused. GPIO6 31 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. GPIO7 30 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Ct_SCL 9 I Hi-Z I2C target serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_SDA 8 I/O Hi-Z I2C target serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Ct_IRQ 10 O Hi-Z I2C target interrupt. Active low. Connect to external voltage through a pull-up resistor. Pin can be re-configured to GPIO10. Tie to ground when unused. I2Cc_SCL 16 O Hi-Z I2C controller serial clock. Open-drain output. Tie to pullup voltage through a resistor when used or unused. GPIO11 13 GPIO Hi-Z General purpose digital I/O. Tie to ground when pin is unused. I2Cc_SDA 15 I/O Hi-Z I2C controller serial data. Open-drain input/output. Tie to pullup voltage through a resistor when used or unused. I2Cc_IRQ 17 I Hi-Z I2C controller interrupt. Active low. Connect to external voltage through a pull-up resistor. Do NOT tie to GND when unused. Pin can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. Pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. PP5V 28, 29 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN. VSYS 19 I — High-voltage sinking node in the system. Pin is used to implement reverse-current-protection (RCP) for the external sinking paths controlled by GATE_VSYS. VBUS 26, 27 I/O VIN_3V3 32 I 5-V to 20-V input. Bypass with capacitance CVBUS to GND. — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. (1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6 Specifications 6.1 Absolute Maximum Ratings 6.1.1 TPS25751D and TPS25751S - Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Input voltage range MIN MAX PP5V –0.3 6 VIN_3V3 –0.3 4 ADCIN1, ADCIN2 –0.3 4 (4) –0.3 28 –0.5 26 GPIOx –0.3 6.0 I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ,I2Ct_SCL, I2Ct_SDA –0.3 4 VBUS_IN, VBUS (2) CC1, CC2 Output voltage range (1) (2) (4) LDO_1V5 (3) –0.3 2 LDO_3V3 (3) –0.3 4 Source or sink current VBUS Source current Source current UNIT V V V internally limited Positive source current on CC1, CC2 1 Positive sink current on CC1, CC2 while VCONN switch is enabled 1 Positive sink current for I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ,I2Ct_SCL, I2Ct_SDA internally limited Positive source current for LDO_3V3, LDO_1V5 internally limited GPIOx A 0.005 A TJ Operating junction temperature –40 175 °C TSTG Storage temperature –55 150 °C (1) (2) (3) (4) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Do not apply voltage to these pins. A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200. 6.1.2 TPS25751D - Absolute Maximum Ratings Input voltage range (1) PPHV MIN MAX UNIT –0.3 28 V VPPHV_VBUS_IN Source-to-source voltage 28 Sink current Continuous current to/from VBUS_IN to PPHV 7 Pulsed current to/from (2) VBUS_IN to PPHV 10 TJ_PPHV Operating junction temperature (1) (2) PP_HV switch –40 175 V A °C All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Pulse duration ≤ 100 µs and duty-cycle ≤ 1%. 6.1.3 TPS25751S - Absolute Maximum Ratings Output voltage range 1 GATE_VBUS, 2 GATE_VSYS MIN MAX –0.3 40 UNIT V Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 7 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.1.3 TPS25751S - Absolute Maximum Ratings (continued) VGATE_VBUS - VVBUS, VGATE_SYS - VVSYS VGS (1) (2) MIN MAX –0.5 12 UNIT V All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Do not apply voltage to these pins. 6.2 ESD Ratings PARAMETER V(ESD) (1) (2) TEST CONDITIONS Electrostatic discharge VALUE Human-body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) ±1000 Charged-device model (CDM), per ANSI/ ESDA/JEDEC JS-002, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3.1 TPS25751D - Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VI VIO Input voltage range I/O voltage range (1) (1) MIN MAX VIN_3V3 3.0 3.6 PP5V 4.9 5.5 ADCIN1, ADCIN2,VBUS_IN, VBUS 4 22 PPHV 0 22 I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 GPIOx 0 5.5 CC1, CC2 0 5.5 VBUS IO Output current (from PP5V) IO Output current (from LDO_3V3) TJ Operating junction temperature (1) (1) CC1, CC2 GPIOx –40 UNIT V V 3 A 315 mA 1 mA 125 °C All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. 6.3.2 TPS25751S - Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VI VIO 8 Input voltage range I/O voltage range (1) (1) (1) MIN MAX VIN_3V3 3.0 3.6 PP5V 4.9 5.5 VBUS 4 22 VSYS 0 22 I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 GPIOx 0 5.5 CC1, CC2 0 5.5 VBUS IO Output current (from PP5V) IO Output current (from LDO_3V3) IO Output current (from VBUS LDO) UNIT V V 3 A 315 mA GPIOx 1 mA sum of current from LDO_3V3 and GPIOx 5 mA CC1, CC2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 over operating free-air temperature range (unless otherwise noted) TJ (1) (1) Operating junction temperature MIN MAX UNIT –40 125 °C All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. 6.4 Recommended Capacitance over operating free-air temperature range (unless otherwise noted) PARAMETER(1) VOLTAGE RATING MIN NOM CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 10 CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 10 CLDO_1V5 Capacitance on LDO_1V5 4V 4.5 CVBUS Capacitance on VBUS 25 V 1 (2) (4) UNIT µF 25 µF 12 µF 10 µF CPP5V Capacitance on PP5V 10 V CVSYS (TPS25751S) Capacitance on VSYS Sink from VBUS(5) 25 V 47 100 µF CPPHV (TPS25751D) Capacitance on PPHV Sink from VBUS(5) 25 V 47 100 µF CCCy Capacitance on CCy pins(3) 6.3 V 400 480 pF (1) (2) (3) (4) (5) 120 4.7 MAX 200 µF Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by 50% at the required operating voltage, then the required external capacitor value is 10 µF. USB PD requirement (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V. Capacitance includes all external capacitance to the Type-C receptacle. The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a capacitance on the higher side of the range is recommended. USB PD specification for cSnkBulkPd (100µF) is the maximum bulk capacitance allowed on a VBUS sink after a PD contract is in place. The capacitance is sufficient for all power conversion devices deriving power from the PD Controller sink path. For systems requiring greater than 100uF, VBUS surge current limiting is implemented as described in the USB3.2 specification. Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 9 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.5 Thermal Information 6.5.1 TPS25751D - Thermal Information TPS25751D THERMAL METRIC(1) QFN UNIT 38 PINS Junction-to-ambient thermal resistance (sinking through PP_HV) 57.4 °C/W Junction-to-ambient thermal resistance (sourcing through PP_5V) 46.5 °C/W Junction-to-case (top) thermal resistance (sinking through PP_HV) 30.5 °C/W Junction-to-case (top) thermal resistance (sourcing through PP_5V) 20.3 °C/W Junction-to-board thermal resistance (sinking through PP_HV) 21.1 °C/W Junction-to-board thermal resistance (sourcing through PP_5V) 11.1 °C/W Junction-to-top characterization parameter (sinking through PP_HV) 18.2 °C/W Junction-to-top characterization parameter (sourcing through PP_5V) 1.0 °C/W Junction-to-board characterization parameter (sinking through PP_HV) 21.1 °C/W Junction-to-board characterization parameter (sourcing through PP_5V) 11.1 °C/W RθJC (bot_GND) Junction-to-case (bottom GND pad) thermal resistance 1.8 °C/W RθJC (bot_DRAIN) Junction-to-case (bottom DRAIN pad) thermal resistance 4.6 °C/W RθJA RθJC (top) RθJB ψJT ψJB (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5.2 TPS25751S - Thermal Information TPS25751S THERMAL METRIC(1) QFN UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 30.5 °C/W RθJC (top) Junction-to-case (top) thermal resistance 24.5 °C/W RθJC Junction-to-board (bottom) thermal resistance 2 °C/W RθJB Junction-to-board thermal resistance 9.8 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.6 Power Supply Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN_3V3, VBUS VVBUS_UVLO VBUS UVLO threshold rising 3.6 falling 3.5 3.9 3.8 hysteresis rising, VVBUS = 0 Voltage required on VIN_3V3 for falling, VVBUS = 0 power on hysteresis VVIN3V3_UVLO V 0.1 2.56 2.66 2.76 2.44 2.54 2.64 V 3.6 V 1.4 Ω 1.65 V 0.12 LDO_3V3, LDO_1V5 VLDO_3V3 Voltage on LDO_3V3 VVIN_3V3 = 0 V, 10 µA ≤ ILOAD ≤ 18 mA, VBUS ≥ 3.9 V RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50 mA VLDO_1V5 Voltage on LDO_1V5 up to maximum internal loading condition 3.0 3.4 1.49 1.5 6.7 Power Consumption Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVIN_3V3,ActSrc Current into VIN_3V3 Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 3 IVIN_3V3,ActSnk Current into VIN_3V3 Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 3 mA IVIN_3V3,IdlSrc Current into VIN_3V3 Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 1.0 mA IVIN_3V3,IdlSnk Current into VIN_3V3 Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 1.0 mA PMstbySnk Power drawn into PP5V CCm floating, VCCn = 0.4 V, VPP5V = 5 V, VVIN_3V3 = 3.3 V, and VIN_3V3 in Modern VVBUS = 5.0 V, GATE_VBUS, GATE_VSYS disabled, and TJ Standby Sink Mode = 25°C 4.1 mW PMstbySrc Power drawn into PP5V CCm floating, CCn tied to GND through 5.1 kΩ, VPP5V = 5 and VIN_3V3 in Modern V, VVIN_3V3 = 3.3 V, IVBUS = 0, TJ = 25°C Standby Source Mode 4.5 mW IPP5V,Sleep Current into PP5V Sleep mode: VPA_VBUS = 0 V, VVIN_3V3 = 3.3 V 2 µA IVIN_3V3,Sleep Current into VIN_3V3 Sleep mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 56 µA 6 mA 6.8 PP_5V Power Switch Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V TYP MAX UNIT RPP_5V PARAMETER Resistance from PP5V to VBUS ILOAD = 3 A, TJ = 25°C TEST CONDITIONS MIN 36 38 mΩ RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A,TJ = 125°C 36 53 mΩ IPP5V_REV VBUS to PP5V leakage current VPP5V = 0 V, VVBUS = 5.5 V, PP_5V disabled, TJ ≤ 85°C, measure IPP5V 5 µA IPP5V_FWD PP5V to VBUS leakage current VPP5V = 5.5 V, VVBUS = 0 V, PP_5V disabled, TJ ≤ 85°C, measure IVBUS 15 µA ILIM5V Current limit setting Configure to setting 0 1.15 1.36 A ILIM5V Current limit setting Configure to setting 1 1.61 1.90 A ILIM5V Current limit setting 2.3 2.70 A ILIM5V Current limit setting Configure to setting 3 3.04 3.58 A ILIM5V Current limit setting Configure to setting 4 3.22 3.78 A Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 11 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.8 PP_5V Power Switch Characteristics (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.05 3.5 3.75 A/V 20 mV IVBUS PP5V to VBUS current sense accuracy VPP_5V_RCP RCP clears and PP_5V starts turning on when VVBUS – VPP5V < VPP_5V_RCP. Measure VVBUS – VPP5V tiOS_PP_5V Response time to VBUS short circuit VBUS to GND through 10 mΩ, CVBUS = 0 1.15 µs tPP_5V_ovp Response time to VVBUS > VOVP4RCP Enable PP_5V, IRpDef being drawn from PP5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4V to 20 V at 100 V/ms, CPP5V = 2.5 µF, measure time from OVP detection until reverse current < 100 mA 4.5 µs tPP_5V_uvlo Response time to VPP5V < R = 100 Ω, no external VPP5V_UVLO, PP_VBUS is deemed off L capacitance on VBUS when VVBUS < 0.8 V 4 µs 0.7 µs 5.1 ms 3.64 A ≥ IVBUS ≥ 1 A 10 VPP5V = 5.5 V, IRpDef being drawn from PP5V, enable PP_5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4 V to 21.5 V at 10 V/µs, measure VPP5V. CPP5V = 104 µF, CVBUS=10 µF, measure time from RCP detection until reverse current < 100 mA tPP_5V_rcp Response time to VPP5V < VVBUS + VPP_5V_RCP tILIM Current clamping deglitch time tON From enable signal to VBUS at 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 2.3 3.3 4.3 ms tOFF From disable signal to VBUS at 10% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.30 0.45 0.6 ms tRISE VBUS from 10% to 90% of final value RL = 100 Ω, VPP5V = 5 V, CL = 0 1.2 1.7 2.2 ms tFALL VBUS from 90% to 10% of initial value RL = 100 Ω, VPP5V = 5 V, CL = 0 0.06 0.1 0.14 ms TEST CONDITIONS MIN TYP MAX UNIT Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV 6.9 PPHV Power Switch Characteristics - TPS25751D Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VRCP 12 Comparator mode RCP threshold, VPPHV - VVBUS Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.9 PPHV Power Switch Characteristics - TPS25751D (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX Soft start slew rate for GATE_VSYS, setting 0 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 Soft start slew rate for GATE_VSYS, setting 1 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.95 Soft start slew rate for GATE_VSYS, setting 2 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 2.0 Soft start slew rate for GATE_VSYS, setting 3 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 TEST CONDITIONS MIN TYP MAX UNIT Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV Setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV Soft start slew rate for GATE_VSYS, setting 0 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 Soft start slew rate for GATE_VSYS, setting 1 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.91 Soft start slew rate for GATE_VSYS, setting 2 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 1.80 Soft start slew rate for GATE_VSYS, setting 3 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 SS UNIT V/ms 6.10 PP_EXT Power Switch Characteristics - TPS25751S Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VRCP Comparator mode RCP threshold, VVSYS - VVBUS SS V/ms Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 13 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.11 Power Path Supervisory Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VOVP4RCP VBUS overvoltage protection for RCP programmable range VOVP4RCPH Hysteresis rOVP Ratio of OVP4RCP input used for OVP4VSYS comparator. rOVP × VOVP4VSYS = VOVP4RCP VOVP4VSYS VOVP4VSYS VPP5V_UVLO TEST CONDITIONS MIN OVP detected when VVBUS > VOVP4RCP 5.0 TYP 1.75 Voltage required on PP5V V 2.25 % 1 V/V 0.95 V/V setting 2 0.90 V/V setting 3 0.875 V/V 5 27.5 V VBUS falling, % of VOVP4VSYS, rOVP setting 0 1.75 2 2.25 VBUS falling, % of VOVP4VSYS, rOVP setting 1 1.8 2.1 2.4 VBUS falling, % of VOVP4VSYS, rOVP setting 2 1.9 2.2 2.5 VBUS falling, % of VOVP4VSYS, rOVP setting 3 2 2.3 2.6 rising 3.9 4.1 4.3 falling 3.8 4.0 4.2 V 15 mA MAX UNIT % 0.1 VVBUS = 22 V, measure IVBUS VBUS discharge current 24 setting 1 hysteresis IDSCH UNIT setting 0 VBUS overvoltage protection range for OVP detected when rOVP × VSYS protection VVBUS > VOVP4RCP Hysteresis 2 MAX 4 6.12 CC Cable Detection Parameters Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP Type-C Source (Rp pullup) VOC_3.3 Unattached CCy open circuit voltage while Rp enabled, no load VLDO_3V3 > 2.302 V, RCC = 47 kΩ 1.85 V VOC_5 Attached CCy open circuit voltage while Rp enabled, no load VPP5V > 3.802 V, RCC = 47 kΩ 2.95 V Unattached reverse current on CCy IRev VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 3.8 V, measure current into CCy 10 VCCy = 5.5 V, VCCx = 0 V, VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V, VPP5V = 0, TJ ≤ 85°C, measure current into CCy 10 µA IRpDef Current source - USB Default 0 < VCCy < 1.0 V, measure ICCy 64 80 96 µA IRp1.5 Current source - 1.5 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 1.5 V, measure ICCy 166 180 194 µA IRp3.0 Current source - 3.0 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 2.45 V, measure ICCy 304 330 356 µA rising 0.2 0.24 V Type-C Sink (Rd pulldown) VSNK1 14 Open/Default detection threshold when Rd applied to CCy Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.12 CC Cable Detection Parameters (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VSNK1 TEST CONDITIONS Open/Default detection threshold when Rd applied to CCy falling MIN TYP 0.16 Hysteresis VSNK2 VSNK2 MAX UNIT 0.20 V 0.04 Default/1.5-A detection threshold falling 0.62 Default/1.5-A detection threshold rising 0.63 0.66 Hysteresis V 0.68 V 0.69 V 0.01 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy falling 1.17 1.25 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy rising 1.22 1.3 V Hysteresis 0.05 V RSNK Rd pulldown resistance 0.25 V ≤ VCCy ≤ 2.1 V, measure resistance on CCy RVCONN_DIS VCONN discharge resistance 0V ≤ VCCy ≤ 5.5 V, measure resistance on CCy 4.0 6.12 VVIN_3V3 = 0 V, 64 µA < ICCy < 96 µA 0.25 1.32 VVIN_3V3 = 0 V, 166 µA < ICCy < 194 µA 0.65 1.32 VVIN_3V3 = 0 V, 304 µA < ICCy < 356 µA 1.20 2.18 VVBUS = 0, VVIN_3V3 = 3.3 V, VCCy = 5 V, measure resistance on CCy 500 kΩ VVBUS = 5 V, VVIN_3V3 = 0, VCCy = 5 V, measure resistance on CCy 500 kΩ VCLAMP ROpen Dead battery Rd clamp Resistance from CCy to GND when configured as open 4.6 5.6 kΩ kΩ V 6.13 CC VCONN Parameters Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 Ω RPP_CABLE Rdson of the VCONN path VPP5V = 5 V, IL = 250 mA, measure resistance from PP5V to CCy ILIMVC Short circuit current limit Setting 0, VPP5V = 5 V, RL=10 mΩ, measure ICCy 350 410 470 mA ILIMVC Short circuit current limit Setting 1, VPP5V = 5 V, RL=10 mΩ, measure ICCy 540 600 660 mA ICC2PP5V Reverse leakage current through VCONN FET VCONN disabled, TJ ≤ 85°C, VCCy = 5.5 V, VPP5V = 0 V, VVBUS = 5 V, LDO forced to draw from VBUS, measure ICCy 10 µA VVC_OVP Overvoltage protection threshold for PP_CABLE VPP5V rising 5.6 5.9 6.2 V VPP5V ≥ 4.9 V, VCCy = VPP5V, VCCx rising 60 200 340 mV VVC_RCP Reverse current protection threshold for PP_CABLE, sourcing VCONN through CCx VPP5V ≥ 4.9 V, VCCy ≤ 4 V, VCCx rising 210 340 470 mV tVCILIM Current clamp deglitch time 1.3 ms tPP_CABLE_FSD Time to disable PP_CABLE after VPP5V > VVC_OVP or VCCx - CL = 0 VPP5V > VVC_RCP 0.5 µs Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 15 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.13 CC VCONN Parameters (continued) Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPP_CABLE_off From disable signal to CCy at 10% of final value IL = 250 mA, VPP5V = 5 V, CL = 0 100 200 300 µs tiOS_PP_CABLE Response time to short circuit VPP5V = 5 V, for short circuit RL = 10 mΩ 2 µs 6.14 CC PHY Parameters Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.125 1.2 V 75 mV 75 Ω Transmitter VTXHI Transmit high voltage on CCy Standard External load 1.05 VTXLO Transmit low voltage on CCy Standard External load –75 ZDRIVER Transmit output impedance while driving the CC line using CCy measured at 750 kHz 33 tRise Rise time. 10 % to 90 % amplitude points on CCy, minimum is under CCCy = 520 pF an unloaded condition. Maximum set by TX mask 300 ns tFall Fall time. 90 % to 10 % amplitude points on CCy, minimum is under an unloaded condition. Maximum set by TX mask CCCy = 520 pF 300 ns VPHY_OVP OVP detection threshold for USB PD PHY 0 ≤ VVIN_3V3 ≤ 3.6 V, 0 ≤ VPP5V ≤ 5.5 V, VVBUS ≥ 4 V. Initially VCC1 ≤ 5.5 V and VCC2 ≤ 5.5 V, then VCCx rises 5.5 54 8.5 V Receiver ZBMCRX Does not include pullup or Receiver input impedance on CCy pulldown resistance from cable detect. Transmitter is Hi-Z CCC Receiver capacitance on CCy VRX_SNK_R Rising threshold on CCy for receiver comparator Sink mode (rising) 499 VRX_SRC_R Rising threshold on CCy for receiver comparator Source mode (rising) VRX_SNK_F Falling threshold on CCy for receiver comparator VRX_SRC_F Falling threshold on CCy for receiver comparator (1) 1 MΩ Capacitance looking into the CC pin when in receiver mode 120 pF 525 551 mV 784 825 866 mV Sink mode (falling) 230 250 270 mV Source mode (falling) 523 550 578 mV (1) CCC includes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding CCCy externally. 16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TPS25751 TPS25751 www.ti.com SLVSH93A – OCTOBER 2023 – REVISED MARCH 2024 6.15 Thermal Shutdown Characteristics over operating