Datasheet · 2020

TI TPS25750 USB Type-C and USB PD Controller — Datasheet (SLVSFR7A)

The NRND predecessor; EEPROM configuration facts.

Author: Texas Instruments
Year: 2020
Type: Datasheet
Credit: Texas Instruments (ti.com)

usb pd
controller
nrnd

TPS25750 TPS25750 SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 www.ti.com TPS25750 USB Type-C® and USB PD Controller with Integrated Power Switches Optimized for Power Applications 1 Features 2 Applications • • • • • • Integrated fully managed power paths – Integrated 5-V, 3-A, 36-mΩ sourcing switch (TPS25750S/D) – Integrated 28-V, 7-A, 16-mΩ bi-directional load switch (TPS25750D only) Standalone USB Type-C PD solution – No firmware development or external microcontroller needed Integrated robust power path protection – Integrated reverse current protection, overvoltage protection, and slew rate control the high-voltage bi-directional power path – Integrated undervoltage and overvoltage protection and current limiting for inrush current protection for the 5V/3A source power path – 26-V tolerant CC pins for robust protection when connected to non-compliant devices Optimized for power applications – Integrated I2C control for TI battery chargers – Web-based GUI and pre-configured firmware – Optimized for power consumer only (sink) (UFP) applications – Optimized for power provider (source) and power consumer (sink) (DRP) applications USB Type-C power delivery (PD) controller – 10 configurable GPIOs – BC1.2 charging support – USB PD 3.0 compliant – USB Type-C specification complaint – Cable attach and orientation detection – Integrated VCONN switch – Physical layer and policy engine – 3.3-V LDO output for dead battery support – Power supply from 3.3 V or VBUS source Power tools, power banks, retail automation and payment Wireless speakers, headphones Other personal electronics and industrial applications • • 3 Description The TPS25750 is a highly integrated stand-alone USB Type-C and Power Delivery (PD) controller optimized for applications supporting USB-C PD Power. The TPS25750 integrates fully managed power paths with robust protection for a complete USB-C PD solution. The TPS25750 also integrates control for external battery charger ICs for added ease of use and reduced time to market. The intuitive web based GUI will ask the user a few simple questions on the applications needs using clear block diagrams and simple multiple-choice questions. As a result, the GUI will create the configuration image for the user’s application, reducing much of the complexity associated with competitive USB PD solutions. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TPS25750D QFN (RJK) 4.0 mm x 6.0 mm TPS25750S QFN (RSM) 4.0 mm x 4.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 5A 5-20 V 3.3 V LDO TPS25750D 5V VBUS 3A 3.3 V Optional Embedded Controller I2C Slave BQ Battery Charger I2C Master Type-C Rp/Rd & state machine, VCONN switches, USB PD policy engine, protocol and physical layer CC1/2 2 CC VCONN USB Type-C Connector GND 10 GPIO An© 2020 IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright Texas Instruments Incorporated Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TPS25750 1 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings........................................ 7 7.2 ESD Ratings............................................................... 8 7.3 Recommeded Operating Conditions...........................8 7.4 Recommended Capacitance.......................................9 7.5 Thermal Information..................................................10 7.6 Power Supply Characteristics................................... 11 7.7 Power Consumption..................................................11 7.8 PP_5V Power Switch Characteristics....................... 11 7.9 PPHV Power Switch Characteristics - TPS25750D..12 7.10 PP_EXT Power Switch Characteristics TPS25750S................................................................. 14 7.11 Power Path Supervisory..........................................16 7.12 CC Cable Detection Parameters.............................16 7.13 CC VCONN Parameters......................................... 17 7.14 CC PHY Parameters...............................................18 7.15 Thermal Shutdown Characteristics......................... 18 7.16 ADC Characteristics................................................19 7.17 Input/Output (I/O) Characteristics........................... 19 7.18 BC1.2 Characteristics............................................. 19 7.19 I2C Requirements and Characteristics................... 20 7.20 Typical Characteristics ........................................... 22 8 Parameter Measurement Information.......................... 24 9 Detailed Description......................................................25 9.1 Overview................................................................... 25 9.2 Functional Block Diagram......................................... 26 9.3 Feature Description...................................................28 9.4 Device Functional Modes..........................................45 10 Application and Implementation................................ 49 10.1 Application Information........................................... 49 10.2 Typical Application.................................................. 49 11 Power Supply Recommendations..............................54 11.1 3.3-V Power............................................................ 54 11.2 1.5-V Power............................................................ 54 11.3 Recommended Supply Load Capacitance..............54 12 Layout...........................................................................55 12.1 TPS25750D - Layout.............................................. 55 12.2 TPS25750S - Layout...............................................60 13 Device and Documentation Support..........................67 13.1 Device Support....................................................... 67 13.2 Documentation Support.......................................... 67 13.3 Support Resources................................................. 67 13.4 Trademarks............................................................. 67 13.5 Electrostatic Discharge Caution..............................67 13.6 Glossary..................................................................67 14 Mechanical, Packaging, and Orderable Information.................................................................... 67 4 Revision History Changes from Revision * (July 2020) to Revision A (November 2020) Page • Changed data sheet status from "Advance Information" to "Production Data"...................................................1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 5 Device Comparison Table 5-V SOURCE LOAD SWITCH INTEGRATED HIGH VOLTAGE BI-DIRECTIONAL LOAD SWITCH (PPHV) HIGH VOLTAGE GATE DRIVER FOR BI-DIRECTIONAL EXTERNAL PATH (PP_EXT) TPS25750D Yes Yes No TPS25750S Yes No Yes DEVICE NUMBER Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 3 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 6 Pin Configuration and Functions VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS GND DRAIN CC2 CC1 GPIO5/ USB_N GPIO4/ USB_P 38 37 36 35 34 33 32 31 30 29 28 27 26 LDO_3V3 1 25 VBUS_IN ADCIN1 2 24 VBUS_IN ADCIN2 3 23 VBUS_IN Thermal Pad (GND) Thermal Pad (DRAIN) LDO_1V5 4 22 PPHV GPIO0 5 21 PPHV GPIO1 6 20 PPHV 7 8 9 10 11 12 13 14 15 16 17 18 19 GPIO2 I2Cs_SDA I2Cs_SCL I2Cs_IRQ GND GND GPIO11 GND DRAIN I2Cm_SDA I2Cm_SCL I2Cm_IRQ GPIO3 Not to Scale VIN_3V3 GPIO6 GPIO7 PP5V PP5V VBUS VBUS CC2 32 31 30 29 28 27 26 25 Figure 6-1. Top View of the TPS25750D 38-pin QFN RJK Package LDO_3V3 1 24 CC1 ADCIN1 2 23 GPIO5/USB_N 22 GPIO4/USB_P 21 GATE_VBUS ADCIN2 3 LDO_1V5 4 GPIO0 5 20 GATE_VSYS GPIO1 6 19 VSYS GPIO2 7 18 GPIO3 I2Cs_SDA 8 17 I2Cm_IRQ 9 10 11 12 13 14 15 16 I2Cs_SCL I2Cs_IRQ GND GND GPIO11 GND I2Cm_SDA I2Cm_SCL Thermal Pad (GND) Not to Scale Figure 6-2. Top View of the TPS25750S 32-pin QFN RSM Package 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Table 6-1. TPS25750D Pin Functions PIN TYPE(1) RESET DESCRIPTION NAME NO. ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 28 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 29 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). GND 11, 12, 14, 31 — — Ground. Connect to ground plane. GPIO0 5 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO1 6 GPIO Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO2 7 O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO3 19 O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO4(USB_P) 26 I/O Hi-Z General purpose digital I/O. Tie to ground when unused.This may be connected to D+ for BC1.2 support. GPIO5(USB_N) 27 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. This may be connected to D- for BC1.2 support. GPIO6 37 O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO7 36 O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Cs_SCL 9 I Hi-Z I2C slave serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Cs_SDA 8 I/O Hi-Z I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Cs_IRQ 10 O Hi-Z I2C slave interrupt. Active low. Connect to external voltage through a pull-up resistor. This can be re-configured to GPIO10. Tie to ground if unused. I2Cm_SCL 17 O Hi-Z I2C master serial clock. Open-drain output. Tie to pullup voltage through a resistor. Can be grounded if unused. GPIO11 13 O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Cm_SDA 16 I/O Hi-Z I2C master serial data. Open-drain input/output. Tie to pullup voltage through a resistor. Can be grounded if unused. I2Cm_IRQ 18 I Hi-Z I2C master interrupt. Active low. Connect to external voltage through a pull-up resistor.Tie to ground when unused. This can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. DRAIN 15, 30 N/A — Connects to drain of internal FET. — 5-V System Supply to VBUS, supply for CCy pins as VCONN. PP5V 34, 35 I PPHV 20, 21, 22 I/O High-voltage sinking node in the system. VBUS_IN 23, 24, 25 I/O 5-V to 20-V input. VBUS 32, 33 O VIN_3V3 38 I (1) 5-V output from PP5V input to LDO. Bypass with capacitance CVBUS to GND. — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 5 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Table 6-2. TPS25750S Pin Functions PIN TYPE(1) RESET DESCRIPTION NAME NO. ADCIN1 2 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. ADCIN2 3 I Hi-Z Configuration Input. Connect to a resistor divider to LDO_3V3. CC1 24 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). CC2 25 I/O Hi-Z I/O for USB Type-C. Filter noise with recommended capacitor to GND (CCCy). GATE_VSYS 20 O Hi-Z Connect to the N-ch MOSFET that has source tied to VSYS. GATE_VBUS 21 O Hi-Z Connect to the N-ch MOSFET that has source tied to VBUS. GND 11, 12, 14 — — Ground. Connect to ground plane. GPIO0 5 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO1 6 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO2 7 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO3 18 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO4 (USB_P) 22 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. This may be connected to D+ for BC1.2 support. GPIO5 (USB_N) 23 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. This may be connected to D- for BC1.2 support. GPIO6 31 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. GPIO7 30 I/O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Cs_SCL 9 I Hi-Z I2C slave serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. I2Cs_SDA 8 I/O Hi-Z I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. I2Cs_IRQ 10 O Hi-Z I2C slave interrupt. Active low. Connect to external voltage through a pull-up resistor. This can be re-configured to GPIO10. Tie to ground when unused. I2Cm_SCL 16 O Hi-Z I2C master serial clock. Open-drain output. Tie to pullup voltage through a resistor when used or unused. GPIO11 13 O Hi-Z General purpose digital I/O. Tie to ground when unused. I2Cm_SDA 15 I/O Hi-Z I2C master serial data. Open-drain input/output. Tie to pullup voltage through a resistor when used or unused. I2Cm_IRQ 17 I Hi-Z I2C master interrupt. Active low. Connect to external voltage through a pull-up resistor. Tie to ground when unused. This can be re-configured to GPIO12. LDO_1V5 4 O — Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits. LDO_3V3 1 O — Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. PP5V 28, 29 I — 5-V System Supply to VBUS, supply for CCy pins as VCONN. VSYS 19 I — High-voltage sinking node in the system. It is used to implement reversecurrent-protection (RCP) for the external sinking paths controlled by GATE_VSYS. VBUS 26, 27 I/O VIN_3V3 32 I 5-V to 20-V input. Bypass with capacitance CVBUS to GND. — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. (1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7 Specifications 7.1 Absolute Maximum Ratings 7.1.1 TPS25750D and TPS25750S - Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Input voltage range MIN MAX PP5V –0.3 6 VIN_3V3 –0.3 4 ADCIN1, ADCIN2 -0.3 4 (4) –0.3 28 –0.5 26 GPIOx -0.3 6.0 I2Cm_SDA, I2Cm_SCL, I2Cm_IRQ, I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA –0.3 4 VBUS_IN, VBUS (2) CC1, CC2 Output voltage range (1) (2) (4) LDO_1V5 (3) –0.3 2 LDO_3V3 (3) –0.3 4 Source or sink current VBUS Source current Source current UNIT V V V internally limited Positive source current on CC1, CC2 1 Positive sink current on CC1, CC2 while VCONN switch is enabled 1 Positive sink current for I2Cm_SDA, I2Cm_SCL, I2Cm_IRQ, I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA internally limited Positive source current for LDO_3V3, LDO_1V5 internally limited GPIOx A 0.005 A TJ Operating junction temperature –40 175 °C TSTG Storage temperature –55 150 °C (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Do not apply voltage to these pins. A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200. 7.1.2 TPS25750D - Absolute Maximum Ratings Input voltage range (1) PPHV MIN MAX –0.3 28 VPPHV_VBUS_IN Source-to-source voltage 28 Sink current Continuous current to/from VBUS_IN to PPHV 7 Pulsed current to/from (2) VBUS_IN to PPHV 10 TJ_PPHV Operating junction temperature (1) (2) PP_HV switch –40 175 UNIT V V A °C All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Pulse duration ≤ 100 µs and duty-cycle ≤ 1%. 7.1.3 TPS25750S - Absolute Maximum Ratings Output voltage range (1) GATE_VBUS, (2) GATE_VSYS MIN MAX –0.3 40 UNIT V Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 7 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.1.3 TPS25750S - Absolute Maximum Ratings (continued) VGATE_VBUS - VVBUS, V GATE_SYS - VVSYS VGS (1) (2) MIN MAX –0.5 12 UNIT V All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board. Do not apply voltage to these pins. 7.2 ESD Ratings PARAMETER V(ESD) (1) (2) TEST CONDITIONS Electrostatic discharge VALUE Human body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) ±1000 Charged device model (CDM), per JEDEC specificationJESD22-C101, all pins(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommeded Operating Conditions 7.3.1 TPS25750D - Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VI Input voltage range VIO I/O voltage range (1) (1) IO Output current (from PP5V) (1) MIN MAX VIN_3V3 3.0 3.6 PP5V 4.9 5.5 ADCIN1, ADCIN2,VBUS_IN, (2) VBUS 4 22 PPHV 0 22 I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 GPIOx 0 5.5 CC1, CC2 0 5.5 VBUS CC1, CC2 UNIT V V 3 A 315 mA IPP_HV Current from VBUS_IN to PPHV 7 A IO Output current (from LDO_3V3) GPIOx 1 mA IO Output current (from VBUS LDO) Current from LDO_3V3 5 mA IPP_5V ≤ 3 A, IPP_HV = 0, IPP_CABLE ≤ 315 mA –40 85 –40 105 IPP_5V = 0, IPP_HV ≤ 7 A, IPP_CABLE =0 –40 45 IPP_5V = 0, IPP_HV ≤ 6 A, IPP_CABLE =0 –40 65 IPP_5V = 0, IPP_HV ≤ 5 A, IPP_CABLE ≤ 315 mA –40 85 IPP_5V = 0, IPP_HV ≤ 3.5 A, I –40 105 PP_HV switch –40 150 °C –40 125 °C IPP_5V ≤ 1.5 A, IPP_HV = 0, I PP_CABLE ≤ 315 mA TA Ambient operating temperature PP_CABLE ≤ 315 mA TJ_PPHV Operating junction temperature TJ Operating junction temperature °C (1) (2) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. All VBUS and VBUS_IN pins be shorted together. 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.3.2 TPS25750S - Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VI Input voltage range VIO I/O voltage range (1) (1) MIN MAX VIN_3V3 3.0 3.6 PP5V 4.9 5.5 VBUS 4 22 VSYS 0 22 I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 0 3.6 GPIOx 0 5.5 CC1, CC2 0 5.5 VBUS IO Output current (from PP5V) IO Output current (from LDO_3V3) IO Output current (from VBUS LDO) TA Ambient operating temperature TJ Operating junction temperature (1) (1) UNIT V V 3 A 315 mA GPIOx 1 mA sum of current from LDO_3V3 and GPIOx 5 mA CC1, CC2 IPP_5V ≤ 1.5 A, IPP_CABLE ≤ 315 mA –40 105 IPP_5V ≤ 3 A, IPP_CABLE ≤ 315 mA –40 85 –40 125 °C °C All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. 7.4 Recommended Capacitance over operating free-air temperature range (unless otherwise noted) PARAMETER(1) VOLTAGE RATING MIN NOM MAX UNIT CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 10 CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 10 CLDO_1V5 Capacitance on LDO_1V5 4V 4.5 CVBUS Capacitance on VBUS 25 V 1 CPP5V Capacitance on PP5V 10 V CVSYS (TPS25750S) Capacitance on VSYS Sink from VBUS 25 V 47 100 µF CPPHV (TPS25750D) Capacitance on PPHV Sink from VBUS 25 V 47 100 µF CCCy Capacitance on CCy pins(3) 6.3 V 400 480 pF (1) (2) (3) (4) (4) 4.7 µF 25 12 µF 10 µF (2) 120 200 µF µF Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by 50% at the required operating voltage, then the required external capacitor value would be 10 µF. This is a requirement from USB PD (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V. This includes all external capacitance to the Type-C receptacle. The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a capacitance on the higher side of this range is recommended. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 9 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.5 Thermal Information 7.5.1 TPS25750D - Thermal Information TPS25750D THERMAL METRIC(1) QFN (RJK) UNIT 38 PINS Junction-to-ambient thermal resistance (sinking through PP_HV) 57.4 °C/W Junction-to-ambient thermal resistance (sourcing through PP_5V) 46.5 °C/W Junction-to-case (top) thermal resistance (sinking through PP_HV) 30.5 °C/W Junction-to-case (top) thermal resistance (sourcing through PP_5V) 20.3 °C/W Junction-to-board thermal resistance (sinking through PP_HV) 21.1 °C/W Junction-to-board thermal resistance (sourcing through PP_5V) 11.1 °C/W Junction-to-top characterization parameter (sinking through PP_HV) 18.2 °C/W Junction-to-top characterization parameter (sourcing through PP_5V) 1.0 °C/W Junction-to-board characterization parameter (sinking through PP_HV) 21.1 °C/W Junction-to-board characterization parameter (sourcing through PP_5V) 11.1 °C/W RθJC (bot_GND) Junction-to-case (bottom GND pad) thermal resistance 1.8 °C/W RθJC (bot_DRAIN) Junction-to-case (bottom DRAIN pad) thermal resistance 4.6 °C/W RθJA RθJC (top) RθJB ψJT ψJB (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5.2 TPS25750S - Thermal Information TPS25750S THERMAL METRIC(1) QFN (RSM) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 30.5 °C/W RθJC (top) Junction-to-case (top) thermal resistance 24.5 °C/W RθJC Junction-to-board (bottom) thermal resistance 2 °C/W RθJB Junction-to-board thermal resistance 9.8 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 9.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.6 Power Supply Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN_3V3, VBUS VVBUS_UVLO VBUS UVLO threshold rising 3.6 falling 3.5 3.9 3.8 hysteresis rising, VVBUS = 0 Voltage required on VIN_3V3 for falling, VVBUS = 0 power on hysteresis VVIN3V3_UVLO V 0.1 2.56 2.66 2.76 2.44 2.54 2.64 V 3.6 V 1.4 Ω 1.65 V 0.12 LDO_3V3, LDO_1V5 VLDO_3V3 Voltage on LDO_3V3 VVIN_3V3 = 0 V, 10 µA ≤ ILOAD ≤ 18 mA, VBUS ≥ 3.9 V RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50 mA VLDO_1V5 Voltage on LDO_1V5 up to maximum internal loading condition 3.0 3.4 1.49 1.5 7.7 Power Consumption Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading PARAMETER TEST CONDITIONS MIN TYP IVIN_3V3,ActSrc Current into VIN_3V3 Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 3 IVIN_3V3,ActSnk Current into VIN_3V3 Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 3 MAX UNIT mA 6 mA IVIN_3V3,IdlSrc Current into VIN_3V3 Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 1.0 mA IVIN_3V3,IdlSnk Current into VIN_3V3 Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 1.0 mA PMstbySnk Power drawn into PP5V CCm floating, VCCn = 0.4 V, VPP5V = 5 V, VVIN_3V3 = 3.3 V, V and VIN_3V3 in Modern VBUS = 5.0 V, GATE_VBUS, GATE_VSYS disabled, and TJ Standby Sink Mode = 25°C 4.1 mW PMstbySrc Power drawn into PP5V CCm floating, CCn tied to GND through 5.1 kΩ, VPP5V = 5 and VIN_3V3 in Modern V, VVIN_3V3 = 3.3 V, IVBUS = 0, TJ = 25°C Standby Source Mode 4.5 mW IPP5V,Sleep Current into PP5V Sleep source mode: VPA_VBUS = 0 V, VPB_VBUS = 0 V, V VIN_3V3 = 3.3 V 2 µA IVIN_3V3,Sleep Current into VIN_3V3 Sleep DRP mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 56 µA 7.8 PP_5V Power Switch Characteristics Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A, TJ = 25°C 36 38 mΩ RPP_5V Resistance from PP5V to VBUS ILOAD = 3 A,TJ = 125°C 36 53 mΩ IPP5V_REV VBUS to PP5V leakage current VPP5V = 0 V, VVBUS = 5.5 V, PP_5V disabled, TJ ≤ 85°C, measure IPP5V 5 µA IPP5V_FWD PP5V to VBUS leakage current VPP5V = 5.5 V, VVBUS = 0 V, PP_5V disabled, TJ ≤ 85°C, measure IVBUS 15 µA ILIM5V Current limit setting Configure to setting 0 1.15 1.36 A ILIM5V Current limit setting Configure to setting 1 1.61 1.90 A ILIM5V Current limit setting 2.3 2.70 A ILIM5V Current limit setting Configure to setting 3 3.04 3.58 A ILIM5V Current limit setting Configure to setting 4 3.22 3.78 A Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 11 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.05 3.5 3.75 A/V 20 mV IVBUS PP5V to VBUS current sense accuracy VPP_5V_RCP RCP clears and PP_5V starts turning on when VVBUS – VPP5V < V PP_5V_RCP. Measure VVBUS – VPP5V tiOS_PP_5V Response time to VBUS short circuit VBUS to GND through 10 mΩ, CVBUS = 0 1.15 µs tPP_5V_ovp Response time to VVBUS > VOVP4RCP Enable PP_5V, IRpDef being drawn from PP5V, configure VOVP4RCP to setting 2, ramp VVBUS from 4V to 20 V at 100 V/ms, C PP5V = 2.5 µF, measure time from OVP detection until reverse current < 100 mA 4.5 µs tPP_5V_uvlo Response time to VPP5V < V PP5V_UVLO, PP_VBUS is deemed off when VVBUS < 0.8 V RL = 100 Ω, no external capacitance on VBUS 4 µs tPP_5V_rcp VPP5V = 5.5 V, IRpDef being drawn from PP5V, enable PP_5V, configure VOVP4RCP to setting 2, ramp VVBUS Response time to VPP5V < VVBUS + V from 4 V to 21.5 V at 10 V/µs, measure VPP5V. C PP_5V_RCP PP5V = 104 µF, CVBUS=10 µF, measure time from RCP detection until reverse current < 100 mA 0.7 µs tILIM Current clamping deglitch time 5.1 ms tON From enable signal to VBUS at 90% of final value RL = 100 Ω, VPP5V = 5 V, C L=0 tOFF From disable signal to VBUS at 10% of final value L=0 tRISE tFALL 3.64 A ≥ IVBUS ≥ 1 A 10 2.3 3.3 4.3 ms 0.30 0.45 0.6 ms VBUS from 10% to 90% of final value RL = 100 Ω, VPP5V = 5 V, C L=0 1.2 1.7 2.2 ms VBUS from 90% to 10% of initial value 0.06 0.1 0.14 ms MIN UNIT RL = 100 Ω, VPP5V = 5 V, C RL = 100 Ω, VPP5V = 5 V, C L=0 7.9 PPHV Power Switch Characteristics - TPS25750D Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER RPPHV VRCP 12 TEST CONDITIONS Resistance from VBUS_IN to PPHV power switch resistance Comparator mode RCP threshold, V PPHV - VVBUS TYP MAX TJ_PPHV = 25°C, IPPHV = 6.5 A 16 19 TJ_PPHV = 125°C, IPPHV = 6.5A 24 29 TJ_PPHV = 150°C, IPPHV = 6.5 A 27 32 mΩ mΩ Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX Soft start slew rate for GATE_VSYS, setting 0 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 Soft start slew rate for GATE_VSYS, setting 1 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.95 Soft start slew rate for GATE_VSYS, setting 2 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 2.0 Soft start slew rate for GATE_VSYS, setting 3 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 Time allowed to disable the internal PPHV switch in normal shutdown mode VVBUS = 20 V, VPPHV = 20 V (initially), CPPHV< 1 nF, I PPHV = 0.1 A, switch is off when VVBUS_IN – VPPHV > 1V 400 1000 µs Time allowed to disable the internal PPHV switch in fast shutdown mode (VOVP4RCP exceeded), this includes the response time of the comparator OVP: VOVP4RCP = setting 57, VVBUS = 20 V initially, then raised to 23 V in 50 ns, VPPHV = V VBUS_IN (initially), CPPHV< 1 nF, IPPHV = 0.1 A, switch is off when VVBUS_IN – V PPHV > 0.1 V 2 4 µs 1 2 µs 0.25 20 μs 1800 2100 μs SS tPPHV_OFF tPPHV_OVP UNIT V/ms RCP: VRCP= setting 0, V tPPHV_RCP tPPHV_FSD Time allowed to disable the internal PPHV switch in fast shutdown mode (VRCP exceeded), this includes the response time of the comparator Time allowed to disable the internal PPHV switch in fast shutdown mode (OVP) VBUS = 5 V, VVSYS = 5 V initially, then raised to 6 V with dV/dt = 0.1 V/µs, C VBUS=10 µF, measure time from VVSYS > VBUS + VRCP to the time of peak voltage on VBUS VPPHV = 20 V (initially), V VBUS=20 V then raised to 23 V in 50 ns, rOVP = 1, C PPHV < 1 nF, IPPHV = 0.1 A, switch is off when VVBUS_IN – VPPHV > 0.5 V VVBUS_IN = 5 V, CPPHV = 0, I tPPHV_ON Time to enable the internal PPHV switch PPHV = 0, measure time from register write to enable PPHV until V VBUS_IN - VPPHV < 0.1 V, soft start setting 3 1500 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 13 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.10 PP_EXT Power Switch Characteristics - TPS25750S Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER IGATE_ON Gate driver sourcing current TEST CONDITIONS MIN 0 ≤ VGATE_VSYS - VVSYS ≤ 6 V, VVSYS ≤ 22 V, VVBUS > 4 V, measure IGATE_VSYS 0 ≤ VGATE_VBUS - VVBUS ≤ 6 V, 4 V ≤ VVBUS ≤ 22 V, measure IGATE_VBUS TYP MAX UNIT 8.5 11.5 µA 8.5 11.5 µA 6 12 V 4 V ≤ VVBUS ≤ 22 V, I GATE_VBUS < 4 µA, measure VGATE_VBUS – VVBUS 6 12 V Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 2 6 10 mV Setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 4 8 12 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 6 10 14 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 8 12 16 mV Normal turnoff: VVSYS = 5 V, VGATE_VSYS = 6 V, measure IGATE_VSYS 13 µA 13 µA 0 ≤ VVSYS ≤ 22 V, I GATE_VSYS < 4 µA, measure VGATE_ON VGATE_VSYS – VVSYS, VVBUS >4V Sourcing voltage (ON) Comparator mode RCP threshold, V VSYS - VVBUS VRCP IGATE_OFF Sinking strength Normal turnoff: VVBUS = V VSYS = 5 V, VGATE_VBUS = 6 V, measure IGATE_VBUS RGATE_FSD RGATE_OFF_UVLO 14 Sinking strength Sinking strength in UVLO (safety) Fast turnoff: VVSYS = 5 V, V GATE_VSYS = 6 V, assert PPHV1_FAST_DISABLE, measure RGATE_VSYS 85 Ω Fast turnoff: VVBUS = VVSYS = 5 V, VGATE_VBUS = 6 V, assert PPHV1_FAST_DISABLE, measure RGATE_VBUS 85 Ω VVIN_3V3 = 0 V, VVBUS = 3.0 V, VGATE_VSYS = 0.1 V, measure resistance from GATE_VSYS to GND 1.5 MΩ Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX Soft start slew rate for GATE_VSYS, setting 0 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.35 0.41 0.47 Soft start slew rate for GATE_VSYS, setting 1 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 0.67 0.81 0.91 Soft start slew rate for GATE_VSYS, setting 2 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 1.33 1.7 1.80 Soft start slew rate for GATE_VSYS, setting 3 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < C GATE_VSYS < 16 nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 tGATE_VBUS_OFF Time allowed to disable the external FET via GATE_VBUS in normal (1) shutdown mode. VVBUS = 20 V, QG of external FET = 40 nC or C GATE_VBUS < 3 nF, gate is off when VGATE_VBUS – VVBUS <1V 450 4000 µs tGATE_VBUS_OVP Time allowed to disable the external FET via GATE_VBUS in fast shutdown mode (VOVP4RCP exceeded), this includes the (1) response time of the comparator OVP: VOVP4RCP = setting 57, VVBUS = 20 V initially, then raised to 23 V in 50 ns, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when V GATE_VBUS – VVBUS < 1 V 3 5 µs tGATE_VBUS_RCP RCP: VRCP = setting 0, V Time allowed to disable the external VBUS = 5 V, VVSYS = 5 V FET via GATE_VBUS in fast initially, then raised to 5.5 V shutdown mode (VRCP exceeded), in 50 ns, QG of external this includes the response time of the FET = 40 nC or CGATE_VBUS (1) comparator < 3 nF, gate is off when V GATE_VBUS – VVBUS < 1 V 1 2 µs tGATE_VSYS_OFF Time allowed to disable the external FET via GATE_VSYS in normal (1) shutdown mode VVSYS= 20 V, QG of external FET = 40 nC or C GATE_VBUS < 3 nF, gate is off when VGATE_VSYS – VVSYS <1V 450 4000 µs tGATE_VSYS_FSD Time allowed to disable the external FET via GATE_VSYS in fast (1) shutdown mode (OVP) VVBUS = 20 V initially, then raised to 23 V in 50 ns, QG of external FET = 40 nC or CGATE_VBUS < 3 nF, gate is off when VGATE_VSYS – V VSYS < 1 V, rOVP = 1 0.25 20 μs tGATE_VBUS_ON Time to enable GATE_VBUS 0.25 2 ms SS UNIT V/ms Measure time from when V (1) (1) GS = 0 V until VGS >3 V, where VGS = VGATE_VBUS – VVBUS These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 15 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 7.11 Power Path Supervisory Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VOVP4RCP VBUS overvoltage protection for RCP programmable range VOVP4RCPH Hysteresis rOVP Ratio of OVP4RCP input used for OVP4VSYS comparator. rOVP × V OVP4VSYS = VOVP4RCP VOVP4VSYS TEST CONDITIONS MIN OVP detected when VVBUS > VOVP4RCP 5.0 1.75 % V/V setting 2 0.90 V/V setting 3 0.875 V/V 5 27.5 V 1.75 2 2.25 VBUS falling, % of V OVP4VSYS, rOVP setting 1 1.8 2.1 2.4 VBUS falling, % of V OVP4VSYS, rOVP setting 2 1.9 2.2 2.5 2 2.3 2.6 rising 3.9 4.1 4.3 falling 3.8 4.0 4.2 V 15 mA MAX UNIT % hysteresis VVBUS = 22 V, measure I VBUS discharge current 2.25 V/V VBUS falling, % of V IDSCH V 1 OVP4VSYS, rOVP setting 3 Voltage required on PP5V 24 0.95 VBUS falling, % of V VPP5V_UVLO UNIT setting 1 VBUS overvoltage protection range for OVP detected when rOVP × VSYS protection VVBUS > VOVP4RCP Hysteresis 2 MAX setting 0 OVP4VSYS, rOVP setting 0 VOVP4VSYS TYP VBUS 0.1 4 7.12 CC Cable Detection Parameters Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER TEST CONDITIONS MIN TYP Type-C Source (Rp pullup) VOC_3.3 Unattached CCy open circuit voltage while Rp enabled, no load VLDO_3V3 > 2.302 V, RCC = 47 kΩ 1.85 V VOC_5 Attached CCy open circuit voltage while Rp enabled, no load VPP5V > 3.802 V, RCC = 47 kΩ 2.95 V VCCy = 5.5 V, VCCx = 0 V, V LDO_3V3_UVLO < VLDO_3V3 < 3.6 V, V 10 PP5V = 3.8 V, measure current into Unattached reverse current on CCy IRev CCy µA VCCy = 5.5 V, VCCx = 0 V, V LDO_3V3_UVLO < VLDO_3V3 < 3.6 V, V PP5V = 0, TJ ≤ 85°C, measure current into CCy 10 IRpDef Current source - USB Default 0 < VCCy < 1.0 V, measure ICCy 64 80 96 µA IRp1.5 Current source - 1.5 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 1.5 V, measure ICCy 166 180 194 µA IRp3.0 Current source - 3.0 A 4.75 V < VPP5V < 5.5 V, 0 < VCCy < 2.45 V, measure ICCy 304 330 356 µA Type-C Sink (Rd pulldown) VSNK1 Open/Default detection threshold when Rd applied to CCy rising 0.2 0.24 V VSNK1 Open/Default detection threshold when Rd applied to CCy falling 0.16 0.20 V Hysteresis 16 0.04 Submit Document Feedback V Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TPS25750 TPS25750 www.ti.com SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020 Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V PARAMETER VSNK2 VSNK2 TEST CONDITIONS MIN Default/1.5-A detection threshold falling 0.62 Default/1.5-A detection threshold rising 0.63 TYP 0.66 Hysteresis MAX UNIT 0.68 V 0.69 V 0.01 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy falling 1.17 1.25 V VSNK3 1.5-A/3.0-A detection threshold when Rd applied to CCy rising 1.22 1.3 V Hysteresis 0.05 V RSNK Rd pulldown resistance 0.25 V ≤ VCCy ≤ 2.1 V, measure resistance on CCy, after trimming using trim_cd_rd,