TI TPS2550 / TPS2551 Adjustable Current-Limited Power-Distribution Switches — Datasheet (SLVS736C)
TPS2550, TPS2551
SLVS736C – FEBRUARY 2008 – REVISED OCTOBER 2023
TPS255x Adjustable Current-Limited Power-Distribution Switches
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
The TPS2550/51 power-distribution switch is intended
for applications where heavy capacitive loads
and short-circuits are likely to be encountered,
incorporating a 100-mΩ, N-channel MOSFET in
a single package. The current-limit threshold is
user adjustable between 100 mA and 1.1 A via an
external resistor. The power-switch rise and fall times
are controlled to minimize current surges during
switching.
Adjustable current-limit, 100 mA–1100 mA
Fast overcurrent response - 2 μS typical
94-mΩ high-side MOSFET (DBV package)
Reverse input-output voltage protection
Operating range: 2.5 V to 6.5 V
Deglitched fault report
1-μA maximum standby supply current
Junction temperature range: –40°C to 125°C
Built-in soft-start
15 kV ESD protection (with external capacitance)
UL listed – file No. E169910
Current-limit resistor calculator – SLVC163
2 Applications
•
•
•
•
•
USB Ports/Hubs
Cell phones
Laptops
Heavy Capacitive Loads
Reverse-Voltage Protection
The device limits the output current to a desired
level by switching into a constant-current mode when
the output load exceeds the current-limit threshold
or a short is present. An internal reverse-voltage
detection comparator disables the power-switch in the
event that the output voltage is driven higher than
the input to protect devices on the input side of the
switch. The FAULT logic output asserts low during
both overcurrent and reverse-voltage conditions.
Package Information
PACKAGE(1)
PART NUMBER
TPS255x
(1)
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 1.60 mm
WSON (6)
2.00 mm × 2.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS2550/51
5 V USB
INPUT
USB Data
0.1 mF
USB
Port
OUT
IN
RFAULT
100 kW
120 mF *
FAULT Signal
FAULT
ILIM
Control Signal
EN
GND
RILIM
15 kW
PowerPAD
* USB Requirement that downstream-facing ports
are bypassed with at least 120 mF per hub
Figure 3-1. Typical Application as USB Power
Switch
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SLVS736C – FEBRUARY 2008 – REVISED OCTOBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 8
8 Parameter Measurement Information.......................... 11
9 Detailed Description......................................................12
9.1 Overview................................................................... 12
9.2 Functional Block Diagram......................................... 12
9.3 Feature Description...................................................12
9.4 Programming............................................................ 13
10 Application and Implementation................................ 15
10.1 Application Information........................................... 15
10.2 Typical Applications................................................ 15
10.3 Power Supply Recommendations ..........................19
10.4 Layout..................................................................... 20
11 Device and Documentation Support..........................22
11.1 Receiving Notification of Documentation Updates.. 22
11.2 Support Resources................................................. 22
11.3 Trademarks............................................................. 22
11.4 Electrostatic Discharge Caution.............................. 22
11.5 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2008) to Revision C (October 2023)
Page
• Added GPN to beginning of title..................................................................................................................... 0
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Changed the high-side MOSFET resistance to 94-mΩ...................................................................................... 1
• Moved the Device Comparison table..................................................................................................................1
• Added a Package Information table, and removed the General Switch Catalog table.......................................1
• Changed this section title to "Device Comparison Table" and reorganized so that it follows the Revision
History section.................................................................................................................................................... 3
• Changed this section title to ''Pin Configuration and Functions'', and added a pinout drawing before the Pin
Functions table................................................................................................................................................... 4
• Updated the ''ESD content'' and the mark message...........................................................................................5
• Added ''ESD Ratings'' section.............................................................................................................................5
• Moved topic to follow the ESD Ratings section.................................................................................................. 6
• Changed this section title to ''Thermal Information''............................................................................................6
• Moved topic to follow the "Thermal Metrics" section.......................................................................................... 6
• Added ''Functional Block Diagram'' section...................................................................................................... 12
• Added ''Device Functional Modes'' section.......................................................................................................13
• Added the ''Design Requirements'' section.......................................................................................................15
• Added ''Power Supply Recommendations'' section.......................................................................................... 19
• Added ''Layout'' section.................................................................................................................................... 20
2
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5 Device Comparison Table
DEVICE
TPS2550
TPS2551
(1)
(2)
AMBIENT
TEMPERATURE(1)
–40°C to 85°C
ENABLE
SON (2)
(DRV)
SOT23(2)
(DBV)
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
Active low
TPS2550DRV
TPS2550DBV
1.1 A
Active high
TPS2551DRV
TPS2551DBV
1.1 A
Maximum ambient temperature is a function of device junction temperature and system level considerations, such as power dissipation
and board layout. See dissipation rating table and recommended operating conditions for specific information related to these devices.
Add an R suffix to the device type for tape and reel.
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6 Pin Configuration and Functions
OUT
ILIM
FAULT
1
2
3
PAD
TPS2550/TPS2551
DRV PACKAGE
(TOP VIEW)
6
IN
5
4
GND
EN
TPS2550/TPS2551
DBV PACKAGE
(TOP VIEW)
IN
GND
EN
1
2
3
6
OUT
ILIM
FAULT
5
4
EN = Active Low for the TPS2550
EN = Active High for the TPS2551
Table 6-1. Pin Functions
PIN
NAME
4
I/O
DESCRIPTION
TPS2550DBV
TPS2551DBV
TPS2550DRV
TPS2551DRV
EN
3
–
4
–
I
Enable input, logic low turns on power switch
EN
–
3
–
4
I
Enable input, logic high turns on power switch
GND
2
2
5
5
IN
1
1
6
6
I
Input voltage; connect a 0.1 μF or greater
ceramic capacitor from IN to GND as close to the
IC as possible.
FAULT
4
4
3
3
O
Active-low open-drain output, asserted during
overcurrent, overtemperature, or reverse-voltage
conditions.
OUT
6
6
1
1
O
Power-switch output
ILIM
5
5
2
2
I
External resistor used to set current-limit
threshold; recommended 14.3 kΩ ≤ RILIM ≤ 80.6
kΩ.
PowerPAD™
–
–
PAD
PAD
Connect ground connection externally to
POWER PAD
Internally connected to GND; used to heat-sink
the part to the circuit board traces, connect to
GND pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1) (2)
Voltage range on IN, OUT, EN or EN, ILIM, FAULT
Voltage range from IN to OUT
IOUT
Continuous output current
VALUE
UNIT
–0.3 to 7
V
–7 to 7
V
Internally limited
See "Thermal Information
Table"
Continuous total power dissipation
FAULT sink current
ILIM source current
25
mA
1
mA
TJ
Maximum junction temperature
–40 to 150
°C
TSgt
Storage temperature
–65 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Voltages are referenced to GND unless otherwise noted.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
VIN
MIN
MAX
UNIT
V
Input voltage, IN
VEN
Enable voltage
V/EN
2.5
6.5
TPS2550
0
6.5
TPS2551
0
6.5
0
1.1
14.3
80.6
kΩ
0
10
mA
–40
125
°C
IOUT
Continuous output current, OUT
RILIM
Current-limit set resistor from ILIM to GND
I/FAULT
FAULT sink current
TJ
Operating virtual junction temperature DRV & DBV
V
A
7.4 Thermal Information
BOARD
PACKAGE
THERMAL
RESISTANCE
θJA
THERMAL
RESISTANCE
θJC
TA ≤ 25°C
POWER
RATING
DERATING
FACTOR
ABOVE
TA = 25°C
TA = 70°C
POWER
RATING
Low-K(1)
DBV
350°C/W
55°C/W
285 mW
2.85 mW/°C
High-K(2)
DBV
160°C/W
55°C/W
625 mW
6.25 mW/°C
Low-K(1)
DRV
140°C/W
20°C/W
715 mW
High-K(2)
DRV
75°C/W
20°C/W
1330 mW
(1)
(2)
TA = 85°C
POWER
RATING
TA = 110°C
POWER
RATING
155 mW
114 mW
42 mW
340 mW
250 mW
93 mW
7.1 mW/°C
395 mW
285 mW
107 mW
13.3 mW/°C
730 mW
530 mW
200 mW
The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
7.5 Electrical Characteristics
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
MIN
TYP
MAX
94
100
UNIT
POWER SWITCH
DBV package, TJ = 25 °C
DBV package, –40 °C ≤TJ ≤125 °C
rDS(on)
Static drain-source on-state resistance
140
DRV package, TJ = 25 °C
100
DRV package, –40 °C ≤TJ ≤105 °C
tf
Rise time, output
Fall time, output
150
VIN = 6.5 V
1.0
1.5
VIN = 2.5 V
0.65
1.0
VIN = 6.5 V
mΩ
145
DRV package, –40 °C ≤TJ ≤125 °C
tr
115
CL = 1 μF, RL = 100 Ω,
(see Figure 8-1)
VIN = 2.5 V
0.2
0.5
0.2
0.5
ms
ENABLE INPUT EN OR EN
VIH
High-level input voltage
VIL
Low-level input voltage
IEN
Input current
ton
Turnon time
toff
Turnoff time
1.1
0.66
VEN = 0 V or 6.5 V, V/EN = 0 V or 6.5 V
–0.5
CL = 1 μF, RL = 100 Ω, (see Figure 8-1)
V
0.5
μA
3
ms
3
ms
CURRENT LIMIT
IOS
IOC
6
Short-circuit current, OUT connected to GND
Current-limit threshold (Maximum DC output current IOUT delivered to load)
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RILIM = 80.6 kΩ
160
265
350
RILIM = 38.3 kΩ
350
550
700
RILIM = 15 kΩ
1100
1450
1700
RILIM = 80.6 kΩ
340
365
390
RILIM = 38.3 kΩ
670
715
755
RILIM = 15 kΩ
1600
1700
1800
mA
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7.5 Electrical Characteristics (continued)
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
TEST CONDITIONS(1)
PARAMETER
tIOS
Response time to short circuit
MIN
VIN = 5.0 V (see Figure 8-2)
TYP
MAX
UNIT
2
μs
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point
(VOUT – VIN)
Time from reverse-voltage condition to
MOSFET turn off
VIN = 5.0 V
95
135
190
mV
3
5
7
ms
0.1
1
μA
SUPPLY CURRENT
IIN_off
Supply current, low-level output
VIN = 6.5 V, No load on OUT, V EN = 6.5 V or VEN = 0 V, 14.3 kΩ ≤
RILIM ≤ 80.6 kΩ
IIN_on
Supply current, high-level output
VIN = 6.5 V, No load on OUT, V EN = 0 V or
VEN = 6.5 V
RILIM = 15 kΩ
150
μA
RILIM = 80.6 kΩ
130
μA
IREV
Reverse leakage current
VOUT = 6.5 V, VIN = 0 V
TJ = 25 °C
0.01
1
μA
2.45
UNDERVOLTAGE LOCKOUT
VUVLO
Low-level input voltage, IN
VIN rising
2.35
Hysteresis, IN
TJ = 25 °C
25
V
mV
FAULT FLAG
VOL
Output low voltage, FAULT
I/FAULT = 1 mA
180
mV
Off-state leakage
V/FAULT = 6.5 V
1
μA
FAULT deglitch
FAULT assertion or de-assertion due to overcurrent condition
5
7.5
10
ms
FAULT assertion or de-assertion due to reverse-voltage condition
2
4
6
ms
THERMAL SHUTDOWN
Thermal shutdown threshold
155
°C
Thermal shutdown threshold in current-limit
135
°C
Hysteresis
(1)
15
°C
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
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7.6 Typical Characteristics
8
Figure 7-1. Turnon Delay and Rise Time
Figure 7-2. Turnoff Delay and Fall Time
Figure 7-3. Device Enabled into Short-Circuit
Figure 7-4. Full-Load to Short-Circuit Transient
Response
Figure 7-5. Short-Circuit to Full-Load Recovery
Response
Figure 7-6. No-Load to Short-Circuit Transient
Response
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Figure 7-8. No Load to 1Ω Transient Response
Figure 7-7. Short-Circuit to No-Load Recovery
Response
Figure 7-9. 1Ω to No Load Transient Response
Figure 7-10. Reverse-Voltage Protection Response
2.40
UVLO - Undervoltage Lockout - V
2.39
2.38
2.37
UVLO Rising
2.36
2.35
2.34
UVLO Falling
2.33
2.32
2.31
Figure 7-11. Reverse-Voltage Protection Recovery
2.30
-50
0
50
100
150
TJ - Junction Temperature - °C
Figure 7-12. UVLO – Undervoltage Lockout – V
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150
0.45
VIN = 6.5 V
0.40
VIN = 5 V
0.35
VIN = 3.3 V
RILIM = 20 kW
0.30
0.25
VIN = 2.5 V
0.20
0.15
0.10
0.05
0
50
TJ - Junction Temperature - °C
100
VIN = 5 V
105
VIN = 3.3 V
90
75
VIN = 2.5 V
60
45
30
0
-50
150
Figure 7-13. IIN – Supply Current, Output Disabled
– μA
0
50
TJ - Junction Temperature - °C
100
150
Figure 7-14. IIN – Supply Current, Output Enabled –
μA
150
rDS(on) - Static Drain-Source On-State Resistance - mW
20
VIN = 5 V,
TA = 25°C
18
16
Current Limit Response - ms
120
15
0
-50
14
12
10
8
6
4
2
0
0
1.5
3
Peak Current - A
4.5
Figure 7-15. Current Limit Response – μs
10
VIN = 6.5 V
135
IIN - Supply Current, Output Enabled - mA
IIN - Supply Current, Output Disabled - mA
0.50
6
125
DRV Package
100
DBV Package
75
50
25
0
-50
0
50
TJ - Junction Temperature - °C
100
150
Figure 7-16. MOSFET rDS(on) Vs. Junction
Temperature
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8 Parameter Measurement Information
OUT
tf
tr
RL
CL
90%
VOUT
10%
90%
10%
TEST CIRCUIT
50%
VEN
VEN
50%
toff
ton
VOUT
50%
50%
toff
ton
90%
90%
VOUT
10%
10%
VOLTAGE WAVEFORMS
Figure 8-1. Test Circuit and Voltage Waveforms
IOS
IOUT
tIOS
Figure 8-2. Response Time to Short-Circuit Waveform
VOUT
DECREASING
LOAD
RESISTANCE
DECREASING
LOAD
RESISTANCE
IOS
IOC
IOUT
Figure 8-3. Output Voltage vs. Current-Limit Threshold
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9 Detailed Description
9.1 Overview
The TPS2550/51 are current-limited, power distribution switches using N-channel MOSFETs for applications
where short-circuits or heavy capacitive loads are encountered. These devices allow the user to program the
current-limit threshold between 100 mA and 1.1 A via an external resistor. Additional device shutdown features
include overtemperature protection and reverse-voltage protection. The device incorporates an internal charge
pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to
the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The
charge pump operates from input voltages as low as 2.5 V and requires little supply current. The driver controls
the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of the
output voltage to limit large current and voltage surges and provide built-in soft-start functionality.
9.2 Functional Block Diagram
-
Reverse
Voltage
Comparator
+
IN
OUT
CS
4-ms
Deglitch
Current
Sense
Charge
Pump
Driver
EN
Current
Limit
FAULT
UVLO
GND
Thermal
Sense
8-ms Deglitch
ILIM
9.3 Feature Description
9.3.1 Overcurrent
The TPS2550/51 responds to an overcurrent condition by limiting its output current to the IOC and IOS levels
shown in Figure 9-1. Three response profiles are possible depending on the loading conditions and are
summarized in Figure 8-3.
One response profile occurs if the TPS2550/51 is enabled into a short-circuit. The output voltage is held near
zero potential with respect to ground and the TPS2550/51 ramps the output current to IOS (see Figure 7-3).
A second response profile occurs if a short is applied to the output after the TPS2550/51 is enabled. The
device responds to the overcurrent condition within time tIOS (see Figure 8-2). The current-sense amplifier is
over-driven during this time and momentarily disables the internal current-limit MOSFET. The current-sense
amplifier gradually recovers and limits the output current to IOS.
A third response profile occurs if the load current gradually increases. The device first limits the load current to
IOC. If the load demands a current greater than IOC, the TPS2550/51 folds back the current to IOS and the output
voltage decreases to IOS x RLOAD for a resistive load, which is shown in Figure 8-3.
The TPS2550/51 thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the above cases. The device turns off when the junction temperature exceeds 135°C (typ). The device
remains off until the junction temperature cools 15°C (typ) and then restarts. The TPS2550/51 cycles on/off until
the overload is removed (see Figure 7-5 and Figure 7-7) .
12
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9.3.2 Reverse-Voltage Protection
The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typical) for 4-ms. This feature prevents damage to devices on the input side of the
TPS2550/51 by preventing significant current from sinking into the input capacitance. The N-channel MOSFET
is allowed to turn-on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The
reverse-voltage comparator also asserts the FAULT output (active-low) after 4-ms.
9.3.3 FAULT Response
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage
condition. The output remains asserted until the fault condition is removed. The TPS2550/51 is designed to
eliminate false FAULT reporting by using an internal delay "deglitch" circuit for overcurrent (7.5-ms) and reversevoltage (4-ms) conditions without the need for external circuitry. This "deglitch" circuit ensures that FAULT is
not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch
circuitry delays entering and leaving fault conditions. Overtemperature conditions are not deglitched and assert
the FAULT signal immediately.
9.3.4 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large
current surges.
9.3.5 ENABLE ( EN or EN)
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the
supply current. The supply current is reduced to less than 1-μA when a logic high is present on EN or when a
logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver, control circuits,
and power switch. The enable input is compatible with both TTL and CMOS logic levels.
9.3.6 Thermal Sense
The TPS2550/51 protects itself with two independent thermal sensing circuits that monitor the operating
temperature of the power-switch and disables operation if the temperature exceeds recommended operating
conditions. The device operates in constant-current mode during an overcurrent conditions, which increases
the voltage drop across power-switch. The power dissipation in the package is proportional to the voltage drop
across the power-switch, so the junction temperature rises during an overcurrent condition. The first thermal
sensor turns off the power-switch when the die temperature exceeds 135°C and the part is in current limit.
The second thermal sensor turns off the power-switch when the die temperature exceeds 155°C regardless
of whether the power-switch is in current limit. Hysteresis is built into both thermal sensors, and the switch
turns on after the device has cooled approximately 15°C. The switch continues to cycle off and on until the
fault is removed. The open-drain false reporting output FAULT is asserted (active low) immediately during an
overtemperature shutdown condition.
9.3.7 Device Functional Modes
There are no other functional modes.
9.4 Programming
9.4.1 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable via an external resistor. Many applications require that the
minimum current-limit is above a certain current level or that the maximum current-limit is below a certain current
level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for RILIM.
The following equations and Figure 9-1 can be used to calculate the resulting overcurrent threshold for a given
external resistor value ®ILIM). Figure 9-1 includes current-limit tolerance due to variations caused by temperature
and process. To reduce parasitic effects on the current-limit accuracy, make the traces routing the RILIM resistor
to the TPS2550/51 as short as possible.
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There are two important current-limit thresholds for the device and are related by Figure 8-3. The first threshold
is the short-circuit current threshold IOS. IOS is the current delivered to the load if the part is enabled into
a short-circuit or a short-circuit is applied during normal operation. The second threshold is the overcurrent
threshold IOC. IOC is the peak DC current that can be delivered to the load before the device begins to limit
current. IOC is important if ramped loads or slow transients are common to the application. It is important to
consider both IOS and IOC when choosing RILIM. RILIM can be selected to provide a current-limit threshold that
occurs 1) above a minimum load current or 2) below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired
load current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current-limit
above a minimum threshold is important to ensure start-up into full-load or heavy capacitive loads. The resulting
maximum DC load current is the intersection of the selected value of RILIM and the IOC(max) curve.
To design below a maximum DC current level, find the intersection of RILIM and the maximum desired load
current on the IOC(max) curve and choose a value of RILIM above this value. Programming the current-limit below
a maximum threshold is important to avoid current-limiting upstream power supplies causing the input voltage
bus to droop. The resulting minimum short-circuit current is the intersection of the selected value of RILIM and the
IOS(min) curve.
Overcurrent Threshold Equations (IOC):
•
•
•
IOC(max) (mA) = (24500 V) / (RILIM kΩ) 0.975 + 50
IOC(typ) (mA) = (23800 V) / (RILIM kΩ) 0.985 + 50
IOC(min) (mA) = (23100 V) / (RILIM kΩ) 0.996 + 50
Short-Circuit Current Equations (IOS):
•
•
•
IOS(max) (mA) = (25500 V) / (RILIM kΩ) 1.013 + 50
IOS(typ) (mA) = (28700 V) / (RILIM kΩ) 1.114 + 50
IOS(min) (mA) = (39700 V) / (RILIM kΩ) 1.342 + 50
where 14.3 kΩ ≤ RILIM ≤ 80.6 kΩ. IOS(typ) and IOS(max) are not plotted to improve graph clarity.
1800
Current-Limit Threshold - mA
1700
1600
1500
1400
IOC(max)
1300
1200
1100
1000
IOC(typ)
IOC(min)
900
800
700
600
500
400
300
200
100
0
15
IOS(min)
20
25
30
35
40
45
50
RILIM - kW
55
60
65
70
75
80
Figure 9-1. Current-Limit Threshold Vs.RILIM
14
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The TPS255x current-limited power switch uses N-channel MOSFETs in applications requiring continuous load
current. The device enters constant-current mode when the load exceeds the current limit threshold.
10.2 Typical Applications
10.2.1 Two-Level Current-Limit Circuit
Some applications require different current-limit thresholds depending on external system conditions. Figure
10-1 shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit
threshold is set by the total resistance from ILIM to GND (see previously discussed "Programming the CurrentLimit Threshold" section). A logic-level input enables/disables MOSFET Q1 and changes the current-limit
threshold by modifying the total resistance from ILIM to GND. Additional MOSFETs/resistor combinations can be
used in parallel to Q1/R2 to increase the number of additional current-limit levels.
Note
Do not drive the ILIM directly with an external signal.
Input
TPS2550/51
0.1 mF
IN
Output
OUT
RFAULT
100 kW
FAULT Signal
FAULT
Control Signal
EN
CLOAD
R1
80.6 kW
ILIM
R2
20 kW
GND
Power Pad
RLOAD
Current Limit
Control Signal
Q1
2N7002
Figure 10-1. Two-Level Current-Limit Circuit
10.2.2 Design Requirements
For this example, use the parameters shown in Table 10-1.
Table 10-1. Design Requirements
PARAMETER
VALUE
Input voltage
5V
Output voltage
5V
Above a minimum current limit
1000 mA
Below a maximum current limit
1250 mA
10.2.3 Detail Design Procedures
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10.2.3.1 Designing Above a Minimum Current Limit
Some applications require that current-limiting cannot occur below a certain threshold. For this example, assume
that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the
IOS equations and Figure 9-1 to select RILIM.
• IOS(min) (mA) = 1000 mA
• IOS(min) (mA) = (39700 V) / (RILIM (kΩ)) 1.342 + 50
• RILIM (kΩ) = [(39700 V) / (IOS(min) (mA) - 50)]1/1.342
• RILIM = 16.14 kΩ
Select the closest 1% resistor less than the calculated value: RILIM = 16 kΩ. This selection sets the minimum
current-limit threshold at 1 A . Use the IOC equations, Figure 9-1, and the previously calculated value for RILIM to
calculate the maximum resulting current-limit threshold.
• RILIM = 16 kΩ
• IOC(max) (mA) = (24500 V) / (RILIM (kΩ)) 0.975 + 50
• IOC(max) (mA) = (24500 V) / (16 (kΩ))0.975 + 50
• IOC(max) = 1691 mA
The resulting maximum current-limit threshold is 1.69 A with a 16 kΩ resistor.
10.2.3.2 Designing Below a Maximum Current Limit
Some applications require that current-limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 1.25 A to protect an up-stream power supply. Use
the IOC equations and Figure 9-1 to select RILIM.
• IOC(max) (mA) = 1250 mA
• IOC(max) (mA) = (24500 V) / (RILIM (kΩ)) 0.975 + 50
• RILIM (kΩ) = [(24500 V) / (IOC(max) (mA) - 50)]1/0.975
• RILIM = 22.05 kΩ
Select the closest 1% resistor greater than the calculated value: RILIM = 22 kΩ. This selection sets the maximum
current-limit threshold at 1.25 A . Use the IOS equations, Figure 9-1, and the previously calculated value for RILIM
to calculate the minimum resulting current-limit threshold.
• RILIM = 22 kΩ
• IOS(min) (mA) = (39700 V) / (RILIM (kΩ)) 1.342 + 50
• IOS(min) (mA) = (39700 V) / (22 (kΩ)) 1.342 + 50
• IOS(min) = 677 mA
The resulting minimum current-limit threshold is 677 mA with a 22 kΩ resistor.
10.2.3.3 Input and Output Capacitance
Input and output capacitance improve the performance of the device; make sure to optimize the actual
capacitance for the particular application. For all applications, a 0.01 μF to 0.1μF ceramic bypass capacitor
between IN and GND is recommended as close to the device as possible for local noise de-coupling. This
precaution reduces ringing on the input due to power-supply transients. Additional input capacitance may be
needed on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device
during heavy transients, which is especially important during bench testing when long, inductive cables are used
to connect the evaluation board to the bench power-supply.
Placing a high-value electrolytic capacitor on the output pin is recommended when the large transient currents
are expected on the output. Additionally, bypassing the output with a 0.01 μF to 0.1 μF ceramic capacitor
improves the immunity of the device to short-circuit transients.
10.2.4 Auto-Retry Functionality
Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor
and capacitor. During a fault condition, FAULT pulls low disabling the part. The part is disabled when EN is
pulled low, and FAULT goes high impedance allowing CRETRY to begin charging. The part re-enables when the
16
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voltage on EN reaches the turnon threshold, and the auto-retry time is determined by the resistor/capacitor time
constant. The part continues to cycle in this manner until the fault condition is removed.
TPS2551
0.1 mF
Input
Output
IN
OUT
RLOAD
RFAULT
100 kW
CLOAD
ILIM
FAULT
1 kW
RILIM
GND
EN
CRETRY
20 kW
Power Pad
0.1 mF
Figure 10-2. Auto-Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
The figure below shows how an external logic signal can drive EN through RFAULT and maintain auto-retry
functionality. The resistor/capacitor time constant determines the auto-retry time-out period.
TPS2551
Input
IN
Output
OUT
RLOAD
0.1 mF
External Logic
Signal & Driver
CLOAD
RFAULT
100 kW
CRETRY
FAULT
1kW
EN
ILIM
RILIM
GND
20 kW
Power Pad
0.1 mF
Figure 10-3. Auto-Retry Functionality With External EN Signal
10.2.5 Latch-Off Functionality
The circuit in Figure 10-4 uses an SN74HC00 quad-NAND gate to implement overcurrent latch-off. The
SN74HC00 high-speed CMOS logic gate is selected because it operates over the 2.5V – 6.5V range of the
TPS2550/51.
This circuit is designed to work with the active-high TPS2551. ENABLE must be logic low during start-up until
VIN is stable to ensure that the switch initializes in the OFF state. A logic high on ENABLE turns on the switch
after VIN is stable. FAULT momentarily pulls low during an overcurrent condition, which latches STAT logic low
and disables the switch. The host can monitor STAT for an overcurrent condition. Toggling ENABLE resets STAT
and re-enables the switch.
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TPS2551
0.1 mF
Input
Output
IN
0.1 mF
OUT
RLOAD
10 kW
CLOAD
External Logic
Enable Signal
ILIM
EN
15 kW
GND
FAULT
RFAULT
10 kW
Power Pad
SN74HC00D
STAT
Figure 10-4. Overcurrent Latch-Off Using a Quad-NAND Gate
10.2.6 Typical Application as USB Power Switch
TPS2550/51
5 V USB
USB Data
0.1 mF
INPUT
USB
Port
OUT
IN
RFAULT
100 kW
120 mF *
FAULT Signal
FAULT
ILIM
Control Signal
EN
GND
RILIM
15 kW
PowerPAD
* USB Requirement that downstream-facing ports
are bypassed with at least 120 mF per hub
Figure 10-5. Typical Application as USB Power Switch
10.2.6.1 Design Requirements
For this example, use the parameters shown in Table 10-2.
Table 10-2. Design Requirements
PARAMETER
VALUE
Input voltage
5V
Output voltage
5V
Current
1250 mA
10.2.6.1.1 USB Power-Distribution Requirements
USB can be implemented in several ways regardless of the type of USB device being developed. Several
power-distribution features must be implemented.
•
•
•
18
SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions
BPHs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 μF)
Functions must:
– Limit inrush currents
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– Power up at <100 mA
The feature set of the TPS2550/51 meets each of these requirements. The integrated current-limiting and
overcurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the
need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.
10.2.6.2 Detail Design Procedures
10.2.6.2.1 Universal Serial Bus (USB) Power-Distribution Requirements
One application for this device is for current-limiting in universal serial bus (USB) applications. The original
USB interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth
PC peripherals (for example keyboards, printers, scanners, and mice). As the demand for more bandwidth
increased, the USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire
USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided
for differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3
V from the 5-V input or its own internal power supply. The USB specification classifies two different classes
of devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA
as defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. Always reference the latest USB standard when considering the current-limit threshold
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or