Manual / Guide · 2023
Terasic DE10-Nano User Manual (rev. E hardware, v2.6)
The MiSTer base board: HPS/ARM and the GPIO used by the I/O board's user port.
- de10-nano
- mister
- cyclone v
- fpga
Manual / Guide · 2023
The MiSTer base board: HPS/ARM and the GPIO used by the I/O board's user port.
DE10-Nano User Manual 1 www.terasic.com August 9, 2023 Chapter 1 DE10-Nano Development Kit 3 1.1 Package Contents 1.2 DE10-Nano System CD 1.3 Getting Help Chapter 2 3 4 4 Introduction of the DE10-Nano Board 2.1 Layout and Components 2.2 Block Diagram of the DE10-Nano Board Chapter 3 5 7 Using the DE10-Nano Board 10 3.1 Settings of FPGA Configuration Mode 3.2 Configuration of Cyclone V SoC FPGA on DE10-Nano 3.3 Board Status Elements 3.4 Board Reset Elements 3.5 Clock Circuitry 3.6 Peripherals Connected to the FPGA 3.6.1 User Push-buttons, Switches and LEDs 3.6.2 2x20 GPIO Expansion Headers 3.6.3 Arduino Uno R3 Expansion Header 3.6.4 A/D Converter and Analog Input 3.6.5 HDMI TX Interface 3.7 Peripherals Connected to Hard Processor System (HPS) 3.7.1 User Push-buttons and LEDs 3.7.2 Gigabit Ethernet 3.7.3 UART 3.7.4 DDR3 Memory 3.7.5 Micro SD Card Socket 3.7.6 USB 2.0 OTG PHY 3.7.7 G-sensor 3.7.8 LTC Connector 10 11 17 18 20 21 22 25 28 29 31 33 33 34 35 36 38 39 40 41 Chapter 4 DE10-Nano System Builder 43 4.1 Introduction 4.2 Design Flow 4.3 Using DE10-Nano System Builder DE10-Nano User Manual 5 1 43 43 44 www.terasic.com August 9, 2023 Chapter 5 Examples For FPGA 50 5.1 DE10-Nano Factory Configuration 5.2 ADC Reading 5.3 HDMI TX 5.4 DDR3_VIP 5.5 DDR3_RTL 5.6 Nios II Access HPS DDR3 Chapter 6 50 51 53 57 62 68 Examples for HPS SoC 73 6.1 Hello Program 6.2 Users LED and KEY 6.3 I2C Interfaced G-sensor 6.4 Setup USB Wi-Fi Dongle 6.5 Query Internet Time Chapter 7 73 75 81 84 87 Examples for using both HPS SoC and FGPA 7.1 Required Background 7.2 System Requirements 7.3 AXI bridges in Intel SoC FPGA 7.4 GHRD Project 7.5 Compile and Programming 7.6 Develop the C Code Chapter 8 90 90 91 93 94 95 Programming the EPCS Device 101 8.1 Before Programming Begins 8.2 Convert .SOF File to .JIC File 8.3 Write JIC File into the EPCS Device 8.4 Erase the EPCS Device 8.5 EPCS Programming via nios-2-flash-programmer Chapter 9 Appendix A User Manual 2 101 101 106 108 109 110 9.1 Revision History DE10-Nano 90 110 www.terasic.com August 9, 2023 Chapter 1 DE10-Nano Development Kit T he DE10-Nano Development Kit presents a robust hardware design platform built around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Intel’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE10-Nano development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications. The DE10-Nano Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later. 1.1 Package Contents Figure 1-1 shows a photograph of the DE10-Nano package. Figure 1-1 The DE10-Nano package contents DE10-Nano User Manual 3 www.terasic.com August 9, 2023 The DE10-Nano package includes: The DE10-Nano development board DE10-Nano Quick Start Guide USB cable Type A to Mini-B for FPGA programming or UART control USB cable Type A to Micro-B for USB OTG connect to PC 5V DC power adapter microSD Card (Installed) Four Silicon Footstands 1.2 DE10-Nano System CD The DE10-Nano System CD contains all the documents and supporting materials associated with DE10-Nano, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://de10-nano.terasic.com/cd. 1.3 Getting Help Here are the addresses where you can get help if you encounter any problems: Terasic Technologies 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan Email: [email protected] Tel.: +886-3-575-0880 Website: DE10-Nano.terasic.com DE10-Nano User Manual 4 www.terasic.com August 9, 2023 Chapter 2 Introduction of the DE10-Nano Board T his chapter provides an introduction to the features and design characteristics of the board. 2.1 Layout and Components Figure 2-1 and Figure 2-2 shows a photograph of the board. It depicts the layout of the board and indicates the location of the connectors and key components. Figure 2-1 DE10-Nano development board (top view) DE10-Nano User Manual 5 www.terasic.com August 9, 2023 Figure 2-2 DE10-Nano development board (bottom view) The DE10-Nano board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the board: FPGA Cyclone® V SE 5CSEBA6U23I7NDK device Serial configuration device – EPCS64 USB-Blaster II onboard for programming; JTAG Mode 2 push-buttons 4 slide switches 8 green user LEDs Three 50MHz clock sources from the clock generator Two 40-pin expansion header One Arduino expansion header (Uno R3 compatibility), can connect with Arduino shields. One 10-pin Analog input expansion header. (shared with Arduino Analog input) A/D converter, 4-wire SPI interface with FPGA HDMI TX, compatible with DVI v1.0 and HDCP v1.4 HPS (Hard Processor System) 800MHz Dual-core ARM Cortex-A9 processor 1GB DDR3 SDRAM (32-bit data bus) DE10-Nano User Manual 6 www.terasic.com August 9, 2023 1 Gigabit Ethernet PHY with RJ45 connector port USB OTG, USB Micro-AB connector Micro SD card socket Accelerometer (I2C interface + interrupt) UART to USB, USB Mini-B connector Warm reset button and cold reset button One user button and one user LED LTC 2x7 expansion header 2.2 Block Diagram of the DE10-Nano Board Figure 2-3 is the block diagram of the board. All the connections are established through the Cyclone V SoC FPGA device to provide maximum flexibility for users. Users can configure the FPGA to implement any system design. Detailed information about Figure 2-3 are listed below. Figure 2-3 Block diagram of DE10-Nano DE10-Nano User Manual 7 www.terasic.com August 9, 2023 FPGA Device Cyclone V SoC 5CSEBA6U23I7NDK Device Dual-core ARM Cortex-A9 (HPS) 110K programmable logic elements 5,570 Kbits embedded memory 6 fractional PLLs Configuration and Debug Serial configuration device – EPCS64 on FPGA Onboard USB-Blaster II (Mini-B USB connector) Memory Device 1GB (2x256Mx16) DDR3 SDRAM on HPS Micro SD card socket on HPS Communication One USB 2.0 OTG (ULPI interface with USB Micro-AB connector) UART to USB (USB Mini-B connector) 10/100/1000 Ethernet Connectors Two 40-pin expansion headers Arduino expansion header One 10-pin ADC input header One LTC connector (one Serial Peripheral Interface (SPI) Master ,one I2C and one GPIO interface ) D is p la y HDMI TX, compatible with DVI v1.0 and HDCP v1.4 ADC 12-Bit Resolution, 500Ksps Sampling Rate. SPI Interface. 8-Channel Analog Input. Input Range : 0V ~ 4.096V. DE10-Nano User Manual 8 www.terasic.com August 9, 2023 Switches, Buttons, and Indicators 3 user Keys (FPGA x2, HPS x1) 4 user switches (FPGA x4) 9 user LEDs (FPGA x8, HPS x 1) 2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n) Sensors G-Sensor on HPS Power 5V DC input DE10-Nano User Manual 9 www.terasic.com August 9, 2023 Chapter 3 Using the DE10-Nano Board T his chapter provides an instruction to use the board and describes the peripherals. 3.1 Settings of FPGA Configuration Mode When the DE10-Nano board is powered on, the FPGA can be configured from EPCS or HPS. The MSEL[4:0] pins are used to select the configuration scheme. It is implemented as a 6-pin DIP switch SW10 on the DE10-Nano board, as shown in Figure 3-1. Table 3-1 shows the relation between MSEL[4:0] and DIP switch (SW10). Figure 3-1 DIP switch (SW10) setting of FPPx32 mode. Table 3-1 FPGA Configuration Mode Switch (SW10) Board Reference Signal Name SW10.1 MSEL0 SW10.2 MSEL1 SW10.3 MSEL2 DE10-Nano User Manual Description Default Use these pins to set the FPGA Configuration scheme 10 ON (“0”) OFF (“1”) ON (“0”) www.terasic.com August 9, 2023 SW10.4 MSEL3 OFF (“1”) SW10.5 MSEL4 ON (“0”) SW10.6 N/A N/A N/A Table 3-2 shows MSEL[4:0] setting for FPGA configure, and default setting is FPPx32 Mode on DE10-Nano Board. When the board is powered on and MSEL[4:0] set to “10010”, the FPGA is configured from EPCS, which is pre-programmed with the default code. If developers using the "Linux LXDE Desktop" SD Card image, the MSEL[4:0] needs to be set to “01010” before the board is powered on. Table 3-2 MSEL Pin Settings for FPGA Configure of DE10-Nano Board Configuration AS SW10.1 SW10.2 SW10.3 SW10.4 SW10.5 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 ON OFF ON ON OFF SW10.6 N/A Description FPGA configured from EPCS FPPx32(1) / FPGA configured Compression from HPS software: Enabled / Fast POR ON OFF ON OFF ON N/A U-Boot, with image stored on the SD card, like LXDE (Default) Desktop (default) FPPx16 / FPGA configured Compression Disabled / Fast POR from HPS software: ON ON ON ON ON N/A U-Boot, with image stored on the SD card (1): Please refer to the following link: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclon e-v/cv_5v4.pdf , See Table 4-1: Configuration Schemes for FPGA Configuration by the HPS 3.2 Configuration of Cyclone V SoC FPGA on DE10-Nano There are two types of programming method supported by DE10-Nano: 1. JTAG programming: It is named after the IEEE standards Joint Test Action Group. DE10-Nano User Manual 11 www.terasic.com August 9, 2023 The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will retain its current status as long as the power keeps applying to the board; the configuration information will be lost when the power is off. 2. AS programming: The other programming method is Active Serial configuration. The configuration bit stream is downloaded into the serial configuration device (EPCS64), which provides non-volatile storage for the bit stream. The information is retained within EPCS64 even if the DE10-Nano board is turned off. When the board is powered on, the configuration data in the EPCS64 device is automatically loaded into the Cyclone V SoC FPGA. JTAG Chain on DE10-Nano Board The FPGA device can be configured through JTAG interface on DE10-Nano board, but the JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA device. Figure 3-2 illustrates the JTAG chain on DE10-Nano board. In addition, the DE10-Nano has one external JTAG Header (J8) reserved for users to connect to JTAG chain of the DE10-Nano via external blaster. The J8 header is not installed, so users need to solder a 2.54mm 2 x 5 male pin header if it is necessary. Figure 3-2 Path of the JTAG chain Configure the FPGA in JTAG Mode There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is programmed in JTAG mode step by step. Open the Quartus II programmer, please Choose Tools > Programmer. The Programmer window opens. Please click “Hardware Setup”, as circled in Figure 3-3. DE10-Nano User Manual 12 www.terasic.com August 9, 2023 Figure 3-3 Programmer Window If it is not already turned on, turn on the DE-SoC [USB-1] option under currently selected hardware and click “Close” to close the window. See Figure 3-4. Figure 3-4 Hardware Setting Return to the Quartus II programmer and click “Auto Detect”, as circled in Figure 3-5 DE10-Nano User Manual 13 www.terasic.com August 9, 2023 Figure 3-5 Detect FPGA device in JTAG mode If the device is detected, the window of the selection device is opened, Please select detected device associated with the board and click “OK” to close the window, as circled in Figure 3-6. Figure 3-6 Select 5CSEBA6 device Both FPGA and HPS are detected, as shown in Figure 3-7. DE10-Nano User Manual 14 www.terasic.com August 9, 2023 Figure 3-7 FPGA and HPS detected in Quartus programmer Right click on the FPGA device and open the .sof file to be programmed, as highlighted in Figure 3-8. Figure 3-8 Open the .sof file to be programmed into the FPGA device DE10-Nano User Manual 15 www.terasic.com August 9, 2023 Select the .sof file to be programmed, as shown in Figure 3-9. Figure 3-9 Select the .sof file to be programmed into the FPGA device Click “Program/Configure” check box and then click “Start” button to download the .sof file into the FPGA device, as shown in Figure 3-10. Figure 3-10 Program .sof file into the FPGA device Configure the FPGA in AS Mode The DE10-Nano board uses a serial configuration device (EPCS64) to store configuration data for the Cyclone V SoC FPGA. This configuration data is DE10-Nano User Manual 16 www.terasic.com August 9, 2023 automatically loaded from the serial configuration device chip into the FPGA when the board is powered up. Users need to use Serial Flash Loader (SFL) to program the serial configuration device via JTAG interface. The FPGA-based SFL is a soft intellectual property (IP) core within the FPGA that bridge the JTAG and Flash interfaces. The SFL Megafunction is available in Quartus II. Figure 3-11 shows the programming method when adopting SFL solution. Please refer to Chapter 8: Steps of Programming the Serial Configuration Device for the basic programming instruction on the serial configuration device. Figure 3-11 Programming a serial configuration device with SFL solution 3.3 Board Status Elements In addition to the 9 LEDs that FPGA/HPS device can control, there are 6 indicators which can indicate the board status (See Figure 3-12), please refer the details in Table 3-3 DE10-Nano User Manual 17 www.terasic.com August 9, 2023 Figure 3-12 LED Indicators on DE10-Nano Table 3-3 LED Indicators Board Reference LED Name Description LED9 3.3-V Power Illuminate when 3.3V power is active. LED10 CONF_DONE Illuminates when the FPGA is successfully configured. LED11 JTAG_TX Illuminate when data is transferred from JTAG to USB Host. LED12 JTAG_RX Illuminate when data is transferred from USB Host to JTAG. TXD UART TXD Illuminate when data is transferred from FT232R to USB Host. RXD UART RXD Illuminate when data is transferred from USB Host to FT232R. 3.4 Board Reset Elements There are two HPS reset buttons on DE10-Nano, HPS (cold) reset and HPS warm reset, as shown in Figure 3-13. Table 3-4 describes the purpose of these two HPS reset buttons. Figure 3-14 is the reset tree for DE10-Nano. DE10-Nano User Manual 18 www.terasic.com August 9, 2023 Figure 3-13 HPS cold reset and warm reset buttons on DE10-Nano Table 3-4 Description of Two HPS Reset Buttons on DE10-Nano Board Reference Signal Name KEY4 HPS_RESET_N KEY3 HPS_WARM_RST_N DE10-Nano User Manual Description Cold reset to the HPS, Ethernet PHY and USB host device. Active low input which resets all HPS logics that can be reset. Warm reset to the HPS block. Active low input affects the system reset domain for debug purpose. 19 www.terasic.com August 9, 2023 Figure 3-14 HPS reset tree on DE10-Nano board 3.5 Clock Circuitr y Figure 3-15 shows the default frequency of all external clocks to the Cyclone V SoC FPGA. A clock generator is used to distribute clock signals with low jitter. The two 50MHz clock signals connected to the FPGA are used as clock sources for user logic. Three 25MHz clock signal are connected to two HPS clock inputs, and the other one is connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected to the USB controller for USB Blaster II circuit and FPGA. One 24MHz clock signals are connected to the clock inputs of USB OTG PHY. The associated pin assignment for clock inputs to FPGA I/O pins is listed in Table 3-5. DE10-Nano User Manual 20 www.terasic.com August 9, 2023 Figure 3-15 Block diagram of the clock distribution on DE10-Nano Table 3-5 Pin Assignment of Clock Inputs Signal Name FPGA Pin No. Description I/O Standard FPGA_CLK1_50 PIN_V11 50 MHz clock input 3.3V FPGA_CLK2_50 PIN_Y13 50 MHz clock input 3.3V FPGA_CLK3_50 PIN_E11 50 MHz clock input (share with FPGA_CLK1_50) 3.3V HPS_CLK1_25 PIN_E20 25 MHz clock input 3.3V HPS_CLK2_25 PIN_D20 25 MHz clock input 3.3V 3.6 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA. Users can control or monitor different interfaces with user logic from the FPGA. DE10-Nano User Manual 21 www.terasic.com August 9, 2023 3.6.1 User Push-buttons, Switches and LEDs The board has two push-buttons connected to the FPGA, as shown in Figure 3-16. Schmitt trigger circuit is implemented and act as switch debounce in Figure 3-17 for the push-buttons connected. The two push-buttons named KEY0 and KEY1 coming out of the Schmitt trigger device are connected directly to the Cyclone V SoC FPGA. The push-button generates a low logic level or high logic level when it is pressed or not, respectively. Since the push-buttons are debounced, they can be used as clock or reset inputs in a circuit. Figure 3-16 Connections between the push-buttons and the Cyclone V SoC FPGA Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced Figure 3-17 Switch debouncing There are four slide switches connected to the FPGA, as shown in Figure 3-18. These switches are not debounced and to be used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to the FPGA. When the switch is set to the DOWN position (towards the edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is generated to the FPGA. DE10-Nano User Manual 22 www.terasic.com August 9, 2023 Figure 3-18 Connections between the slide switches and the Cyclone V SoC FPGA There are also eight user-controllable LEDs connected to the FPGA. Each LED is driven directly and individually by the Cyclone V SoC FPGA; driving its associated pin to a high logic level or low level to turn the LED on or off, respectively. Figure 3-19 shows the connections between LEDs and Cyclone V SoC FPGA. Table 3-6, Table 3-7 and Table 3-8 list the pin assignment of user push-buttons, switches, and LEDs. DE10-Nano User Manual 23 www.terasic.com August 9, 2023 Figure 3-19 Connections between the LEDs and the Cyclone V SoC FPGA Table 3-6 Pin Assignment of Slide Switches Signal Name FPGA Pin No. Description I/O Standard SW[0] PIN_Y24 Slide Switch[0] 3.3V SW[1] PIN_W24 Slide Switch[1] 3.3V SW[2] PIN_W21 Slide Switch[2] 3.3V SW[3] PIN_W20 Slide Switch[3] 3.3V Signal Name FPGA Pin No. Description I/O Standard KEY[0] PIN_AH17 Push-button[0] 3.3V KEY[1] PIN_AH16 Push-button[1] 3.3V Signal Name FPGA Pin No. Description I/O Standard LED[0] PIN_W15 LED [0] 3.3V LED[1] PIN_AA24 LED [1] 3.3V LED[2] PIN_V16 LED [2] 3.3V LED[3] PIN_V15 LED [3] 3.3V LED[4] PIN_AF26 LED [4] 3.3V LED[5] PIN_AE26 LED [5] 3.3V Table 3-7 Pin Assignment of Push-buttons Table 3-8 Pin Assignment of LEDs DE10-Nano User Manual 24 www.terasic.com August 9, 2023 3.6.2 2x20 GPIO Expansion Headers The board has two 40-pin expansion headers. Each header has 36 user pins connected directly to the Cyclone V SoC FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins. Figure 3-20 shows the I/O distribution of the GPIO connector. The maximum power consumption allowed for a daughter card connected to one or two GPIO ports is shown in Table 3-9 and Table 3-10 shows all the pin assignments of the GPIO connector. GPIO 0 (JP1) GPIO 1 (JP7) PIN_V12 GPIO_0[0] 1 2 GPIO_0[1] PIN_E8 PIN_Y15 GPIO_1[0] 1 2 GPIO_1[1] PIN_AC24 PIN_W12 GPIO_0[2] 3 4 GPIO_0[3] PIN_D11 PIN_AA15 GPIO_1[2] 3 4 GPIO_1[3] PIN_AD26 PIN_D8 GPIO_0[4] 5 6 GPIO_0[5] PIN_AH13 PIN_AG28 GPIO_1[4] 5 6 GPIO_1[5] PIN_AF28 PIN_AF7 GPIO_0[6] 7 8 GPIO_0[7] PIN_AH14 PIN_AE25 GPIO_1[6] 7 8 GPIO_1[7] PIN_AF27 PIN_AF4 GPIO_0[8] 9 10 GPIO_0[9] PIN_AH3 PIN_AG26 GPIO_1[8] 9 10 GPIO_1[9] PIN_AH27 5V 11 12 GND 5V 11 12 GND PIN_AD5 GPIO_0[10] 13 14 GPIO_0[11] PIN_AG14 PIN_AG25 GPIO_1[10] 13 14 GPIO_1[11] PIN_AH26 PIN_AE23 GPIO_0[12] 15 16 GPIO_0[13] PIN_AE6 PIN_AH24 GPIO_1[12] 15 16 GPIO_1[13] PIN_AF25 PIN_AD23 GPIO_0[14] 17 18 GPIO_0[15] PIN_AE24 PIN_AG23 GPIO_1[14] 17 18 GPIO_1[15] PIN_AF23 PIN_D12 GPIO_0[16] 19 20 GPIO_0[17] PIN_AD20 PIN_AG24 GPIO_1[16] 19 20 GPIO_1[17] PIN_AH22 PIN_C12 GPIO_0[18] 21 22 GPIO_0[19] PIN_AD17 PIN_AH21 GPIO_1[18] 21 22 GPIO_1[19] PIN_AG21 PIN_AC23 GPIO_0[20] 23 24 GPIO_0[21] PIN_AC22 PIN_AH23 GPIO_1[20] 23 24 GPIO_1[21] PIN_AA20 PIN_Y19 GPIO_0[22] 25 26 GPIO_0[23] PIN_AB23 PIN_AF22 GPIO_1[22] 25 26 GPIO_1[23] PIN_AE22 PIN_AA19 GPIO_0[24] 27 28 GPIO_0[25] PIN_W11 PIN_AG20 GPIO_1[24] 27 28 GPIO_1[25] PIN_AF21 3.3V 29 30 GND 3.3V 29 30 GND PIN_AA18 GPIO_0[26] 31 32 GPIO_0[27] PIN_W14 PIN_AG19 GPIO_1[26] 31 32 GPIO_1[27] PIN_AH19 PIN_Y18 GPIO_0[28] 33 34 GPIO_0[29] PIN_Y17 PIN_AG18 GPIO_1[28] 33 34 GPIO_1[29] PIN_AH18 PIN_AB25 GPIO_0[30] 35 36 GPIO_0[31] PIN_AB26 PIN_AF18 GPIO_1[30] 35 36 GPIO_1[31] PIN_AF20 PIN_Y11 GPIO_0[32] 37 38 GPIO_0[33] PIN_AA26 PIN_AG15 GPIO_1[32] 37 38 GPIO_1[33] PIN_AE20 PIN_AA13 GPIO_0[34] 39 40 GPIO_0[35] PIN_AA11 PIN_AE19 GPIO_1[34] 39 40 GPIO_1[35] PIN_AE17 Figure 3-20 GPIO Pin Arrangement DE10-Nano User Manual 25 www.terasic.com August 9, 2023 Table 3-9 Voltage and Max. Current Limit of Expansion Header(s) Supplied Voltage Max. Current Limit 5V 1A (depend on the power adapter specification.) 3.3V 1.5A Table 3-10 Show all Pin Assignment of Expansion Headers Signal Name FPGA Pin No. Description I/O Standard GPIO_0[0] PIN_V12 GPIO Connection 0[0] 3.3V GPIO_0[1] PIN_E8 GPIO Connection 0[1] 3.3V GPIO_0[2] PIN_W12 GPIO Connection 0[2] 3.3V GPIO_0[3] PIN_D11 GPIO Connection 0[3] 3.3V GPIO_0[4] PIN_D8 GPIO Connection 0[4] 3.3V GPIO_0[5] PIN_AH13 GPIO Connection 0[5] 3.3V GPIO_0[6] PIN_AF7 GPIO Connection 0[6] 3.3V GPIO_0[7] PIN_AH14 GPIO Connection 0[7] 3.3V GPIO_0[8] PIN_AF4 GPIO Connection 0[8] 3.3V GPIO_0[9] PIN_AH3 GPIO Connection 0[9] 3.3V GPIO_0[10] PIN_AD5 GPIO Connection 0[10] 3.3V GPIO_0[11] PIN_AG14 GPIO Connection 0[11] 3.3V GPIO_0[12] PIN_AE23 GPIO Connection 0[12] 3.3V GPIO_0[13] PIN_AE6 GPIO Connection 0[13] 3.3V GPIO_0[14] PIN_AD23 GPIO Connection 0[14] 3.3V GPIO_0[15] PIN_AE24 GPIO Connection 0[15] 3.3V GPIO_0[16] PIN_D12 GPIO Connection 0[16] 3.3V GPIO_0[17] PIN_AD20 GPIO Connection 0[17] 3.3V GPIO_0[18] PIN_C12 GPIO Connection 0[18] 3.3V GPIO_0[19] PIN_AD17 GPIO Connection 0[19] 3.3V GPIO_0[20] PIN_AC23 GPIO Connection 0[20] 3.3V GPIO_0[21] PIN_AC22 GPIO Connection 0[21] 3.3V GPIO_0[22] PIN_Y19 GPIO Connection 0[22] 3.3V GPIO_0[23] PIN_AB23 GPIO Connection 0[23] 3.3V GPIO_0[24] PIN_AA19 GPIO Connection 0[24] 3.3V GPIO_0[25] PIN_W11 GPIO Connection 0[25] 3.3V GPIO_0[26] PIN_AA18 GPIO Connection 0[26] 3.3V GPIO_0[27] PIN_W14 GPIO Connection 0[27] 3.3V GPIO_0[28] PIN_Y18 GPIO Connection 0[28] 3.3V GPIO_0[29] PIN_Y17 GPIO Connection 0[29] 3.3V GPIO_0[30] PIN_AB25 GPIO Connection 0[30] 3.3V GPIO_0[31] PIN_AB26 GPIO Connection 0[31] 3.3V DE10-Nano User Manual 26 www.terasic.com August 9, 2023 GPIO_0[32] PIN_Y11 GPIO Connection 0[32] 3.3V GPIO_0[33] PIN_AA26 GPIO Connection 0[33] 3.3V GPIO_0[34] PIN_AA13 GPIO Connection 0[34] 3.3V GPIO_0[35] PIN_AA11 GPIO Connection 0[35] 3.3V GPIO_1[0] PIN_Y15 GPIO Connection 1[0] 3.3V GPIO_1[1] PIN_AC24 GPIO Connection 1[1] 3.3V GPIO_1[2] PIN_AA15 GPIO Connection 1[2] 3.3V GPIO_1[3] PIN_AD26 GPIO Connection 1[3] 3.3V GPIO_1[4] PIN_AG28 GPIO Connection 1[4] 3.3V GPIO_1[5] PIN_AF28 GPIO Connection 1[5] 3.3V GPIO_1[6] PIN_AE25 GPIO Connection 1[6] 3.3V GPIO_1[7] PIN_AF27 GPIO Connection 1[7] 3.3V GPIO_1[8] PIN_AG26 GPIO Connection 1[8] 3.3V GPIO_1[9] PIN_AH27 GPIO Connection 1[9] 3.3V GPIO_1[10] PIN_AG25 GPIO Connection 1[10] 3.3V GPIO_1[11] PIN_AH26 GPIO Connection 1[11] 3.3V GPIO_1[12] PIN_AH24 GPIO Connection 1[12] 3.3V GPIO_1[13] PIN_AF25 GPIO Connection 1[13] 3.3V GPIO_1[14] PIN_AG23 GPIO Connection 1[14] 3.3V GPIO_1[15] PIN_AF23 GPIO Connection 1[15] 3.3V GPIO_1[16] PIN_AG24 GPIO Connection 1[16] 3.3V GPIO_1[17] PIN_AH22 GPIO Connection 1[17] 3.3V GPIO_1[18] PIN_AH21 GPIO Connection 1[18] 3.3V GPIO_1[19] PIN_AG21 GPIO Connection 1[19] 3.3V GPIO_1[20] PIN_AH23 GPIO Connection 1[20] 3.3V GPIO_1[21] PIN_AA20 GPIO Connection 1[21] 3.3V GPIO_1[22] PIN_AF22 GPIO Connection 1[22] 3.3V GPIO_1[23] PIN_AE22 GPIO Connection 1[23] 3.3V GPIO_1[24] PIN_AG20 GPIO Connection 1[24] 3.3V GPIO_1[25] PIN_AF21 GPIO Connection 1[25] 3.3V GPIO_1[26] PIN_AG19 GPIO Connection 1[26] 3.3V GPIO_1[27] PIN_AH19 GPIO Connection 1[27] 3.3V GPIO_1[28] PIN_AG18 GPIO Connection 1[28] 3.3V GPIO_1[29] PIN_AH18 GPIO Connection 1[29] 3.3V GPIO_1[30] PIN_AF18 GPIO Connection 1[30] 3.3V GPIO_1[31] PIN_AF20 GPIO Connection 1[31] 3.3V GPIO_1[32] PIN_AG15 GPIO Connection 1[32] 3.3V GPIO_1[33] PIN_AE20 GPIO Connection 1[33] 3.3V GPIO_1[34] PIN_AE19 GPIO Connection 1[34] 3.3V GPIO_1[35] PIN_AE17 GPIO Connection 1[35] 3.3V DE10-Nano User Manual 27 www.terasic.com August 9, 2023 3.6.3 Arduino Uno R3 Expansion Header The board provides Arduino Uno revision 3 compatibility expansion header which comes with four independent headers. The expansion header has 17 user pins (16pins GPIO and 1pin Reset) connected directly to the Cyclone V SoC FPGA. 6-pins Analog input connects to ADC, and also provides DC +9V (VCC9), DC +5V (VCC5), DC +3.3V (VCC3P3 and IOREF), and three GND pins. Please refer to Figure 3-21 for detailed pin-out information. The blue font represents the Arduino Uno R3 board pin-out definition. Figure 3-21 lists the all the pin-out signal name of the Arduino Uno connector. The blue font represents the Arduino pin-out definition. The 16 GPIO pins are provided to the Arduino Header for digital I/O. Table 3-11 lists the all the pin assignments of the Arduino Uno connector (digital), signal names relative to the Cyclone V SoC FPGA. DE10-Nano User Manual 28 www.terasic.com August 9, 2023 Table 3-11 Pin Assignments for Arduino Uno Expansion Header connector Schematic Specific features FPGA Pin No. Description Signal Name I/O Standard For Arduino Arduino_IO0 PIN_AG13 Arduino IO0 RXD 3.3-V Arduino_IO1 PIN_AF13 Arduino IO1 TXD 3.3-V Arduino_IO2 PIN_AG10 Arduino IO2 3.3-V Arduino_IO3 PIN_AG9 Arduino IO3 3.3-V Arduino_IO4 PIN_U14 Arduino IO4 3.3-V Arduino_IO5 PIN_U13 Arduino IO5 3.3-V Arduino_IO6 PIN_AG8 Arduino IO6 3.3-V Arduino_IO7 PIN_AH8 Arduino IO7 3.3-V Arduino_IO8 PIN_AF17 Arduino IO8 3.3-V Arduino_IO9 PIN_AE15 Arduino IO9 3.3-V Arduino_IO10 PIN_AF15 Arduino IO10 SS 3.3-V Arduino_IO11 PIN_AG16 Arduino IO11 MOSI 3.3-V Arduino_IO12 PIN_AH11 Arduino IO12 MISO 3.3-V Arduino_IO13 PIN_AH12 Arduino IO13 SCK 3.3-V Arduino_IO14 PIN_AH9 Arduino IO14 SDA 3.3-V Arduino_IO15 PIN_AG11 Arduino IO15 SCL 3.3-V Arduino_Reset_n PIN_AH7 Reset signal, low active. 3.3-V Besides 16 pins for digital GPIO, there are also 6 analog inputs on the Arduino Uno R3 Expansion Header (ADC_IN0 ~ ADC_IN5). Consequently, we use ADC LTC2308 from Linear Technology on the board for possible future analog-to-digital applications. We will introduce in the next section. 3.6.4 A/D Conver ter and Analog Input The DE10-Nano has an analog-to-digital converter (LTC2308). The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit ADC with a SPI/MICROWIRE compatible serial interface. This ADC includes an internal reference and a fully differential sample-and-hold circuit to reduce common mode noise. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40MHz. DE10-Nano User Manual 29 www.terasic.com August 9, 2023 It can be configured to accept eight input signals at inputs ADC_IN0 through ADC_IN7. These eight input signals are connected to a 2x5 header, as shown in Figure 3-22. Figure 3-22 Signals of the 2x5 Header These Analog inputs are shared with the Arduino's analog input pin (ADC_IN0 ~ ADC_IN5), Figure 3-23 shows the connections between the FPGA, 2x5 header, Arduino Analog input, and the A/D converter. More information about the A/D converter chip is available in its datasheet. It can be found on manufacturer’s website or in the directory \Datasheet\ADC of DE10-Nano system CD. DE10-Nano User Manual 30 www.terasic.com August 9, 2023 Figure 3-23 Connections between the FPGA, 2x5 header, and the A/D converter Table 3-12 Pin Assignment of ADC Signal Name FPGA Pin No. Description I/O Standard ADC_CONVST PIN_U9 Conversion Start 3.3V ADC_SCK PIN_V10 Serial Data Clock 3.3V ADC_SDI PIN_AC4 Serial Data Input (FPGA to ADC) 3.3V ADC_SDO PIN_AD4 Serial Data Out (ADC to FPGA) 3.3V 3.6.5 HDMI TX Interface The development board provides High Performance HDMI Transmitter via the Analog Devices ADV7513 which incorporates HDMI v1.4 features, including 3D video support, and 165 MHz supports all video formats up to 1080p and UXGA. The ADV7513 is controlled via a serial I2C bus interface, which is connected to pins on the Cyclone V SoC FPGA. A schematic diagram of the audio circuitry is shown in Figure 3-24. Detailed information on using the ADV7513 HDMI TX is available on the manufacturer’s website, or under the Datasheets\HDMI folder on the Kit System CD. DE10-Nano User Manual 31 www.terasic.com August 9, 2023 Table 3-13 lists the HDMI Interface pin assignments and signal names relative to the Cyclone V SoC device. Figure 3-24 Connections between the Cyclone V SoC FPGA and HDMI Transmitter Chip Table 3-13 HDMI Pin Assignments, Schematic Signal Names, and Functions Signal Name FPGA Pin No Description I/O Standard HDMI_TX_D0 PIN_AD12 Video Data bus 3.3-V HDMI_TX_D1 PIN_AE12 Video Data bus 3.3-V HDMI_TX_D2 PIN_W8 Video Data bus 3.3-V HDMI_TX_D3 PIN_Y8 Video Data bus 3.3-V HDMI_TX_D4 PIN_AD11 Video Data bus 3.3-V HDMI_TX_D5 PIN_AD10 Video Data bus 3.3-V HDMI_TX_D6 PIN_AE11 Video Data bus 3.3-V HDMI_TX_D7 PIN_Y5 Video Data bus 3.3-V HDMI_TX_D8 PIN_AF10 Video Data bus 3.3-V HDMI_TX_D9 PIN_Y4 Video Data bus 3.3-V HDMI_TX_D10 PIN_AE9 Video Data bus 3.3-V HDMI_TX_D11 PIN_AB4 Video Data bus 3.3-V HDMI_TX_D12 PIN_AE7 Video Data bus 3.3-V HDMI_TX_D13 PIN_AF6 Video Data bus 3.3-V DE10-Nano User Manual 32 www.terasic.com August 9, 2023 HDMI_TX_D14 PIN_AF8 Video Data bus 3.3-V HDMI_TX_D15 PIN_AF5 Video Data bus 3.3-V HDMI_TX_D16 PIN_AE4 Video Data bus 3.3-V HDMI_TX_D17 PIN_AH2 Video Data bus 3.3-V HDMI_TX_D18 PIN_AH4 Video Data bus 3.3-V HDMI_TX_D19 PIN_AH5 Video Data bus 3.3-V HDMI_TX_D20 PIN_AH6 Video Data bus 3.3-V HDMI_TX_D21 PIN_AG6 Video Data bus 3.3-V HDMI_TX_D22 PIN_AF9 Video Data bus 3.3-V HDMI_TX_D23 PIN_AE8 Video Data bus 3.3-V HDMI_TX_CLK PIN_AG5 Video Clock 3.3-V HDMI_TX_DE PIN_AD19 Data Enable Signal for Digital Video. 3.3-V HDMI_TX_HS PIN_T8 Horizontal Synchronization 3.3-V HDMI_TX_VS PIN_V13 Vertical Synchronization 3.3-V HDMI_TX_INT PIN_AF11 Interrupt Signal 3.3-V HDMI_I2S0 PIN_T13 I2S Channel 0 Audio Data Input 3.3-V HDMI_MCLK PIN_U11 Audio Reference Clock Input 3.3-V HDMI_LRCLK PIN_T11 Audio Left/Right Channel Signal Input 3.3-V HDMI_SCLK PIN_T12 I2S Audio Clock Input 3.3-V I2C_SCL PIN_U10 I2C Clock 3.3-V I2C_SDA PIN_AA4 I2C Data 3.3-V 3.7 Peripherals Connected to Hard Processor System (HPS) This section introduces the interfaces connected to the HPS section of the Cyclone V SoC FPGA. Users can access these interfaces via the HPS processor. 3.7.1 User Push-buttons and LEDs Similar to the FPGA, the HPS also has its set of switches, buttons, LEDs, and other interfaces connected exclusively. Users can control these interfaces to monitor the status of HPS. Table 3-14 gives the pin assignment of all the LEDs, switches, and push-buttons. Table 3-14 Pin Assignment of LEDs, Switches and Push-buttons Signal Nam FPGA Pin No HPS GPIO Register/bit Function HPS_KEY PIN_J18 GPIO54 GPIO1[25] I/O HPS_LED PIN_A20 GPIO53 GPIO1[24] I/O DE10-Nano User Manual 33 www.terasic.com August 9, 2023 3.7.2 Gigabit Ether net The board supports Gigabit Ethernet transfer by an external Micrel KSZ9031RN PHY chip and HPS Ethernet MAC function. The KSZ9031RN chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver also supports RGMII MAC interface. Figure 3-23 shows the connections between the HPS, Gigabit Ethernet PHY, and RJ-45 connector. The pin assignment associated to Gigabit Ethernet interface is listed in Table 3-15. More information about the KSZ9031RN PHY chip and its datasheet, as well as the application notes, which are available on the manufacturer’s website. Figure 3-23 Connections between the HPS and Gigabit Ethernet Table 3-15 Pin Assignment of Gigabit Ethernet PHY Signal Name FPGA Pin No Description I/O Standard HPS_ENET_TX_EN PIN_A12 GMII and MII transmit enable 3.3V HPS_ENET_TX_DATA[0] PIN_A16 MII transmit data[0] 3.3V HPS_ENET_TX_DATA[1] PIN_J14 MII transmit data[1] 3.3V HPS_ENET_TX_DATA[2] PIN_A15 MII transmit data[2] 3.3V HPS_ENET_TX_DATA[3] PIN_D17 MII transmit data[3] 3.3V HPS_ENET_RX_DV PIN_J13 GMII and MII receive data valid 3.3V HPS_ENET_RX_DATA[0] PIN_A14 GMII and MII receive data[0] 3.3V HPS_ENET_RX_DATA[1] PIN_A11 GMII and MII receive data[1] 3.3V HPS_ENET_RX_DATA[2] PIN_C15 GMII and MII receive data[2] 3.3V HPS_ENET_RX_DATA[3] PIN_A9 GMII and MII receive data[3] 3.3V HPS_ENET_RX_CLK PIN_J12 GMII and MII receive clock 3.3V DE10-Nano User Manual 34 www.terasic.com August 9, 2023 HPS_ENET_RESET_N PIN_B4 Hardware Reset Signal 3.3V HPS_ENET_MDIO PIN_E16 Management Data 3.3V HPS_ENET_MDC PIN_A13 Management Data Clock Reference 3.3V HPS_ENET_INT_N PIN_B14 Interrupt Open Drain Output 3.3V HPS_ENET_GTX_CLK PIN_J15 GMII Transmit Clock 3.3V There are two LEDs, green LED (LEDG) and yellow LED (LEDY), which represent the status of Ethernet PHY (KSZ9031RN). The LED control signals are connected to the LEDs on the RJ45 connector. The state and definition of LEDG and LEDY are listed in Table 3-16. For instance, the connection from board to Gigabit Ethernet is established once the LEDG lights on. Table 3-16 State and Definition of LED Mode Pins LED (State) LED (Definition) Link /Activity LEDG LEDY LEDG LEDY H H OFF OFF Link off L H ON OFF 1000 Link / No Activity Toggle H Blinking OFF 1000 Link / Activity (RX, TX) H L OFF ON 100 Link / No Activity H Toggle OFF Blinking 100 Link / Activity (RX, TX) L L ON ON 10 Link/ No Activity Toggle Toggle Blinking Blinking Link / Activity (RX, TX) 3.7.3 UART The board has one UART interface connected for communication with the HPS. This interface doesn’t support HW flow control signals. The physical interface is implemented by UART-USB onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More information about the chip is available on the manufacturer’s website, or in the directory \Datasheets\UART_TO_USB of DE10-Nano system CD. Figure 3-25 shows the connections between the HPS, FT232R chip, and the USB Mini-B connector. Table 3-17 lists the pin assignment of UART interface connected to the HPS. DE10-Nano User Manual 35 www.terasic.com August 9, 2023 Figure 3-25 Connections between the HPS and FT232R Chip Table 3-17 Pin Assignment of UART Interface Signal Name FPGA Pin No. Description I/O Standard HPS_UART_RX PIN_A22 HPS UART Receiver 3.3V HPS_UART_TX PIN_B21 HPS UART Transmitter 3.3V HPS_CONV_USB_N PIN_C6 Reserve 3.3V 3.7.4 DDR3 Memor y The board supports 1GB of DDR3 SDRAM comprising of two x16 bit DDR3 devices on HPS side. The signals are connected to the dedicated Hard Memory Controller for HPS I/O banks and the target speed is 400 MHz. Figure 3-26 shows the connections between the DDR3 and Cyclone V SoC FPGA. Table 3-18 lists the pin assignment of DDR3 and its description with I/O standard. Figure 3-26 Connections between FPGA and DDR3 DE10-Nano User Manual 36 www.terasic.com August 9, 2023 Table 3-18 Pin Assignment of DDR3 Memory Signal Name FPGA Pin No Description I/O Standard HPS_DDR3_A[0] PIN_C28 HPS DDR3 Address[0] SSTL-15 Class I HPS_DDR3_A[1] PIN_B28 HPS DDR3 Address[1] SSTL-15 Class I HPS_DDR3_A[2] PIN_E26 HPS DDR3 Address[2] SSTL-15 Class I HPS_DDR3_A[3] PIN_D26 HPS DDR3 Address[3] SSTL-15 Class I HPS_DDR3_A[4] PIN_J21 HPS DDR3 Address[4] SSTL-15 Class I HPS_DDR3_A[5] PIN_J20 HPS DDR3 Address[5] SSTL-15 Class I HPS_DDR3_A[6] PIN_C26 HPS DDR3 Address[6] SSTL-15 Class I HPS_DDR3_A[7] PIN_B26 HPS DDR3 Address[7] SSTL-15 Class I HPS_DDR3_A[8] PIN_F26 HPS DDR3 Address[8] SSTL-15 Class I HPS_DDR3_A[9] PIN_F25 HPS DDR3 Address[9] SSTL-15 Class I HPS_DDR3_A[10] PIN_A24 HPS DDR3 Address[10] SSTL-15 Class I HPS_DDR3_A[11] PIN_B24 HPS DDR3 Address[11] SSTL-15 Class I HPS_DDR3_A[12] PIN_D24 HPS DDR3 Address[12] SSTL-15 Class I HPS_DDR3_A[13] PIN_C24 HPS DDR3 Address[13] SSTL-15 Class I HPS_DDR3_A[14] PIN_G23 HPS DDR3 Address[14] SSTL-15 Class I HPS_DDR3_BA[0] PIN_A27 HPS DDR3 Bank Address[0] SSTL-15 Class I HPS_DDR3_BA[1] PIN_H25 HPS DDR3 Bank Address[1] SSTL-15 Class I HPS_DDR3_BA[2] PIN_G25 HPS DDR3 Bank Address[2] SSTL-15 Class I HPS_DDR3_CAS_n PIN_A26 DDR3 Column Address Strobe SSTL-15 Class I HPS_DDR3_CKE PIN_L28 HPS DDR3 Clock Enable SSTL-15 Class I HPS_DDR3_CK_n PIN_N20 HPS DDR3 Clock Differential 1.5-V SSTL Class I HPS_DDR3_CK_p PIN_N21 HPS DDR3 Clock p Differential 1.5-V SSTL Class I HPS_DDR3_CS_n PIN_L21 HPS DDR3 Chip Select SSTL-15 Class I HPS_DDR3_DM[0] PIN_G28 HPS DDR3 Data Mask[0] SSTL-15 Class I HPS_DDR3_DM[1] PIN_P28 HPS DDR3 Data Mask[1] SSTL-15 Class I HPS_DDR3_DM[2] PIN_W28 HPS DDR3 Data Mask[2] SSTL-15 Class I HPS_DDR3_DM[3] PIN_AB28 HPS DDR3 Data Mask[3] SSTL-15 Class I HPS_DDR3_DQ[0] PIN_J25 HPS DDR3 Data[0] SSTL-15 Class I HPS_DDR3_DQ[1] PIN_J24 HPS DDR3 Data[1] SSTL-15 Class I HPS_DDR3_DQ[2] PIN_E28 HPS DDR3 Data[2] SSTL-15 Class I HPS_DDR3_DQ[3] PIN_D27 HPS DDR3 Data[3] SSTL-15 Class I HPS_DDR3_DQ[4] PIN_J26 HPS DDR3 Data[4] SSTL-15 Class I HPS_DDR3_DQ[5] PIN_K26 HPS DDR3 Data[5] SSTL-15 Class I HPS_DDR3_DQ[6] PIN_G27 HPS DDR3 Data[6] SSTL-15 Class I HPS_DDR3_DQ[7] PIN_F28 HPS DDR3 Data[7] SSTL-15 Class I HPS_DDR3_DQ[8] PIN_K25 HPS DDR3 Data[8] SSTL-15 Class I HPS_DDR3_DQ[9] PIN_L25 HPS DDR3 Data[9] SSTL-15 Class I HPS_DDR3_DQ[10] PIN_J27 HPS DDR3 Data[10] SSTL-15 Class I DE10-Nano User Manual 37 www.terasic.com August 9, 2023 HPS_DDR3_DQ[11] PIN_J28 HPS DDR3 Data[11] SSTL-15 Class I HPS_DDR3_DQ[12] PIN_M27 HPS DDR3 Data[12] SSTL-15 Class I HPS_DDR3_DQ[13] PIN_M26 HPS DDR3 Data[13] SSTL-15 Class I HPS_DDR3_DQ[14] PIN_M28 HPS DDR3 Data[14] SSTL-15 Class I HPS_DDR3_DQ[15] PIN_N28 HPS DDR3 Data[15] SSTL-15 Class I HPS_DDR3_DQ[16] PIN_N24 HPS DDR3 Data[16] SSTL-