Datasheet · 2022

ST STUSB4500 Standalone USB PD Sink Controller — Datasheet (DS12499)

The proposed 20 V sink (UP-4).

Author: STMicroelectronics
Year: 2022
Type: Datasheet
Credit: STMicroelectronics (st.com)

usb pd
sink controller

STUSB4500 Datasheet Standalone USB PD sink controller with short-to-VBUS protections Features • • • • • Product status link STUSB4500 • Integrated VBUS voltage monitoring • Internal and/or external VBUS discharge paths • • Short-to-VBUS protections on CC pins (22 V) High voltage capability on VBUS pins (28 V) • Dual power supply (VSYS and/or VDD): • • • • Device summary Order code Description STUSB4500QTR STUSB4500BJR Standalone USB PD sink controller (auto-run mode) QFN-24 EP (4x4) Package WLCSP-25 (2.6x2.6x0.5) Marking 4500 Auto-run Type-C™ and USB PD sink controller Dead battery mode support Up to 3 sink PDO configurable profiles (up to 20 V; 5 A) Dual high power charging path support Integrated VBUS switch gate drivers (PMOS) • – VSYS = [3.0 V; 5.5 V] – VDD = [4.1 V; 22 V] Debug accessory mode support Temperature range: -40 °C up to 105 °C ESD: 3 kV HBM - 1.5 kV CDM Certified: – USB Type-C™ rev 1.2 – USB PD rev 2.0 (TID #1000133) Interoperable with USB PD rev 3.0 Applications • • • • • • Printers, camcorders, cameras IoT, drones, accessories and battery powered devices LED lighting and industrial Toys, gaming, POS, scanner Healthcare and handheld devices Any Type-C sink device up to 100 W (20 V; 5 A) Description The STUSB4500 is a USB power delivery controller that addresses sink up to 100 W (20 V; 5 A). It implements a proprietary algorithm to allow the negotiation of a power delivery contract with a source without MCU support (auto-run mode). PDO profiles are configured in an integrated non-volatile memory. The device supports dead battery mode and is suited for sink devices powered from dead battery state and requiring high power charging profile to be fully operational. Thanks to its 20 V technology, it implements high voltage features to protect the CC pins against short-circuits to VBUS up to 22 V and to support high voltage on the VBUS pins directly connected to the VBUS power path up to 28 V. DS12499 - Rev 8 - November 2022 For further information contact your local STMicroelectronics sales office. www.st.com STUSB4500 Functional description 1 Functional description The STUSB4500 is a USB Type-C™ and power delivery controller IC for sink applications. It is able to negotiate a power delivery contract with a source without MCU support (auto-run mode). It relies on proprietary algorithms and configurable PDO (power data objects) thanks to an integrated non-volatile memory. It supports dead battery mode to allow a system to be powered from an external source directly. Combined with its capability to negotiate directly a power contract, the STUSB4500 is the ideal controller device for autonomous systems requiring high power charging profile to be fully operational. The STUSB4500 major role is to: 1. Detect the connection between two USB Type-C ports (attach detection) 2. Establish a valid source-to-sink connection 3. Determine the attached device mode: source or debug accessory 4. Resolve cable orientation and twist connections to establish USB data routing (MUX control) 5. Negotiate a USB power delivery (PD) contract with a PD capable source device 6. Configure the incoming VBUS power path and the charging paths accordingly 7. Monitor the VBUS power path and manage the VBUS voltage transitions 8. Handle the high voltage protections The STUSB4500 also provides: 1.1 • • • Dead battery mode PDO (power data object) customization through NVM Internal and/or external VBUS discharge paths • • • Dual high power charging path support Debug accessory mode detection Customization of the device configuration through NVM to support specific applications Block overview Figure 1. Functional block diagram VSYS VDD Internal supply RESET POR VBUS_VS_DISCH voltage monitoring VBUS status VBUS_EN_SNK A_B_SIDE DISCH ADDR[1..0] SCL SDA I²C slave Port C controller CC line access Protocol Layer Physical Layer CC1DB CC1 CC2 CC2DB Port status ALERT ATTACH POWER_OK2 POWER_OK3 GPIO Control Device Policy Manager Policy Engine GND DS12499 - Rev 8 page 2/42 STUSB4500 Inputs/outputs 2 Inputs/outputs 2.1 Pinout VDD VREG_2V7 VSYS VREG_1V2 POWER_OK2 ALERT Figure 2. QFN-24 pin connections (top view) 24 23 22 21 20 19 CC1DB 1 18 VBUS_VS_DISCH CC1 2 17 A_B_SIDE NC 3 16 VBUS_EN_SNK EP 5 14 POWER_OK3 RESET 6 13 ADDR1 SCL 7 8 9 10 11 12 ADDR0 CC2DB ATTACH GPIO GND 15 DISCH 4 SDA CC2 Figure 3. WLCSP-25 pin connections (top view) DS12499 - Rev 8 1 2 3 4 5 A VBUS_VS _DISCH POWER _OK2 VREG _1V2 VREG _2V7 VDD B VSYS ALERT - CC1DB CC1 C VBUS_ EN_SNK A_B_ SIDE - CC2DB CC2 D GPIO ADDR1 ADDR0 RESET SCL E POWER _OK3 ATTACH GND DISCH SDA page 3/42 STUSB4500 Pinout Table 1. Pin function list QFN CSP Name Type 1 B4 CC1DB HV AIO Dead battery enable on CC1 pin To CC1 pin if used or ground 2 B5 CC1 HV AIO Type-C configuration channel 1 To Type-C receptacle A5 3 B3, C3 NC - - Floating 4 C5 CC2 HV AIO Type-C configuration channel 2 To Type-C receptacle B5 5 C4 CC2DB HV AIO Dead battery enable on CC2 pin To CC2 pin if used or ground 6 D4 RESET DI Reset input, active high From system I2C clock input To I²C master, ext. pull-up 7 D5 SCL DI 8 E5 SDA DI/OD Description Typical connection I2C data input/output, active low open drain To I²C master, ext. pull-up Internal discharge path or external discharge path enable, active low open drain From power system (internal path) or to the discharge path switch (external path), ext. pullup 9 E4 DISCH HV AI/OD 10 E3 GND GND Ground Ground 11 E2 ATTACH OD Attachment detection, active low open drain To MCU if any, ext. pull-up I²C device address setting Static, to ground or ext. pull-up for address selection, 12 D3 ADDR0 DI to ground if no connection to MCU I²C device address setting Static, to ground or ext. pull-up for address selection, 13 D2 ADDR1 DI 14 E1 POWER_OK3 OD Power contract flag, active low open drain To power system, ext. pull-up 15 D1 GPIO OD General purpose output, active low open drain To system, ext. pull-up 16 C1 VBUS_EN_SNK HV OD VBUS sink power path enable, active low open drain To power switch or to power system, ext. pull-up 17 C2 A_B_SIDE OD Cable orientation, active low open drain USB super speed MUX select, ext. pull-up 18 A1 VBUS_VS_DISCH HV AI VBUS voltage monitoring and discharge path From VBUS, receptacle side 19 B2 ALERT OD I2C interrupt, active low open drain To I²C master, ext. pull-up 20 A2 POWER_OK2 HV OD Power contract flag, active low open drain To power switch or to power system, ext. pull-up 21 A3 VREG_1V2 PWR 1.2 V internal regulator output 1 µF typ. decoupling capacitor 22 B1 VSYS PWR Power supply from system From power system, connect to ground if not used 23 A4 VREG_2V7 PWR 2.7 V internal regulator output 1 µF typ. decoupling capacitor 24 A5 VDD HV PWR Power supply from USB power line From VBUS, receptacle side EP - EP GND Exposed pad is connected to ground To ground DS12499 - Rev 8 to ground if no connection to MCU page 4/42 STUSB4500 Pin description Table 2. Pin function descriptions 2.2 Pin description 2.2.1 CC1 / CC2 Type Description D Digital A Analog O Output pad I Input pad IO Bidirectional pad OD Open drain output PD Pull-down PU Pull-up HV High voltage PWR Power GND Ground CC1 and CC2 are the configuration channel pins used for connection and attachment detection, plug orientation determination, USB power delivery communication, and system configuration management across USB Type-C cable. CC1 and CC2 are HiZ during reset. 2.2.2 CC1DB / CC2DB CC1DB and CC2DB are used for dead battery mode. This mode is enabled by connecting CC1DB and CC2DB respectively to CC1 and CC2. Thanks to this connection, the pull-down terminations on the CC pins are present by default even if the device is not supplied (see Section 3.5 Dead battery mode). Warning: CC1DB and CC2DB must be connected to ground when dead battery mode is not supported. 2.2.3 RESET Active high reset. DS12499 - Rev 8 page 5/42 STUSB4500 Pin description 2.2.4 I²C interface pins Table 3. I2C interface pin list Name SCL I²C clock, need external pull-up SDA I²C data, need external pull-up ALERT I²C interrupt, need external pull-up ADDR0, ADDR1 • I²C device address bits (see Section 4 I²C Interface) Warning: – – 2.2.5 Description ADDR0 and ADDR1 pins must be connected to ground when there is no connection to an MCU SCL and SDA are pulled down when none of VDD or VSYS is present DISCH This input/output pin can be used to implement a discharge path for highly capacitive VBUS line on power system side. When used as input, the discharge is internal and a serial resistor must connected to the pin to limit the discharge current through the pin. Maximum discharge current is 500 mA. The pin can be also used as an open drain output to control an external VBUS discharge path when higher discharge current is required by the application, for instance. The pin is activated at the same time as the internal discharge path on VBUS_VS_DISCH pin. The discharge is activated automatically during cable disconnection, transition to a lower PDO voltage, hard reset and error recovery state. The discharge time is programmable by NVM (see Section 5 Start-up configuration). 2.2.6 GND Ground. 2.2.7 ATTACH This pin is asserted when a valid source-to-sink connection is established. It is also asserted when a connection to a debug accessory device is detected. DS12499 - Rev 8 page 6/42 STUSB4500 Pin description 2.2.8 POWER_OK2 / POWER_OK3 These pins report by default the status of the USB power delivery contract negotiation with the source. Different configurations are proposed as stated in the table below to meet specific application requirements. The configuration of the POWER_OK pins can be changed by NVM programming (see Section 5 Start-up configuration). Depending on the programmed configuration, they can be used in combination with VBUS_EN_SNK pin to enable different power path scenarios. POWER_OK2 pin is a high voltage open drain output that allows a PMOS transistor to be directly driven to enable a power path. POWER_OK3 is a low voltage open drain output. Table 4. POWER_OK pin configuration Configuration ID /NVM parameter Pin name Value Description PWR_OK_CFG[1:0] Configuration 1: all PDOs on single VBUS power path Hi-Z No source attached 0 Source attached POWER_OK2 Hi-Z No functionality POWER_OK3 Hi-Z No functionality VBUS_EN_SNK(1) 00b Configuration 2: all PDOs on single VBUS power path + dedicated high power charging paths VBUS_EN_SNK (1) 10b (default) POWER_OK2 POWER_OK3 Hi-Z No source attached 0 Source attached Hi-Z No PD explicit contract 0 PD explicit contract with PDO2 Hi-Z No PD explicit contract 0 PD explicit contract with PDO3 Configuration 3: all PDOs on single VBUS power path + detection of USB Type-C current capability from source VBUS_EN_SNK(1) Hi-Z No source attached 0 Source attached Hi-Z No source attached or source supplies default USB Type-C current at 5 V when source attached 0 Source supplies 3.0 A USB Type-C current at 5 V when source attached Hi-Z No source attached or source supplies default USB Type-C current at 5V when source attached 0 Source supplies 1.5 A USB Type-C current at 5 V when source attached POWER_OK2 11b POWER_OK3 01b Not applicable 1. The VBUS_EN_SNK pin values correspond to the default behavior In case of configuration 2 (default): • • DS12499 - Rev 8 When a PDO negotiation succeeds, the POWER_OK pin related to the negotiated PDO is enabled (active low) when PS_READY message is received from the source When a new PDO is negotiated upon source request, the active POWER_OK pin is disabled (Hi-Z) when the STUSB4500 sends an RDO (request data object) message to the source with the new negotiated PDO page 7/42 STUSB4500 Pin description • 2.2.9 At detachment the POWER_OK pins remain enabled (if already asserted), whereas VBUS_EN_SNK is disabled (Hi-Z) to deactivate the VBUS power path from the USB Type-C receptacle. The POWER_OK pins state is reinitialized (Hi-Z) after new attachment or after a reset GPIO This pin is an active low open drain output that can be configured by NVM as per table below (see Section 5 Start-up configuration). Table 5. GPIO pin configuration NVM parameter GPIO_CFG[1:0] 00b 01b (default) 10b 11b 2.2.10 Pin name Pin function SW_CTRL_GPIO ERROR_RECOVERY DEBUG SINK_POWER Value Description Software controlled GPIO. Hi-Z When bit #0 value is 0b (at start-up) The output state is defined by the value of I2C register bit #0 at address 2Dh 0 When bit #0 value is 1b Hardware fault detection Hi-Z No hardware fault detected (see Section 3.7 Hardware fault management) 0 Hardware fault detected Debug accessory detection Hi-Z No debug accessory detected (see Section 3.8 Debug accessory mode detection) 0 Indicates USB Type-C current capability advertised by the source Debug accessory detected Hi-Z Source supplies default or 1.5 A USB Type-C current at 5 V 0 Source supplies 3.0 A USB Type-C current at 5 V VBUS_EN_SNK This pin allows the incoming VBUS power from the USB Type-C receptacle to be enabled when a source is connected according to different operating conditions stated in the table below. The default behavior of the pin can be changed by NVM programming (see Section 5 Start-up configuration). Table 6. VBUS_EN_SNK pin configuration NVM parameter POWER_ONLY Pin function Value Description Enables VBUS power path when source attached whatever VBUS voltage (5 V or any PDO voltage) Hi-Z No source attached 0 Source attached Enables VBUS power path only when source attached and VBUS voltage negotiated to PDO2 or PDO3 voltage Hi-Z No source attached or no PD explicit contract with PDO2 or PDO3 0 Source attached and PD explicit contract with PDO2 or PDO3 Comment _ABOVE_5V 0b (default) 1b Valid for all POWER_OK pin configurations 1, 2 and 3 When POWER_ONLY_ABOVE_5V bit is set to logic level high, the VBUS_EN_SNK pin is asserted only when a PDO2 or PDO3 explicit contract is established with the source (see Section 3.3 Auto-run mode). This feature is suited for sink devices requiring high power charging profile above 5 V to be fully operational (see Section 6.1.2 Powering a system under high charging profile only). VBUS_EN_SNK pin is a high voltage open drain output that allows a PMOS transistor to be directly driven to enable the VBUS power path. DS12499 - Rev 8 page 8/42 STUSB4500 Pin description 2.2.11 A_B_SIDE This output pin provides the cable orientation. It is used to establish USB SuperSpeed signal routing. This signal is not required in case of USB 2.0 support. Table 7. USB data MUX select Value 2.2.12 Description HiZ CC1 pin is attached to CC line 0 CC2 pin is attached to CC line VBUS_VS_DISCH This input pin is used to sense VBUS presence, monitor VBUS voltage, and discharge VBUS from the USB Type-C receptacle side. A serial resistor connected to the pin must be used to limit the discharge current through the pin. Maximum discharge current is 50 mA. The discharge is activated automatically during cable disconnection, transition to a lower PDO voltage, hard reset and error recovery state. The discharge time is programmable by NVM (see Section 5 Start-up configuration). 2.2.13 VREG_1V2 This pin is used only for external decoupling of the 1.2 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min., 10 µF max.) 2.2.14 VSYS This is the low power supply from the system, if there is any. It can be connected directly to a single cell Lithium battery or to the system power supply delivering 3.3 V or 5 V. It is recommended to connect the pin to ground when it is not used. 2.2.15 VREG_2V7 This pin is used only for external decoupling of the 2.7 V internal regulator. The recommended decoupling capacitor is: 1 µF typ. (0.5 µF min., 10 µF max.) 2.2.16 VDD This is the power supply from the USB power line for applications powered by VBUS. DS12499 - Rev 8 page 9/42 STUSB4500 Description of the features 3 Description of the features 3.1 CC interface The STUSB4500 controls the connection to the configuration channel (CC) pins, CC1 and CC2, through two main blocks: the CC line interface block and the CC control logic block. The CC line interface block is used to: • • • Set pull-down termination mode on the CC pins Monitor the CC pin voltage values related to the attachment detection thresholds Protect the CC pins against overvoltage The CC control logic block is used to: • • • • • • • Execute the Type-C FSM related to the sink power role with debug accessory support Determine the electrical state for each CC pin related to the detected thresholds Evaluate the conditions relative to the CC pin states and the VBUS voltage value to transition from one state to another in the Type-C FSM Advertise a valid source-to-sink connection Determine the attached device mode: source or debug accessory Determine cable orientation to allow external routing of the USB data Manage USB Type-C power capability on VBUS: USB default, medium or high current mode • Handle hardware faults 3.2 Power delivery blocks 3.2.1 Physical layer The physical layer defines the signaling technology for USB power delivery. It is the physical link between CC pins and protocol layer. In Tx mode, it receives packet data from the protocol layer, calculates and appends a CRC, encodes the payload (i.e. packet data and CRC) and transmits the packet (i.e. preamble, SOP, payload, CRC and EOP) using biphase mark coding (i.e. BMC) over CC pins. In Rx mode, it recovers the clock and the data, detects the SOP, decodes the received data including the CRC, detects the EOP and validates the CRC. 3.2.2 Protocol layer The protocol layer has the responsibility to manage the messages from/to the physical layer. It automatically manages the protocol receive timeouts, the message counter, the retry counter and the GoodCRC messages. It communicates with the internal policy engine. 3.2.3 Policy engine The policy engine implements the power negotiation with the connected device according to its sink role. It implements all state machines controlling the protocol layer that forms and schedules the messages. The policy engine uses the protocol layer to send/receive messages. The policy engine interprets the device policy manager’s input in order to implement policy for port and directs the protocol layer to send appropriate messages. 3.2.4 Device policy manager The device policy manager deals with the power capability request and change management. It operates according to the decision algorithm described in the following section. 3.3 Auto-run mode The STUSB4500 implements a hardcoded decision algorithm that allows the device to negotiate in autonomous way a power delivery transaction with a source according to the PDO (power data objects) profiles programmed in the NVM. DS12499 - Rev 8 page 10/42 STUSB4500 Auto-run mode It makes the STUSB4500 a plug-and-play, autonomous and effective solution to develop USB PD sink systems operating in standalone. 3.3.1 Sink PDO configuration The STUSB4500 features up to 3 sink PDOs (SNK_PDO). The value of each PDO is defined in the NVM (see Section 5 Start-up configuration). Table 8. Sink PDO description Sink PDO # Comment Priority Description PDO1 Mandatory Low PDO2 Optional Medium Defines the intermediate power configuration PDO3 Optional High Defines the highest power configuration (if any) Defines the default power configuration PDO voltage configuration: • • PDO1 voltage is fixed to 5 V by hardware PDO2 and PDO3 voltages are programmable by NVM from 5 V to 20 V by steps of 50 mV as defined in the USB PD standard specification (see Section 5 Start-up configuration) PDO current configuration: • • • 3.3.2 The current of each PDO is programmable by NVM through look-up table see (Section 5 Start-up configuration) 15 predefined values are set in the look-up table from 0.5 A to 5 A 1 custom value can be programmed in the look-up table from 10 mA to 5 A by steps of 10 mA as defined in the USB PD standard specification. This value is common to all PDOs if used Decision algorithm description The decision algorithm compares each SNK_PDOi with the SRC_PDOj capabilities received from the source. The comparison starts from the SNK_PDO with the highest priority to the SNK_PDO with the lowest priority. The voltage is compared first, the current afterwards. A match occurs when both conditions are met: 1. V(SNK_PDOi) = V(SRC_PDOj) 2. I(SNK_PDOi) ≤ I(SRC_PDOj) The comparison loop stops at the first match. The remaining SRC_PDOj are not compared and the SNK_PDOi with lower priority are discarded. In case of match: • • An RDO (request data object) message is formed with matched voltage V(SNK_PDOi) as operating voltage, related I(SNK_PDOi) current as operating current and I(SRC_PDOj) current from matched SRC_PDOj as maximum current The RDO message is sent to the source for evaluation and acceptance by the source prior the transition to matched PDO voltage by the source and the reception of PS_READY message by the sink In case of no match: • • 3.3.3 At the end of the comparison loop, if no match happens, the USB PD negotiation ends with an explicit USB PD contract at 5 V An RDO message is sent to the source with capability mismatch enabled, operating current set to current value from source PDO at 5 V, and maximum current set to I(SNK_PDO1) Requesting maximum source current Thanks to dedicated NVM bit “REQ_SRC_CURRENT”, the operating current informed in the RDO message, when a matching PDO is found, can be set either to the current value from the matched sink PDO (default) or to the current value from the matched source PDO. Requesting current value from the matched source PDO is useful for a sink that can benefit from higher power capability than originally required in order to increase its performance. This implies for the source to allocate a power reserve as stated in the USB PD standard specification. DS12499 - Rev 8 page 11/42 STUSB4500 VBUS power path control In case the sink is not able to consume more power than requested, this option must not be used. It avoids allocating by the source a power reserve that is not used, thus limiting the overall power system optimization. 3.3.4 Decision algorithm application with examples The following capabilities from the source have been considered to study the negotiation result for different sink PDO configuration cases with the STUSB4500: • • • SRC_PDO1 = 5 V, 3 A SRC_PDO2 = 9 V, 3 A SRC_PDO3 = 15 V, 2 A Table 9. Decision algorithm results for different cases Case 1 2 3 4 5 3.4 3.4.1 Configured sink capabilities Result REQ_SRC_CURRENT = 0b Result REQ_SRC_CURRENT = 1b SNK_PDO2 = 9 V, 2.5 A Match: RDO = 9 V, 2.5 A, 3 A Match: RDO = 9 V, 3 A, 3 A SNK_PDO1 = 5 V, 3 A Not compared Not compared SNK_PDO3 = 9.1 V, 2.9 A No match No match SNK_PDO2 = 8.9 V, 2.9 A No match No match SNK_PDO1 = 5 V, 3 A Match: RDO = 5 V, 3 A, 3 A Match: RDO = 5 V, 3 A, 3 A SNK_PDO3 = 15 V, 2.1 A No match No match SNK_PDO2 = 9 V, 2.5 A Match: RDO = 9 V, 2.5 A, 3 A Match: RDO = 9 V, 3 A, 3 A SNK_PDO1 = 5 V, 3 A Not compared Not compared SNK_PDO3 = 15.1 V, 2 A No match No match SNK_PDO2 = 15 V, 1 A Match: RDO = 15 V, 1 A, 2 A Match: RDO = 15 V, 2 A, 2 A SNK_PDO1 = 5 V, 3 A Not compared Not compared SNK_PDO2 = 15 V, 3 A No match No match SNK_PDO3 = 9 V, 1 A Match: RDO = 9 V, 1 A, 3 A Match: RDO = 9 V, 3 A, 3 A SNK_PDO1 = 5 V, 1 A Not compared Not compared VBUS power path control VBUS monitoring The VBUS monitoring block supervises from the VBUS_VS_DISCH input pin the VBUS voltage on the USB Type-C receptacle side. It is used to check that VBUS is within a valid voltage range to establish a valid source-to-sink connection and to enable safely the VBUS power path through the VBUS_EN_SNK pin. It allows detection of unexpected VBUS voltage conditions such as undervoltage or overvoltage relative to the valid VBUS voltage range. When such conditions occur, the STUSB4500 reacts as follows: • • At attachment, it prevents the source-to-sink connection to be established and the VBUS power path to be asserted After attachment, it goes into unattached state and it disables the VBUS power path The valid VBUS voltage range is defined by a high limit VMONUSBH and a low limit that can take as value either VTHUSB or VMONUSBL depending on system operation and VBUS voltage. VTHUSB low limit is fixed by hardware at 3.3 V. It corresponds to the undervoltage condition to detect a VBUS disconnection when VBUS voltage is at 5 V (USB Type-C or PDO1). The nominal value of VMONUSBL is VBUS-5%. The low limit value can be shifted by fraction of VBUS from -1% to -15%. The nominal value of VMONUSBH is VBUS+5%. The high limit value can be shifted independently by fraction of VBUS from +1% to +15%. It means the threshold limits can vary from VBUS-5% to VBUS-20% for the low limit and from VBUS+5% to VBUS+20% for the high limit. DS12499 - Rev 8 page 12/42 STUSB4500 VBUS power path control At attachment, the valid VBUS voltage range is defined by VMONUSBH and VMONUSBL limits to establish a valid source-to-sink connection. After attachment and during system operations, the valid VBUS voltage range is automatically adjusted to VMONUSBH and VTHUSB limits when VBUS voltage is at 5 V (USB Type-C or PDO1), or to VMONUSBH and VMONUSBL limits when VBUS operates under PDO2 or PDO3 voltage. The VBUS voltage value is automatically adjusted to 5 V (USB Type-C) at attachment and to the negotiated PDO voltage after PDO transition. During each PDO transition, the VBUS monitoring is disabled for tSrcReady (285 ms max.) as per USB PD standard specifications. Then the new limits applicable to the negotiated PDO voltage are monitored. The threshold limits are preset by default in the NVM with different shift coefficients (see Section 7.3 Electrical and timing characteristics). The threshold limits can be changed independently through NVM programming (see Section 5 Start-up configuration). 3.4.2 VBUS discharge The monitoring block also handles the VBUS discharge paths connected to the VBUS_VS_DISCH pin for the USB Type-C receptacle side and to the DISCH pin for the power system side. The discharge paths are activated at the same time when disconnection is detected, during transition to a lower PDO voltage, when a hard reset is performed or when the device goes into the error recovery state (see Section 3.7 Hardware fault management). At detachment, during error recovery state or hard reset, the discharge is activated for TDISUSB0V time. During transition to a lower PDO voltage, the discharge is activated for TDISUSBPDO time. The discharge time durations are also preset by default in the NVM (see Section 7.3 Electrical and timing characteristics). The discharge time durations can be changed through NVM programming (see Section 5 Startup configuration). The VBUS discharge feature is enabled by default in the NVM and can be disabled through NVM programming (see Section 5 Start-up configuration). 3.4.3 VBUS power path assertion The STUSB4500 can control the assertion of the VBUS power path from the USB Type-C receptacle, directly or indirectly, through the VBUS_EN_SNK pin. The table below summarizes the operating conditions that determine the electrical value of the VBUS_EN_SNK pin during system operation. Table 10. VBUS_EN_SNK pin behavior depending on the operating conditions Operating conditions Value NVM parameter POWER_ONLY Connection stage VBUS voltage from source VBUS monitoring conditions on VBUS_VS_DISCH pin Type-C state _ABOVE_5V At attachment 5V (USB Type-C) 0b 5V 0 During operation 0b or 1b 0b or 1b During operation Before attachment Hi-Z 1b DS12499 - Rev 8 At attachment VBUS < VMONUSBH1 and VBUS > VMONUSBL1 VBUS < VMONUSBH1 Attached.SNK (USB Type-C and or or SNK_PDO1) VBUS > VTHUSB Debug Accessory.SNK V(SNK_PDO2) or V(SNK_PDO3) N.A. 5V (USB Type-C) VBUS < VMONUSBH2/3 and VBUS > VMONUSBL2/3 N.A. Unattached.SNK VBUS < VMONUSBH1 Attached.SNK and or VBUS > VMONUSBL1 Debug Accessory.SNK page 13/42 STUSB4500 Dead battery mode Operating conditions Value NVM parameter POWER_ONLY Connection stage VBUS voltage from source VBUS monitoring conditions on VBUS_VS_DISCH pin Type-C state _ABOVE_5V 0b Hi-Z At attachment 0b 5V (USB Type-C) and VBUS > VMONUSBH1 (USB Type-C or or SNK_PDO1) VBUS < VTHUSB V(SNK_PDO2) or V(SNK_PDO3) AttachWait.SNK VBUS < VMONUSBL1 5V During operation 0b or 1b VBUS > VMONUSBH1 VBUS > VMONUSBH2/3 Attached.SNK or Debug Accessory.SNK or VBUS < VMONUSBL2/3 Type-C state column refers to the Type-C FSM states as defined in the USB Type-C standard specification. 3.5 Dead battery mode Dead battery mode allows systems powered by a battery to be supplied by the VBUS when the battery is discharged and to start the battery charging process. This mode is also used in systems that are powered through the VBUS only. Dead battery mode operates only if the CC1DB and CC2DB pins are connected respectively to the CC1 and CC2 pins. Thanks to these connections, the STUSB4500 presents a pull-down termination on its CC pins and advertises itself as a sink even if the device is not supplied. When a source system connects to a USB Type-C port with the STUSB4500 configured in dead battery mode, it can detect the pull-down termination, establish the source-to-sink connection, and provide the VBUS. The STUSB4500 is then supplied thanks to the VDD pin connected to VBUS on the USB Type-C receptacle side. The STUSB4500 can finalize the connection on its side and enable the power path on VBUS thanks to the VBUS_EN_SNK pin to allow the system to be powered. DS12499 - Rev 8 page 14/42 STUSB4500 High voltage protections 3.6 High voltage protections The STUSB4500 can be safely used in systems or connected to systems that handle high voltage on the VBUS power path. The device integrates an internal circuitry on the CC pins that tolerates high voltage and ensures protection up to 22 V in case of unexpected short-circuits with the VBUS as per figure below. Figure 4. Short-to-VBUS 3.7 Hardware fault management The STUSB4500 handles during system operation some pre-identified hardware fault conditions. When such conditions happen, the circuit goes into a transient error recovery state named ErrorRecovery in the Type-C FSM as defined in the USB Type-C standard specifications. The error recovery state is equivalent to force a detach event. When entering in this state, the device de-asserts the VBUS power path by disabling the VBUS_EN_SNK, POWER_OK2 and POWER_OK3 pins, and it removes the terminations from the CC pins during several tens of milliseconds. Then, it transitions to the unattached state. The STUSB4500 goes into error recovery state when at least one condition listed below is met: • If an overtemperature is detected (junction temperature above maximum TJ) • If an overvoltage is detected on the CC pins (voltage on CC pins above VOVP) • If after a hard reset the power delivery communication with the source is broken The detection of a hardware fault is advertised through the GPIO pin when configured in ERROR_RECOVERY mode. See Section 7 Electrical characteristics for threshold values. DS12499 - Rev 8 page 15/42 STUSB4500 Debug accessory mode detection 3.8 Debug accessory mode detection The STUSB4500 detects a connection to a debug and test system (DTS) as defined in the USB Type-C standard specification. The debug accessory detection is advertised through the GPIO pin when configured in DEBUG mode. A debug accessory device is detected when both the CC1 and CC2 pins are pulled up by an Rp resistor from the connected device. The voltage levels on the CC1 and CC2 pins give the orientation and current capability as described in the table below. The GPIO pin configured in DEBUG mode is asserted to advertise the DTS detection and the A_B_SIDE pin indicates the orientation of the connection. Table 11. Orientation and current capability detection in sink power role A_B_SIDE pin CC1 pin (CC2 pin) (CC1 pin) Charging current configuration 1 Rp 3 A Rp 1.5 A Default Hi-Z (0) 2 Rp 1.5 A Rp default 1.5 A Hi-Z (0) 3 Rp 3 A Rp default 3.0 A Hi-Z (0) Rp Rp def/1.5 A/3 A def/1.5 A/3 A Default Hi-Z (Hi-Z) 4 DS12499 - Rev 8 CC2 pin # CC1/CC2 (CC2/CC1) page 16/42 STUSB4500 I²C Interface 4 I²C Interface 4.1 Read and write operations The I²C interface is used to configure, control and read the operation status of the device. It is compatible with the Philips I²C Bus® (version 2.1). The I²C is a slave serial interface based on two signals: • • SCL - serial clock line: input clock used to shift data SDA - serial data line: input/output bidirectional data transfers A filter rejects the potential spikes on the bus data line to preserve data integrity. The bidirectional data line supports transfers up to 400 kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first. The first bit must be high (START) followed by the 7-bit device address and the read/write control bit. Four 7-bit device address are available for the STUSB4500 thanks to the external programming of DevADDR0 and DevADDR1 bits through ADDR0 and ADDR1 pins setting i.e. 0x28 or 0x29 or 0x2A or 0x2B. It allows four STUSB4500 devices to be connected on the same I2C bus. Table 12. Device address format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DevADDR6 DevADDR5 DevADDR4 DevADDR3 DevADDR2 DevADDR1 DevADDR0 R/W 0 1 0 1 0 ADDR1 ADDR0 0/1 Table 13. Register address format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RegADDR7 RegADDR6 RegADDR5 RegADDR4 RegADDR3 RegADDR2 RegADDR1 RegADDR0 Table 14. Register data format Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Figure 5. Read operation Master Start Slave Device addr W A 7 bits Reg address A Restart Device addr 8 bits R A Reg data 7 bits A 8 bits Start bit = SDA falling when SCL = 1 Stop bit = SDA rising when SCL = 1 Restart bit = start after a start Acknowledge = SDA forced low during a SCL clock Reg data A Reg data 8 bits 8 bits Address n+1 Address n+2 Ᾱ Stop Figure 6. Write operation Start Device addr W A Reg address 7 bits Start bit = SDA falling when SCL = 1 Stop bit = SDA rising when SCL = 1 Restart bit = start after a start DS12499 - Rev 8 8 bits A Reg data 8 bits A Reg data A Reg data 8 bits 8 bits Address n+1 Address n+2 A Stop page 17/42 STUSB4500 Timing specifications 4.2 Timing specifications The device uses a standard slave I²C channel at speed up to 400 kHz. Table 15. I²C timing parameters - VDD = 5 V Symbol Parameter Min. Typ. Max. Unit kHz Fscl SCL clock frequency 0 400 thd,sta Hold time (repeated) START condition 0.6 - tlow LOW period of the SCL clock 1.3 - thigh HIGH period of the SCL clock 0.6 - tsu,dat Setup time for repeated START condition 0.6 - thd,dat Data hold time 0.04 tsu,dat Data setup time μs 0.9 - 100 - tr Rise time of both SDA and SCL signals 20 + 0.1 Cb 300 tf Fall time of both SDA and SCL signals 20 + 0.1 Cb 300 tsu,sto Set-up time for STOP condition 0.6 - tbuf Bus free time between a STOP and START condition 1.3 - Cb Capacitive load for each bus line - 400 ns μs pF Figure 7. I²C timing diagram tf Vih SDA Vil thd,sta tr tsu,dat thigh SCL tlow DS12499 - Rev 8 thd,dat tsu,sto page 18/42 STUSB4500 Start-up configuration 5 Start-up configuration 5.1 User-defined parameters The STUSB4500 has a set of user-defined parameters that can be customized by NVM re-programming through the I2C interface. This feature allows the customer to change the preset configuration of the USB Type-C and PD interface and to define a new configuration to meet specific application requirements addressing various use cases, or specific implementations. The NVM re-programming overrides the initial default setting to define a new default setting that is used at power-up or after a reset. The default setting is copied at power-up, or after a reset, from the embedded NVM into I2C registers. The values copied in the I2C registers are used by the STUSB4500 during the system operation. The NVM re-programming is possible with a customer password. The I2C registers must be re-initialized after each NVM re-programming to make effective the new parameters setting either through power-off and power-up sequence, or through reset. 5.2 Default start-up configuration The table below lists the user-defined parameters and indicates the default start-up configuration of the STUSB4500. Table 16. STUSB4500 user-defined parameters and default settings Parameter name Parameter description Reset value Value Description (default) SNK_PDO_NUMB[1:0] Number of sink PDOs 00b 1 PDO 11b 01b 1 PDO (3) 10b 2 PDOs 11b 3 PDOs Flexible voltage value V_SNK_PDO2 Voltage value for SNK_PDO2 0.05*300 (15 V) 0.05*100 to 5 V ≤ 0.05*V_SNK_PDO2_FLEX[9:0] ≤ 20 V by steps of 50 mV 0.05*400 Default V_SNK_PDO2_FLEX[9:0] = 0100101100 Flexible voltage value V_SNK_PDO3 Voltage value for SNK_PDO3 0.05*400 (20 V) 0.05*100 to 0.05*400 Default V_SNK_PDO3_FLEX[9:0] = 0110010000 0000b I_SNK_PDO1 Current value for SNK_PDO1 0101b (1.5 A) 0001b to 1111b 0000b I_SNK_PDO2 Current value for SNK_PDO2 0101b (1.5 A) 0001b to DS12499 - Rev 8 5 V ≤ 0.05*V_SNK_PDO3_FLEX[9:0] ≤ 20 V by steps of 50 mV I_SNK_PDO_LUT[3:0] flexible current value from look-up table (see Table 17. Look-up table for sink PDO current configuration) I_SNK_PDO_LUT[3:0] pre-defined current values from look-up table (see Table 17. Look-up table for sink PDO current configuration ) I_SNK_PDO_LUT[3:0] flexible current value from look-up table (see Table 17. Look-up table for sink PDO current configuration) I_SNK_PDO_LUT[3:0] pre-defined current values from look-up table (see Table 17. Look-up table for sink PDO current configuration) page 19/42 STUSB4500 Default start-up configuration Parameter name Parameter description Reset value Value Description (default) I_SNK_PDO2 Current value for SNK_PDO2 0101b (1.5 A) 1111b 0000b I_SNK_PDO3 Current value for SNK_PDO3 0011b (1.0 A) 0001b to 1111b I_SNK_PDO_LUT[3:0] flexible current value from look-up table (see Table 17. Look-up table for sink PDO current configuration) I_SNK_PDO_LUT[3:0] pre-defined current values from look-up table (see Table 17. Look-up table for sink PDO current configuration) Flexible current value I_SNK_PDO_FLEX SHIFT_VBUS_HL1 SHIFT_VBUS_LL1 SHIFT_VBUS_HL2 SHIFT_VBUS_LL2 SHIFT_VBUS_HL3 SHIFT_VBUS_LL3 VBUS_DISCH_TIME_TO_0V Flexible current value common to all PDOs DS12499 - Rev 8 (2.0 A) Coefficient to shift up nominal VBUS high voltage limit applicable to 5 V and SNK_PDO1 voltage 1010b Coefficient to shift down nominal VBUS low voltage limit applicable to 5 V and SNK_PDO1 voltage 1111b (10%) (15%) Coefficient to shift up nominal VBUS high voltage limit applicable to SNK_PDO2 voltage 0101b Coefficient to shift down nominal VBUS applicable to SNK_PDO2 voltage 1111b (5%) (15%) Coefficient to shift up nominal VBUS high voltage limit applicable to SNK_PDO3 voltage 0101b Coefficient to shift down nominal VBUS low voltage limit applicable to SNK_PDO3 voltage 1111b Coefficient used to compute VBUS discharge time to 0V Coefficient used to compute VBUS VBUS_DISCH_TIME_TO_PDO discharge time when