Datasheet · 2008

Solomon Systech SSD1306 128×64 OLED Segment/Common Driver with Controller — Datasheet (Rev 1.1)

Small OLED controller; its 400 kHz I2C limit constrains a shared sensor bus.

Author: Solomon Systech
Year: 2008
Type: Datasheet
Credit: Solomon Systech. Copy via Adafruit (cdn-shop.adafruit.com)

oled
display controller
i2c

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1306 Advance Information 128 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1306 Rev 1.1 P 1/59 Apr 2008 Copyright © 2008 Solomon Systech Limited CONTENTS 1 GENERAL DESCRIPTION .......................................................................................................6 2 FEATURES...................................................................................................................................6 3 ORDERING INFORMATION ...................................................................................................6 4 BLOCK DIAGRAM ....................................................................................................................7 5 DIE PAD FLOOR PLAN ............................................................................................................ 8 6 PIN ARRANGEMENT..............................................................................................................11 6.1 SSD1306TR1 PIN ASSIGNMENT .......................................................................................................................... 11 7 PIN DESCRIPTION ..................................................................................................................13 8 FUNCTIONAL BLOCK DESCRIPTIONS.............................................................................15 8.1 MCU INTERFACE SELECTION.............................................................................................................................. 15 8.1.1 MCU Parallel 6800-series Interface.......................................................................................................... 15 8.1.2 MCU Parallel 8080-series Interface.......................................................................................................... 16 8.1.3 MCU Serial Interface (4-wire SPI) ............................................................................................................ 17 8.1.4 MCU Serial Interface (3-wire SPI) ............................................................................................................ 18 8.1.5 MCU I2C Interface..................................................................................................................................... 19 8.2 COMMAND DECODER ......................................................................................................................................... 22 8.3 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR ..................................................................................... 22 8.4 FR SYNCHRONIZATION ....................................................................................................................................... 23 8.5 RESET CIRCUIT ................................................................................................................................................... 23 8.6 SEGMENT DRIVERS / COMMON DRIVERS ............................................................................................................ 24 8.7 GRAPHIC DISPLAY DATA RAM (GDDRAM)..................................................................................................... 25 8.8 SEG/COM DRIVING BLOCK ............................................................................................................................... 26 8.9 POWER ON AND OFF SEQUENCE ........................................................................................................................ 27 9 COMMAND TABLE ................................................................................................................. 28 9.1 10 DATA READ / WRITE .......................................................................................................................................... 33 COMMAND DESCRIPTIONS ............................................................................................. 34 10.1 FUNDAMENTAL COMMAND ................................................................................................................................ 34 10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) ................................................. 34 10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) ................................................ 34 10.1.3 Set Memory Addressing Mode (20h).......................................................................................................... 34 10.1.4 Set Column Address (21h) ......................................................................................................................... 35 10.1.5 Set Page Address (22h).............................................................................................................................. 36 10.1.6 Set Display Start Line (40h~7Fh) .............................................................................................................. 36 10.1.7 Set Contrast Control for BANK0 (81h)...................................................................................................... 36 10.1.8 Set Segment Re-map (A0h/A1h) ................................................................................................................. 36 10.1.9 Entire Display ON (A4h/A5h) .................................................................................................................. 37 10.1.10 Set Normal/Inverse Display (A6h/A7h).................................................................................................. 37 10.1.11 Set Multiplex Ratio (A8h)....................................................................................................................... 37 10.1.12 Set Display ON/OFF (AEh/AFh) ........................................................................................................... 37 10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h)............................................................. 37 10.1.14 Set COM Output Scan Direction (C0h/C8h).......................................................................................... 37 10.1.15 Set Display Offset (D3h) ........................................................................................................................ 37 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) ............................................................... 40 10.1.17 Set Pre-charge Period (D9h) ................................................................................................................. 40 10.1.18 Set COM Pins Hardware Configuration (DAh)..................................................................................... 40 10.1.19 Set VCOMH Deselect Level (DBh) ........................................................................................................... 43 Solomon Systech Apr 2008 P 2/59 Rev 1.1 SSD1306 10.1.20 NOP (E3h) ............................................................................................................................................. 43 10.1.21 Status register Read ............................................................................................................................... 43 10.2 GRAPHIC ACCELERATION COMMAND ................................................................................................................. 44 10.2.1 Horizontal Scroll Setup (26h/27h) ............................................................................................................. 44 10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah)..................................................................... 45 10.2.3 Deactivate Scroll (2Eh).............................................................................................................................. 46 10.2.4 Activate Scroll (2Fh).................................................................................................................................. 46 10.2.5 Set Vertical Scroll Area(A3h) .................................................................................................................... 46 11 MAXIMUM RATINGS..........................................................................................................47 12 DC CHARACTERISTICS.....................................................................................................48 13 AC CHARACTERISTICS.....................................................................................................49 14 APPLICATION EXAMPLE..................................................................................................55 15 PACKAGE INFORMATION................................................................................................56 15.1 15.2 SSD1306 SSD1306TR1 DETAIL DIMENSION ..................................................................................................................... 56 SSD1306Z DIE TRAY INFORMATION .................................................................................................................. 58 Rev 1.1 P 3/59 Apr 2008 Solomon Systech TABLES TABLE 5-1 : SSD1306Z BUMP DIE PAD COORDINATES ...................................................................................................... 10 TABLE 6-1 : SSD1306TR1 PIN ASSIGNMENT TABLE .......................................................................................................... 12 TABLE 7-1 : MCU BUS INTERFACE PIN SELECTION ............................................................................................................ 14 TABLE 8-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ...................................................... 15 TABLE 8-2 : CONTROL PINS OF 6800 INTERFACE................................................................................................................. 15 TABLE 8-3 : CONTROL PINS OF 8080 INTERFACE................................................................................................................. 17 TABLE 8-4 : CONTROL PINS OF 4-WIRE SERIAL INTERFACE ................................................................................................. 17 TABLE 8-5 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE ................................................................................................. 18 TABLE 9-1: COMMAND TABLE ........................................................................................................................................... 28 TABLE 9-2 : READ COMMAND TABLE ................................................................................................................................. 33 TABLE 9-3 : ADDRESS INCREMENT TABLE (AUTOMATIC) ................................................................................................... 33 TABLE 10-1 : EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH NO REMAP .......................................... 38 TABLE 10-2 :EXAMPLE OF SET DISPLAY OFFSET AND DISPLAY START LINE WITH REMAP ................................................ 39 TABLE 10-3 : COM PINS HARDWARE CONFIGURATION ..................................................................................................... 40 TABLE 11-1 : MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS)................................................................................ 47 TABLE 12-1 : DC CHARACTERISTICS .................................................................................................................................. 48 TABLE 13-1 : AC CHARACTERISTICS .................................................................................................................................. 49 TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 50 TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS......................................................... 51 TABLE 13-4 : 4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 52 TABLE 13-5 : 3-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS ................................................................................ 53 TABLE 13-6 :I2C INTERFACE TIMING CHARACTERISTICS .................................................................................................... 54 Solomon Systech Apr 2008 P 4/59 Rev 1.1 SSD1306 FIGURES FIGURE 4-1 SSD1306 BLOCK DIAGRAM .............................................................................................................................. 7 FIGURE 5-1 : SSD1306Z DIE DRAWING ............................................................................................................................... 8 FIGURE 5-2 : SSD1306Z ALIGNMENT MARK DIMENSIONS .................................................................................................... 9 FIGURE 6-1 : SSD1306TR1 PIN ASSIGNMENT ................................................................................................................. 11 FIGURE 7-1 PIN DESCRIPTION ............................................................................................................................................. 13 FIGURE 8-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ....................................................................... 16 FIGURE 8-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE......................................................... 16 FIGURE 8-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE .......................................................... 16 FIGURE 8-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ......................................................... 17 FIGURE 8-5 : WRITE PROCEDURE IN 4-WIRE SERIAL INTERFACE MODE ............................................................................... 18 FIGURE 8-6 : WRITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE ............................................................................... 18 FIGURE 8-7 : I2C-BUS DATA FORMAT .................................................................................................................................. 20 FIGURE 8-8 : DEFINITION OF THE START AND STOP CONDITION ......................................................................................... 21 FIGURE 8-9 : DEFINITION OF THE ACKNOWLEDGEMENT CONDITION ................................................................................... 21 FIGURE 8-10 : DEFINITION OF THE DATA TRANSFER CONDITION ......................................................................................... 21 FIGURE 8-11 : OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR .............................................................................. 22 FIGURE 8-12 : SEGMENT OUTPUT WAVEFORM IN THREE PHASES ....................................................................................... 24 FIGURE 8-13 : GDDRAM PAGES STRUCTURE OF SSD1306................................................................................................ 25 FIGURE 8-14 : ENLARGEMENT OF GDDRAM (NO ROW RE-MAPPING AND COLUMN-REMAPPING)...................................... 25 FIGURE 8-15 : IREF CURRENT SETTING BY RESISTOR VALUE ............................................................................................. 26 FIGURE 8-16 : THE POWER ON SEQUENCE.......................................................................................................................... 27 FIGURE 8-17 : THE POWER OFF SEQUENCE ........................................................................................................................ 27 FIGURE 10-1 : ADDRESS POINTER MOVEMENT OF PAGE ADDRESSING MODE ..................................................................... 34 FIGURE 10-2 : EXAMPLE OF GDDRAM ACCESS POINTER SETTING IN PAGE ADDRESSING MODE (NO ROW AND COLUMNREMAPPING) ............................................................................................................................................................... 34 FIGURE 10-3 : ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESSING MODE ......................................................... 35 FIGURE 10-4 : ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESSING MODE .............................................................. 35 FIGURE 10-5 : EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT .............................................................. 36 FIGURE 10-6 :TRANSITION BETWEEN DIFFERENT MODES .................................................................................................... 37 FIGURE 10-7 : HORIZONTAL SCROLL EXAMPLE: SCROLL RIGHT BY 1 COLUMN ................................................................. 44 FIGURE 10-8 : HORIZONTAL SCROLL EXAMPLE: SCROLL LEFT BY 1 COLUMN ................................................................... 44 FIGURE 10-9 : HORIZONTAL SCROLLING SETUP EXAMPLE................................................................................................... 44 FIGURE 10-10 : CONTINUOUS VERTICAL AND HORIZONTAL SCROLLING SETUP EXAMPLE .................................................. 45 FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS ...................................................................... 50 FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS................................................................................ 51 FIGURE 13-3 : 4-WIRE SERIAL INTERFACE CHARACTERISTICS ............................................................................................. 52 FIGURE 13-4 : 3-WIRE SERIAL INTERFACE CHARACTERISTICS ............................................................................................. 53 FIGURE 13-5 : I2C INTERFACE TIMING CHARACTERISTICS .................................................................................................. 54 FIGURE 14-1 : APPLICATION EXAMPLE OF SSD1306Z ....................................................................................................... 55 FIGURE 15-1 SSD1306TR1 DETAIL DIMENSION ................................................................................................................ 56 FIGURE 15-2 : SSD1306Z DIE TRAY INFORMATION ............................................................................................................ 58 SSD1306 Rev 1.1 P 5/59 Apr 2008 Solomon Systech 1 GENERAL DESCRIPTION SSD1306 is a single-chip CMOS OLED/PLED driver with controller for organic / polymer light emitting diode dot-matrix graphic display system. It consists of 128 segments and 64commons. This IC is designed for Common Cathode type OLED panel. The SSD1306 embeds with contrast control, display RAM and oscillator, which reduces the number of external components and power consumption. It has 256-step brightness control. Data/Commands are sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface, I2C interface or Serial Peripheral Interface. It is suitable for many compact portable applications, such as mobile phone sub-display, MP3 player and calculator, etc. 2 FEATURES • • • • • • • • • • • • 3 Resolution: 128 x 64 dot matrix panel Power supply o VDD = 1.65V to 3.3V for IC logic o VCC = 7V to 15V for Panel driving For matrix display o OLED driving output voltage, 15V maximum o Segment maximum source current: 100uA o Common maximum sink current: 15mA o 256 step contrast brightness current control Embedded 128 x 64 bit SRAM display buffer Pin selectable MCU Interfaces: o 8-bit 6800/8080-series parallel interface o 3 /4 wire Serial Peripheral Interface o I2C Interface Screen saving continuous scrolling function in both horizontal and vertical direction RAM write synchronization signal Programmable Frame Rate and Multiplexing Ratio Row Re-mapping and Column Re-mapping On-Chip Oscillator Chip layout for COG & COF Wide range of operating temperature: -40°C to 85°C ORDERING INFORMATION Table 3-1: Ordering Information Ordering Part Number SEG COM SSD1306Z 128 64 SSD1306TR1 104 48 Solomon Systech Package Form Reference Remark o Min SEG pad pitch : 47um o Min COM pad pitch : 40um 8 COG o Die thickness: 300 +/- 25um o 35mm film, 4 sprocket hole, Folding TAB o 8-bit 80 / 8-bit 68 / SPI / I2C interface 11, 56 o SEG, COM lead pitch 0.1mm x 0.997 TAB =0.0997mm o Die thickness: 457 +/- 25um Apr 2008 P 6/59 Rev 1.1 SSD1306 4 BLOCK DIAGRAM SSD1306 Rev 1.1 P 7/59 Apr 2008 Common Driver Segment Driver Current Control Voltage Control SEG0 SEG1 | | SEG126 SEG127 COM1 COM3 | | COM61 COM63 VCOMH IREF CL CLS FR Oscillator Command Decoder VDD VCC VSS VLSS COM62 COM60 | | COM2 COM0 Common Driver D7 D6 D5 D4 D3 D2 D1 D0 Display Controller MCU Interface RES# CS# D/C# E (RD#) R/W#(WR#) BS2 BS1 BS0 Graphic Display Data RAM (GDDRAM) Figure 4-1 SSD1306 Block Diagram Solomon Systech 5 DIE PAD FLOOR PLAN Figure 5-1 : SSD1306Z Die Drawing Pad 1 Die size 6.76mm x 0.86mm Die thickness Min I/O pad pitch 300 +/- 25um 60um Min SEG pad pitch 47um Min COM pad pitch 40um Bump height Nominal 15um Bump size SSD1306Z Pad 1, 106, 124, 256 80um x 50um Pad 2-18, 89-105, 107-123, 257-273 25ium x 80um Pad 19-88 40um x 89um Pad 125-255 31um x 59um Pad 274-281 (TR pads) 30um x 50um Alignment mark + shape (-2973, 0) 75um x 75um + shape (2973, 0) 75um x 75um Circle (2466.665, 7.575) R37.5um, inner 18um SSL Logo (-2862.35, 144.82) - Position Size (For details dimension please see p.9 ) Note (1) Diagram showing the Gold bumps face up. (2) Coordinates are referenced to center of the chip. (3) Coordinate units and size of all alignment marks are in um. (4) All alignment keys do not contain gold Y X SSD1306 Pad 1,2,3,…->281 Gold Bumps face up Solomon Systech Apr 2008 P 8/59 Rev 1.1 SSD1306 Figure 5-2 : SSD1306Z alignment mark dimensions T shape + shape Circle *All units are in um SSD1306 Rev 1.1 P 9/59 Apr 2008 Solomon Systech Table 5-1 : SSD1306Z Bump Die Pad Coordinates Pad no. Pad Name X-pos 1 NC -3315 2 VSS -3084.77 3 COM49 -3044.77 4 COM50 -3004.77 5 COM51 -2964.77 6 COM52 -2924.77 7 COM53 -2884.77 8 COM54 -2844.77 9 COM55 -2804.77 COM56 -2764.77 10 11 COM57 -2724.77 12 COM58 -2684.77 13 COM59 -2644.77 COM60 -2604.77 14 15 COM61 -2564.77 16 COM62 -2524.77 17 COM63 -2484.77 18 VCOMH -2444.77 -2334.965 19 NC C2P -2278.265 20 21 C2P -2218.265 22 C2N -2136.715 23 C2N -2055.465 C1P -1995.465 24 25 C1P -1904.115 26 C1N -1844.115 27 C1N -1762.865 28 VBAT -1679.31 29 VBAT -1619.31 VBREF -1537.51 30 31 BGGND -1477.51 -1416.01 32 VCC -1356.01 33 VCC VCOMH -1266.955 34 35 VCOMH -1206.955 36 VLSS -1125.155 37 VLSS -1043.355 38 VLSS -983.355 39 VSS -920 VSS -856 40 41 VSS -796 42 VDD -732.645 43 VDD -672.645 BS0 -595.655 44 45 VSS -531.955 46 BS1 -467.655 47 VDD -403.155 48 VDD -342.555 49 BS2 -279.705 VSS -215.705 50 51 FR -151.955 -89.815 52 CL 53 VSS -25.665 CS# 38.635 54 55 RES# 109.835 56 D/C# 182.425 57 VSS 246.125 58 R/W# 310.425 59 E 373.125 VDD 457.175 60 61 VDD 517.175 62 D0 609.275 63 D1 692.475 D2 765.675 64 65 D3 828.875 66 VSS 890.325 67 D4 951.275 68 D5 1013.315 69 D6 1075.355 D7 1137.395 70 71 VSS 1220.735 72 VSS 1280.735 73 CLS 1362.585 VDD 1425.285 74 75 VDD 1485.885 76 VDD 1553.185 77 VDD 1613.185 78 IREF 1684.585 79 IREF 1744.585 VCOMH 1815.585 80 Solomon Systech Y-pos -377.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 Pad no. Pad Name 81 VCOMH 82 VCC 83 VCC 84 VLSS 85 VLSS 86 VLSS 87 NC 88 NC 89 VSS 90 COM31 91 COM30 92 COM29 93 COM28 94 COM27 95 COM26 96 COM25 97 COM24 98 COM23 99 COM22 100 COM21 101 COM20 102 COM19 103 COM18 104 COM17 105 VSS 106 NC 107 COM16 108 COM15 109 COM14 110 COM13 111 COM12 112 COM11 113 COM10 114 COM9 115 COM8 116 COM7 117 COM6 118 COM5 119 COM4 120 COM3 121 COM2 122 COM1 123 COM0 124 NC 125 NC 126 SEG0 127 SEG1 128 SEG2 129 SEG3 130 SEG4 131 SEG5 132 SEG6 133 SEG7 134 SEG8 135 SEG9 136 SEG10 137 SEG11 138 SEG12 139 SEG13 140 SEG14 141 SEG15 142 SEG16 143 SEG17 144 SEG18 145 SEG19 146 SEG20 147 SEG21 148 SEG22 149 SEG23 150 SEG24 151 SEG25 152 SEG26 153 SEG27 154 SEG28 155 SEG29 156 SEG30 157 SEG31 158 SEG32 159 SEG33 160 SEG34 X-pos 1875.585 1967.185 2027.185 2109.185 2169.185 2254.185 2314.185 2374.185 2444.77 2484.77 2524.77 2564.77 2604.77 2644.77 2684.77 2724.77 2764.77 2804.77 2844.77 2884.77 2924.77 2964.77 3004.77 3044.77 3084.77 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3315 3055.5 3009.5 2962.5 2915.5 2868.5 2821.5 2774.5 2727.5 2680.5 2633.5 2586.5 2539.5 2492.5 2445.5 2398.5 2351.5 2304.5 2257.5 2210.5 2163.5 2116.5 2069.5 2022.5 1975.5 1928.5 1881.5 1834.5 1787.5 1740.5 1693.5 1646.5 1599.5 1552.5 1505.5 1458.5 1411.5 Y-pos -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -352.83 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -362.5 -377.5 -325 -285 -245 -205 -165 -125 -85 -45 -5 35 75 115 155 195 235 275 315 367.5 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 Pad no. Pad Name X-pos Y-pos 161 SEG35 1364.5 356 162 SEG36 1317.5 356 163 SEG37 1270.5 356 164 SEG38 1223.5 356 165 SEG39 1176.5 356 166 SEG40 1129.5 356 167 SEG41 1082.5 356 168 SEG42 1035.5 356 169 SEG43 988.5 356 170 SEG44 941.5 356 171 SEG45 894.5 356 172 SEG46 847.5 356 173 SEG47 800.5 356 174 SEG48 753.5 356 175 SEG49 706.5 356 659.5 356 176 SEG50 177 SEG51 612.5 356 178 SEG52 565.5 356 179 SEG53 518.5 356 180 SEG54 471.5 356 181 SEG55 424.5 356 182 SEG56 377.5 356 183 SEG57 330.5 356 184 SEG58 283.5 356 185 SEG59 236.5 356 186 SEG60 189.5 356 187 SEG61 142.5 356 188 SEG62 95.5 356 189 SEG63 48.5 356 190 SEG64 1.5 356 191 SEG65 -45.5 356 192 SEG66 -92.5 356 193 SEG67 -139.5 356 194 SEG68 -186.5 356 195 SEG69 -233.5 356 196 SEG70 -280.5 356 197 SEG71 -327.5 356 198 SEG72 -374.5 356 199 SEG73 -421.5 356 200 SEG74 -468.5 356 201 SEG75 -515.5 356 202 SEG76 -562.5 356 203 SEG77 -609.5 356 204 SEG78 -656.5 356 205 SEG79 -703.5 356 -750.5 356 206 SEG80 207 SEG81 -797.5 356 208 SEG82 -844.5 356 209 SEG83 -891.5 356 210 NC -940 356 211 SEG84 -988.5 356 212 SEG85 -1035.5 356 213 SEG86 -1082.5 356 214 SEG87 -1129.5 356 215 SEG88 -1176.5 356 216 SEG89 -1223.5 356 217 SEG90 -1270.5 356 218 SEG91 -1317.5 356 219 SEG92 -1364.5 356 220 SEG93 -1411.5 356 221 SEG94 -1458.5 356 222 SEG95 -1505.5 356 223 SEG96 -1552.5 356 224 SEG97 -1599.5 356 225 SEG98 -1646.5 356 226 SEG99 -1693.5 356 227 SEG100 -1740.5 356 228 SEG101 -1787.5 356 229 SEG102 -1834.5 356 230 SEG103 -1881.5 356 231 SEG104 -1928.5 356 232 SEG105 -1975.5 356 233 SEG106 -2022.5 356 234 SEG107 -2069.5 356 235 SEG108 -2116.5 356 236 SEG109 -2163.5 356 237 SEG110 -2210.5 356 238 SEG111 -2257.5 356 239 SEG112 -2304.5 356 240 SEG113 -2351.5 356 Apr 2008 P 10/59 Pad no. Pad Name 241 SEG114 242 SEG115 243 SEG116 244 SEG117 245 SEG118 246 SEG119 247 SEG120 248 SEG121 249 SEG122 250 SEG123 251 SEG124 252 SEG125 253 SEG126 254 SEG127 255 NC 256 NC 257 COM32 258 COM33 259 COM34 260 COM35 261 COM36 262 COM37 263 COM38 264 COM39 265 COM40 266 COM41 267 COM42 268 COM43 269 COM44 270 COM45 271 COM46 272 COM47 273 COM48 X-pos -2398.5 -2445.5 -2492.5 -2539.5 -2586.5 -2633.5 -2680.5 -2727.5 -2774.5 -2821.5 -2868.5 -2915.5 -2962.5 -3009.5 -3056.5 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 -3315 Y-pos 356 356 356 356 356 356 356 356 356 356 356 356 356 356 356 367.5 315 275 235 195 155 115 75 35 -5 -45 -85 -125 -165 -205 -245 -285 -325 Pad no. Pad Name X-pos Pin# Pin name X-dir 274 TR0 2757.05 275 TR1 2697.05 276 TR2 2637.05 277 TR3 2577.05 278 VSS 2517.05 2457.05 279 TR4 280 TR5 2397.05 281 TR6 2337.05 Y-pos Y-dir 114.8 114.8 114.8 114.8 114.8 114.8 114.8 114.8 Rev 1.1 SSD1306 6 PIN ARRANGEMENT 6.1 SSD1306TR1 pin assignment Figure 6-1 : SSD1306TR1 Pin Assignment Note: (1) COM sequence (Split) is under command setting: DAh, 12h SSD1306 Rev 1.1 P 11/59 Apr 2008 Solomon Systech Table 6-1 : SSD1306TR1 Pin Assignment Table Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Solomon Systech Pin Name NC VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E/RD# R/W# D/C# RES# CS# NC BS2 BS1 VDD NC NC NC NC NC NC NC NC VSS NC NC NC COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC NC NC NC NC SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 Pin no. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 Pin no. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 Pin Name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 NC NC NC NC NC NC NC NC NC NC COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 NC NC Apr 2008 P 12/59 Rev 1.1 SSD1306 7 PIN DESCRIPTION Key: I = Input O =Output I/O = Bi-directional (input/output) P = Power pin NC = Not Connected Pull LOW= connect to Ground Pull HIGH= connect to VDD Figure 7-1 Pin Description Pin Name Type Description VDD P Power supply pin for core logic operation. VCC P Power supply for panel driving voltage. This is also the most positive power voltage supply pin. VSS P This is a ground pin. VLSS P This is an analog ground pin. It should be connected to VSS externally. VCOMH O The pin for COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. VBAT P Reserved pin. It should be connected to VDD. BGGND P Reserved pin. It should be connected to ground. C1P/C1N C2P/C2N VBREF I Reserved pin. It should be kept NC. P Reserved pin. It should be kept NC. BS[2:0] I MCU bus interface selection pins. Please refer to Table 7-1 for the details of setting. IREF I This is segment output current reference pin. A resistor should be connected between this pin and VSS to maintain the IREF current at 12.5 uA. Please refer to Figure 8-15 for the details of resistor value. FR O This pin outputs RAM write synchronization signal. Proper timing between MCU data writing and frame display timing can be achieved to prevent tearing effect. It should be kept NC if it is not used. Please refer to Section 8.4 for details usage. CL I This is external clock input pin. When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and should be connected to VSS. When internal clock is disabled (i.e. LOW in CLS pin), this pin is the external clock source input pin. CLS I This is internal clock enable pin. When it is pulled HIGH (i.e. connect to VDD), internal clock is enabled. When it is pulled LOW, the internal clock is disabled; an external clock source must be connected to the CL pin for normal operation. RES# This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation. I CS# SSD1306 This pin is the chip select input. (active LOW). I Rev 1.1 P 13/59 Apr 2008 Solomon Systech Pin Name Type Description D/C# I This is Data/Command control pin. When it is pulled HIGH (i.e. connect to VDD), the data at D[7:0] is treated as data. When it is pulled LOW, the data at D[7:0] will be transferred to the command register. In I2C mode, this pin acts as SA0 for slave address selection. When 3-wire serial interface is selected, this pin must be connected to VSS. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams: Figure 13-1 to Figure 13-5. E (RD#) I When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled HIGH (i.e. connect to VDD) and the chip is selected. When connecting to an 8080-series microprocessor, this pin receives the Read (RD#) signal. Read operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. R/W#(WR#) I This is read / write control input pin connecting to the MCU interface. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled HIGH (i.e. connect to VDD) and write mode when LOW. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled LOW and the chip is selected. When serial or I2C interface is selected, this pin must be connected to VSS. D[7:0] IO These are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be the serial data input: SDIN and D2 should be kept NC. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in application and D0 is the serial clock input, SCL. TR0-TR6 - Testing reserved pins. It should be kept NC. SEG0 ~ SEG127 O These pins provide Segment switch signals to OLED panel. These pins are VSS state when display is OFF. COM0 ~ COM63 O These pins provide Common switch signals to OLED panel. They are in high impedance state when display is OFF. NC - This is dummy pin. Do not group or short NC pins together. Table 7-1 : MCU Bus Interface Pin Selection 2 SSD1306 Pin Name BS0 BS1 BS2 I C Interface 6800-parallel interface (8 bit) 0 0 1 0 0 1 8080-parallel interface (8 bit) 0 1 1 4-wire Serial interface 3-wire Serial interface 0 0 0 1 0 0 Note (1) 0 is connected to VSS (2) 1 is connected to VDD Solomon Systech Apr 2008 P 14/59 Rev 1.1 SSD1306 8 FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface selection SSD1306 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface mode is summarized in Table 8-1. Different MCU mode can be set by hardware selection on BS[2:0] pins (please refer to Table 7-1 for BS[2:0] setting). Table 8-1 : MCU interface assignment under different bus interface mode Pin Name Data/Command Interface Bus Interface D7 D6 D5 D4 D3 8-bit 8080 D[7:0] 8-bit 6800 D[7:0] 3-wire SPI Tie LOW 4-wire SPI Tie LOW I2C Tie LOW 8.1.1 Control Signal D2 D1 D0 E R/W# RD# WR# E R/W# NC SDIN SCLK Tie LOW NC SDIN SCLK Tie LOW SDAOUT SDAIN SCL Tie LOW CS# CS# CS# CS# CS# D/C# RES# D/C# RES# D/C# RES# Tie LOW RES# D/C# RES# SA0 RES# MCU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#. A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal. Table 8-2 : Control pins of 6800 interface Function E R/W# CS# D/C# Write command ↓ L L L Read status ↓ H L L Write data ↓ L L H Read data ↓ H L H Note (1) ↓ stands for falling edge of signal H stands for HIGH in signal L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 8-1. SSD1306 Rev 1.1 P 15/59 Apr 2008 Solomon Systech Figure 8-1 : Data read back procedure - insertion of dummy read R/W# E N Databus Write column address 8.1.2 Dummy read n n+1 n+2 Read 1st data Read 2nd data Read 3rd data MCU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#. A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write. A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW. A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW. Figure 8-2 : Example of Write procedure in 8080 parallel interface mode CS# WR# D[7:0] D/C# RD# high low Figure 8-3 : Example of Read procedure in 8080 parallel interface mode CS# RD# D[7:0] D/C# WR# high low Solomon Systech Apr 2008 P 16/59 Rev 1.1 SSD1306 Table 8-3 : Control pins of 8080 interface Function Write command Read status Write data Read data RD# H ↑ WR# ↑ H H ↑ ↑ H CS# L L L L D/C# L L H H Note (1) ↑ stands for rising edge of signal (2) H stands for HIGH in signal (3) L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 8-4. Figure 8-4 : Display data read back procedure - insertion of dummy read WR# RD# Databus N Write column address 8.1.3 Dummy read n n+1 n+2 Read 1st data Read 2nd data Read 3rd data MCU Serial Interface (4-wire SPI) The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and R/W# (WR#)# can be connected to an external ground. Table 8-4 : Control pins of 4-wire Serial interface Function Write command Write data E(RD#) Tie LOW Tie LOW R/W#(WR#) Tie LOW Tie LOW CS# L L D/C# L H D0 ↑ ↑ Note (1) H stands for HIGH in signal (2) L stands for LOW in signal SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock. Under serial mo