Reference / Paper · c. 1979

Motorola AN-851 — MC6845 CRTC Simplifies Video Display Controllers

A low-to-high edge on LPSTB latches the refresh address into R16/R17.

Author: Charles Melear and Jack Browne, Motorola Semiconductor
Year: c. 1979
Type: Reference / Paper
Credit: Motorola. Copy via bitsavers on the Internet Archive

mc6845
crtc
light pen
lpstb

® AN-8S1 MOTOROLA Application Note Semiconductor Products Inc. MOTOROLA MC684S CRTC SIMPLIFIES VIDEO DISPLAY CONTROLLERS Prepared by Charles Melear and Jack Browne Microprocessor Applications Engineering Austin, Texas monitor. Systems could range in complexity from those which display only a few lines of data to complicated word processors. Historically, character printers gave way to line printers. However, obtaining hard copy is cumbersome and slow, and a considerable amount of paper is used. Much of this information is used only momentarily and then discarded, such as inventory checks or airport flight schedules. The efficiency of low cost, high performance video monitors have The need for displaying visual information by the general business community has found widespread applications. Banks, airports, department stores, and other businesses need rapid display of visual information at points of sale and points of use. Much of this information is generated by people who have only a limited knowledge of the electronics involved. Therefore, they must rely on the equipment used to automatically receive data, digest it, and display it on a video MC6808 Microprocessor Secondary Bus Display RAM B Logic 8 Parallel-to Serial Shift Register Display Enable Hex D Flip-Flop A14 A15 R/W Video Output Flip-Flop Video Out made the transition from hard copy to visual display even more advantageous. As video monitors have come into general use, the requirement for cost savings in the controller has intensified. LSI circuits have been appearing which meet that need. The Motorola MC6845 CRT controller (CRTC) can economically solve many of the problems encountered with video monitor displays. This is acomplished by using an innovative design aimed at complete control of the monitor with intervention by the MPU only when new information is put into the display memory. The problems to be solved by the MC6845 in a raster scan video display controller are: cost, number of required components, amount of intervention by MPU, timing and synchronization of signals, and software, among others. Today, CRT controllers can be built using an MC6845 which require approximately 25 ICs plus the extra chips required for memory. This number represents only a fraction of the parts required just a few years ago when SSI and MSI logic devices were used. CRT controllers were built using SSI and MSI logic devices which required well over one hundred ICs. With the MC6845 approach, the number of ICs can be reduced to approximately 25 plus those required for memory. To illustrate the capabilities of an MC6845 based terminal, the software and "rough" hardware considerations used in its design are discussed. The terminal, as shown in Figure I, has the following features: Move Cursor Up One Line Blinking Cursor Carriage Return Paging Backspace Home Cursor Line Feed Clear Screen Automatic Scrolling The CRTC has an address register that can point to any one of eighteen buried registers as shown in Figure 2. These can be programmed for up to 256 characters per row and 128 rows per screen with the only limitation being the bandwidth of the monitor. For this terminal, an 80 by 24 format of 7 by 9 dot matrix characters is used. Horizontal and vertical sync positions are programmable allowing the CRTC to generate the horizontal and vertical retrace pulses. A blanking signal (display enable) is generated during both horizontal and vertical retrace. Two sets of address lines are used. The first set of fourteen lines cycles in a binary fashion through the display memory and is incremented with each CRTC clock pulse. The second set of four lines can be used to address the row address select lines of a character generator. These also cycle in a binary fashion and are incremented with each horizontal sync pulse. A cursor, which may be programmed to blink, is also generated by the CRTC. It will be displayed at the address held in the CRTC cursor address register. SYSTEM IMPLEMENT AnON Figure 3 represents a complete MC6808-MC6845 based system capable of receiving a digital input, processing it, and displaying alphanumeric data on a video monitor. The timing for the system is derived from a dot clock oscillator. Its frequency determines the rate at which information is shifted to the monitor. The dot clock oscillator output is divided by a counter to obtain the character rate clock. For a 9 column by 12 row character block which accommodates a 7 by 9 character, binary 8 is detected at Q3 on the counter and the resulting inverted output is fed into the synchronous clear input of the counter. For a 7 by 9 block, a logic gate could detect binary 6 on QO, QI, and Q2. It is important to use a counter with a synchronous clear so the clear pulse will be one dot clock period wide. The character clock (generated by the rising edge of Q3) serves as a shift/load signal for the output shift register and a clock to latch data from the display memory. The CRTC clock (generated by the trailing edge of Q2) is used to clock the MC6845 CRTC. Each character rate clock increments the address lines (MAQ-MAI3) of the MC6845. The display memory must be capable of being controlled by either the MPU or the CRTC. Therefore, the address lines for both devices (AQ-A13 and MAQ-MA13) are routed through multiplexers such as the SN74LS157. The MPU takes control of the display memory only when a new character is to be written. The output of the multiplexer addresses the memory. As shown in Figure 3, the 8K x 8 static display memory requires 10 address lines for the address bus of the memory elements and 3 address lines for the 3-to-8Iine decoder which drives the chip selects of the memory elements. The output of the display memory is fed into an 8-bit latch (74LS374) and is clocked into the latch on the next character clock. This latch helps to prevent address line jitter which could present spurious data to the character generator ROM. The character clock is used to latch data into the SN74LS374. This creates a one character clock delay from the time that an address becomes valid to the memory until data is presented to the character generator ROM. The character clock is also used to load the parallel word from the character generator ROM into the shift register, producing a second character clock delay. Once the shift register is loaded the dot clock is used to serially shift data from the shift register to the video driver. In order to synchronize both the display enable and cursor output with the shift register output, a two CRTC clock delay must be imposed. Both signals are synchronous with the CRTC address lines. To implement this delay, the two signals (cursor and display enable) are clocked through two latches by the noninverted character clock and fed into the video driver. The video signal is the combination of the shifted data ORed with cursor and then ANDed with Display Enable. This is fed into a "D" flip-flop and clocked out by the dot clock. The CRTC generates row addresses for the character generator ROM. Cycling is synchronized within the CRTC by the horizontal sync pulse (HSYNC) so that the address lines are incremented by each HSYNC. When the MPU is required to read or write to the display memory, the address line multiplexer must be switched to the MPU address lines. Since the display memory is located from $‫סס‬oo to $3FFF, address lines AI5 and AI4 will both be logic "0" if and only if the display memory is being addressed. Therefore, only "00" needs to be decoded on these two lines as an MPU address select line. In normal operation where the CRT controller is controlling the display memory, the secondary data bus is being driven by the display memory. Also, the MPU data bus is being driven by the MPU or some other peripheral. This requires that the two data buses be isolated from each other except during an MPU read or write of the display memory. This requires bus transceivers that can be set to the high-impedance state in both directions. These are shown in Figure 2 as three MC6885 Hex Buffer-Inverters. (If octal buffers are used, only two are required.) To complete the entire system, RAM, ROM, and I/O interface circuitry is placed on the data buses. The RAM is used primarily for a scratch pad memory and the locations accessed by the stack pointer register. The ROM contains the operating program to service the I/O interface. The I/O interface can be a keyboard outputting parallel ASCII code or row/column information. As long as some method can be programmed to receive digital data and transfer it onto the data bus, the CRT controller, using an MC6845, can display that information on a video display. Horizontal CTR (-;- 256) MC Vertical Control Vertical Sync Position Reg Interlace Mode Reg Linear Address Generator r ''';r' t 4 I R~R/W lAD 23 ~~; ~Al ~A2 (3~A3 A4 1 S: ~ AS A6 ~~ e50l ~ ~ ~C"Sl ~rn ,At3 ~rn lAW 5 7400 9 8 HSYNC 10 Data Bus ~A3 A4 00..1.... ::i ~ IA15 10 --=r ~AO AD 6 VSYNC ~ 13 C53 15 C55 ~ ~~~ 02+ ...i... gAl g A8 ~A9 ~CSO ~CSl ~CS2 D4~ 05 ~ 07 ....!!... D6....!!... I ..L 02 ..L 03 ...L 01 Ol~ D3 CRTC Clock 00-4- A4 04 CLK ~ 05 ~ D6..!.. 07 ..!.. ~CS3 ::;1~11/;lml~I******'!!ili!? >l NIl:lI<'\ iQl i'jIMll<lllllll::; IEl \f y X 1 MAD MAl MA2 ; 31~161~ MA3 MA4 MA5 MAS 10 ~ 131 MA7 MAS or:{ ~« ,1m« :1,r~« «~ J:~ <{ 2 3 5 6 11 10 14 13 2 MA9 3 5 MAlO MAll ;: - 0 6 I MA121MA13 4: ~ 31 ~16 11 10 14 13 -~r6~ ~llJJIJ, AT CuI/Series Resonant A15n.9~ 8 n..J.LJ '~ At3 Al2 6 -- ABC 5 AI4 VMA~ R/W 4 r C A B YD~ Yl~ Y2 74lS138 Gl G2A Y3~ Y4~ G2B 3 10 4 20 7 30 8K )(8 H*--- Static 14 60 la~ 2Q~Al 3a~A2 4Q~A3:;:;: 5O~A4 6Q~ 17 70 7Q~A6 8 40 13 50 Display Y5T~~tI:: Memory lStores Screen Characters I 18 80 C51 C52 J ~;i eLK 2 AI55~ ~ 11 11 =~~~ AO '<t AS3 24 11 DO 7 D1~B D2~C D3~D 04~E 05 ~ 12 A F Character ::I~~~::h >-j ..~ 6E- 3 15 5 7 J,J QAOBOCOCOEDF IA 214 OOID! MC6887 (MeaT9]) 18 Ie 6 10 10 Shift ~ 2 4 610 11 13 ~;IBICID DEOF ......! em IE 12 02 0304051 IF 141 21.1 MC68B7 (MeaT9?) OA 00 ,......2 1E 51 7 9 12114 DO 01102 D3 OOID7 3 fA IB Ie 10 NC- IF 00 MC6887 IMCBT971 OAABOCOD I "" :l:JJ,:1 D4 4 3 7404 .••••••• " '-74V u~ 01 02 03 1"1" 6 ,-;T;r 10 20 3D 40 eLK 10 20 CLK ~5V 10' 113 2eeR 2PR 20 9 208 12 20 Display Enable 1~ A15 A14 07 w 00 rr [ ;r :;l l]5 Three-StBle Buffers ENi 74163W" Q.. Register 9 11 ---"'- 00 , EI'l1 74165 ~LK I '= II: ..J 1 D6~G 80t!2 <0 Z 4-811 Counter f: QH~ Ge;~r~lOr AS '0 14 13 RS2 ~23 ;::: ~ ~ I- Z 9 ~20 21 7432 A15 A14 I ~20 J::lll A ti ~~ 71 9 12 4 0 I 11 2CLK 1 74a3 74LS]4 )L--110 3 1 eLK 1 PR A R/W " 7404 10 ~ 1 CLA 4U 6+sv DEVICE IMPLEMENTATION The MC6845 CRTC has 18 programmable registers (RO-RI7 in Figure 2) that control: the horizontal and vertical sync, number of characters per row, number of scan lines per row, number of rows per screen, the portion of memory to be displayed, cursor format and position, and the choice of one of three interlace modes. The first four registers, ROthrough R3, are concerned with the horizontal format. These registers determine the number of characters to be displayed, their width, and horizontal position. Programming considerations are based on the period of the monitor, i.e., the sweep plus retrace time. Also, the horizontal sync pulse should occur slightly after the beam is driven past the right-hand side of the screen. It is important to note that the beam is over driven on the left side of the screen as well as the right. This means that a certain time elapses between the horizontal sync pulse and when the beam sweeps onto the screen from the left and is at the position for it to start displaying data. ro u 0'::; co u 0'::; ID > CD > l.- L Display Period Horizontal Retrace Period Vertical Retrace The period of the monitor should be divided into character times (see Figure 4). This will define the width of a character block and this value will be stored in the Horizontal Total Register (RO). A video monitor will require about 20070of the period to be reserved for retrace (see Figure 5), as opposed to about 35% for a TV. This means that the Horizontal Displayed Register (RI), which contains the number of characters to be displayed per row, will not usually exceed about 80% of the value in RO. If RO contains a very small number, each character will be very wide. Likewise, if RO contains a large number, the characters will be very narrow. The Horizontal Sync Position Register (R2) is programmed in character times and should be positioned such that it will occur slightly after the beam is driven past the right margin of the screen. The Horizontal Sync Width Register (R3), programmed in character times, should provide sufficient width to allow the discharge of the circuitry driving the horizontal sweep. It should be noted that the value in ROusually exceeds the sum of the values in R2 and R3. This is to allow for the time required for the beam to sweep onto the screen from the left margin since it could be over driven to the left. I I I •• Horizontal Total RO , I' 1------1 ~ Display Enable ., I I Horizontal Display R1-.J I I I I Horizontal Sync Width R3 ---..: ~ Horizontal Sync Position R2 I 1 ----~ I I I ~ ---.1L Horizontal' Sync I MAO- I ~~~rrrrrJI Four registers, R4-R7, are used to set up the vertical format (see Figure 6). The frequency of the horizontal oscillator and the vertical refresh rate must be known. Generally, the vertical refresh rate is 60 Hz. The horizontal frequency, usually 15,750 Hz, divided by the frame refresh rate is equal to the total number of scan lines per frame. The vertical sync pulse requires 16 scan lines. This means that the programmer cannot use the total number of scan lines for information display. A character block which contains the character to be displayed, plus spacing columns to the right and additional scan lines on the bottom, is chosen by the programmer. Typically, a character generator ROM with a 7 x 9 matrix element will be placed in a 9x 12 character block. The Vertical Total Register (R4) contains the number of character rows per screen which is equal to the total number of scan lines divided by the height of the character block. This height is programmed in scan lines and placed in the Max Scan Line Address Register (R9). The number of scan lines left over is written into the Vertical Adjust Register (R5). All scan lines must be accounted for so the CRT controller will exactly match the vertical refresh rate; otherwise, the display will "swim" or have a wavy motion. The Vertical Displayed Register (R6) contains the number of character rows that the programmer wishes to be displayed. The Vertical Sync Position Register (R7) contains the position of the vertical sync pulse. This number, programmed in character times, must be I..I 1 I .1 I Vertical Total R4 II t-+-- Vertical Displayed R6 --.: " I , I Display 1_.-----1I I ---.J Enable !-+-- I l:...- ---.n _ I Vertical Sync Position R7 , I Vertical Sync , I I Vertical : I Adjust ...• R5 1 I greater than or equal to the Vertical Displayed Register (R6), but not so much greater that it shifts the last rows of the displayed text off the bottom of the screen. Once these registers are set up, the raster is completely defined. Three operating modes are available with the MC6845 which have to do with which field (odd or even) that information is written into. The first mode, Normal Sync, writes information into one field only (see Figure 7). Remember, one frame requires two vertical sweeps of the screen. The first sweep (even field) starts at the upper left corner of the screen and the second sweep (odd field) starts at the top center. When writing into one field, each dot will be updated 60 times per second. Raster Add. Raster Add. 0----- ~=I~~~P i]~~~E! 0----- 1 0 2 3 0 0 0 0 4 00000 0 5 0 0 6 7 0 0 0 0 Normal Sync Master Add. 0----- 2-8---3-1 1-0---0-0 5- 67- - - --- -4 -5 -6 --Even Field - e - - - e -7 - - - Odd Field Interlace Sync Interlace Sync and Video The second mode, Interlace Sync, writes in both fields. The odd field is an exact duplicate of the even field. Essentially, the same information is written twice. This has the advantage of making the letters appear to have solid vertical lines thus improving resolution. However, each dot is now refreshed only 30 times per second which may cause an objectionable flicker on the screen. This flicker cannot be perceived by all people due to variances in eye sight. Also, the persistance of the phosphor will moderate the effect of the flicker. The third mode, Interlace Sync and Video, also writes in both fields. However, one half the character is written in each field. This means an eight row character block in this mode will have four scan lines in the even field and four in the odd field making a character only half the height of the other two modes. This allows the highest screen density for the MC6845. These modes are programmed in the Interlace Mode Register (R8). The MC6845 also controls the cursor format and blink rate (see Figure 8). Each character row has a certain number of scan lines as defined by the Max Scan Line Address Register (R9). The Cursor Start Register (RIO) specifies on which scan line the cursor begins. Also, this register contains a bit that specifies whether the cursor will blink or not blink. Another bit specifies the blink rate which is either one sixteenth or one thirty second of the field rate. The Cursor End Register (RII) specifies the scan line at the bottom of the cursor. If the same number is specified for both the starting and ending scan line, the cursor will be one line tall. There are six remaining registers. The Start Address Registers High (RI2) and Low (RI3), contain the address of the first byte of memory to be displayed after vertical retrace. The Cursor Registers High (RI4) and Low (RI5) contain the address where the cursor will appear. The Light Pen Registers High (RI6) and Low (R17) will receive the current address appearing on the CRT control address lines following the recognition of the low-to-high transition of the light pen strobe (LPSTB) input. Once the LPSTB low-to-high Raster Address Raster Address o -+-+-+-i-+-+--+- o -+-+-+-H-+-+- 1 -+-+-+-+-+-+-+- 1 "'M$EIl~r 4-+-++-+-H-+- lD1l1 2-4++-+-H-+3-+-+-+-i-+-+-+- 5-+-+-+-i-+-+--+6-+-+-+-i-+-+-+7-+-+-+-<H-+-+8-+-+-+-H-+-+- 6 -+-++-+-~-+- 10-+-+-+-H.-+-+-11-+-+-++-+-+-+- 9 -$4MMl$EJr 7-+-++-+-I-+-+-8 -+-++-H-+-+9-+-++-H-+-+10-+-+++-+-+-+11-+-++-+-+-+-+- Cursor Start = 9 Cursor End = 9 Cursor Start = 1 Cursor End = 5 FIGURE 8 - Cursor Start and End Register transition is recognized, the next low-to-high CRTC clock transition latches the address information and loads it into the Light Pen Register. These registers are used primarily by the programmer who writes the software for the terminal. The method in which they are used is discussed in the software considerations portion of this application note. In order to complete the hardware discussion, the dot clock and character clocks must be defined. The character clock rate will be the product of the horizontal oscillator frequency and the total horizontal character times described in calculating the value for RO. The dot clock will be the product of the character rate clock and the width of the character block in columns. This requires a different dot clock for each screen format. SOFfWARE IMPLEMENTATION Once the system has been defined, software development may begin. The firmware residing in ROM will initialize and support the terminal. When power is applied to the system, the MPU automatically jumps to the reset address stored in location $FFFE and $FFFF. This address is the beginning of the initialization sequence. After a power-on-reset, the display memory is initialized (to avoid a flash of false data), the eighteen buried registers of the CRT controller are initialized, and characters are accepted from the keyboard. Some control characters will be decoded to implement the following features: Carriage Return Move Cursor Up One Line Backspace Paging Line Feed Home Cursor Clear Screen Scrolling up or down will be done automatically as required. The software was developed using the concepts of structured programming. The first two routines which were written support the hardware development and debugging. The first routine is named CHARON and its flowchart is shown in Figure 9. This routine initializes the display memory with successive ASCII character codes which help identify addressing problems. The second routine is named CRTINT and initializes the CRT controller (see flowchart in Figure 10). The register values to implement an 80 by 24 display are read from the ROM and stored into the buried registers of the CRT controller. Again, it is important to initialize the display memory prior to initializing the MC6845, to avoid a flash of false data. After the system has been initialized by running this program (as listed in Figure 11), waveforms, timing, and data may be checked, thus speeding the design phase. Initialize Register Counter and Parameter Counter Increment Register Counter and Parameter Counter FIGURE 10 - CRTINT Subroutine Flowchart Initializes the CRTC registers with the previously calculated values stored in the ROM . FIGURE 9 - CHARGN Subroutine Flowchart Loads ASCII character codes into display memory. PAGE 001 BOOT •SA:l 00001 4000 A CRTCAD 00002 4001 A CRTCRG 00003A E3FE 00004A E3FE EO A 00005A EOOO 00006A EOOO 4F CHARGN 00007A E001 CE 0000 A 00008A E004 A7 00 A CHAR 00009A E006 4C 00010A E007 08 OOOllA E008 8C 1000 A 00012A EOOB 26 F7 E004 OOOl3A EOOD 5F CRTINT OOO14A EOOE CE E022 A 00015A EOll F7 4000 A CRTIN1 00016A E014 A6 00 A 00017A E016 B7 4001 A 00018A E019 08 00019A E01A 5C 00020A E01B C1 10 A 00021A E01D 26 F2 EOll 00022A E01F 01 LOOPER 00023A E020 20 FD EOlF 00024A E022 30 A TABLE 00025A E028 12 A 00026 TOTAL ERRORS 00000--00000 EQU EQU ORG FCB ORG CLRA LDX STAA INCA INX CPX BNE CLRB LDX STAB LDAA STAA INX INCB CMPB BNE NOP BRA FCB FCB END $4000 $4001 $E3FE $EO,O $EOOO FILL #$0000 O,X #$1000 CHAR #TABLE CRTCAD O,X CRTCRG SCREEN WITH CHARACTER STORE CHARACTER GET NEXT CHARACTER MOVE TO NEXT LOCATION FINISHED FINISHED? INITIALIZE CRTC SELECT CRTC REGISTER #$10 CRTIN1 LOOPER $30,$26,$2B,$02,$14,$01 $12,$13,$00,$OB,$40,$08,$00,$00,$00 FIGURE 11 - CRT OEM Listing This program, resident in PROM, will initialize the display memory with successive ASCII characters. This will allow initial checkout of the hardware. These routines must be modified and additional routines written to implement all of the features of the terminal. A MONITOR program (see flowchart in Figure 12)is called by the reset vector stored in the ROM. Under control of the monitor program, the stack pointer is initialized at the end of the RAM (address $A07F), the self-modifying sections of code are dumped to the RAM, and all variables are initialized. The BLANKR subroutine is then called. It is a revision of the CHARON subroutine (see flowchart in Figure 9 and listing in Figure 11). Instead of stepping through the entire ASCII character code, the ASCII blank code ($20) is stored in the display memory. After the display memory has been filled with blanks, the CRTINT subroutine, discussed previously, is called. The monitor program calls CHARRC, a subroutine which accepts and processes a character. Control is returned to the monitor program which in turn loops on the CHARRC subroutine call. The result is that the terminal continuously accepts characters. A flowchart of CHARRC appears in Figure 13. The CHARRC subroutine calls the input character subroutine INCH (see flowchart in Figure 14), which receives one keyboard entry. Accepts FIGURE 12 - MONITOR Program Flowchart Calls all routines required to implement the terminal. FIGURE 13 - CHARRC Subroutine characters from keyboard, moves cursor, and decodes all special characters. 8 The special functions are implemented using control characters which are not normally utilized by CRT terminals. Table 1 lists the feature and its control character and indicates which routine processes the command. Each time one of the special characters is received, a jump to the appropriate routine occurs. All characters received from the keyboard, except for the special control characters, are written to the current cursor location, the cursor is moved one space, and a blank is written under the cursor. To facilitate carriage returns, a space counter (SPACES) is used. It keeps track of the cursor displacement from the beginning of the current line. The counter (SPACES) is used whenever a carriage return key is pressed. The cursor is moved back to the beginning of the line by subtracting the number of spaces from the Cursor Registers (R14 and RI5). A line feed is then generated by adding the number of characters per line to the Cursor Register. The CRT controller treats the screen memory as a linear array such that the last space of a line and the first space of the next line are located at adjacent memory locations. When the cursor is at the end of a line and another character is input, the cursor moves to the first of the next line. The space counter (SPACES) must be reset. Yes Get Input Character Code From PIAAD FIGURE 14 - INCH Subroutine Flowchart Polls PIA A Control Register until IRQA 1 is set, then the data is retrieved from the PIA A Data Register. Keyboard Entry Subroutine Name Flowcharted in Figure None SCROLU 15b Called whenever a line feed is generated. Will add a line to bottom of screen when necessary. Carriage Return CR Key CR 16 Generates carriage return, calls LF. Line Feed LF Key LF 17 Generates line feed, calls SCROLU. Back Space © H BS 18 Generates back space and blanks under cursor, calls SCROLD when cursor moves back to previous line. UPLINE 19 Moves cursor up one line, calls SCROLD. Clear Screen © $ © D © A © G Scroll Down None Feature Scroll Up . Move Cursor Up One Line Move to Next Page Home Cursor Result PAGE 20 Moves to same place on next page. HOME 21 Moves cursor. CLEAR 22 Clears page starting at cursor. SCROLD 23 Called whenever cursor moves back one line. Adds a new line to top of screen when necessary. -1840 } _ 1919 23rd Line 1919 1920 24th Line Remainder 1999 } { 2047 2047 } Remainder FIGURE 15a - Scrolling Performed by changing the Start Address in R12 and R13 in the CRTC. This example shows how an 80 x 24 display is scrolled up one line. FIGURE 16 - CR Subroutine Flowchart Generates a cursor return by subtracting SPACES (the space counter) from the current cursor position in R14 and R15 of the CRT. Jumps to LF to generate a line feed. Clear the Portion of the Line at Beginning of Display Memory Calculate Remaining Number of Spaces to Be Blanked Increment Start Address by Number of Characters per Line Blank Rest of Line at End of Display Memory FIGURE 15b - SCROLU Subroutine Flowchart The 14-bit cursor address is checked to see if cursor has moved off the screen. If so, the 14-bit start address is incremented to add a new line (with the cursor) at the bottom. FIGURE 17 - LF Subroutine Flowchart Generates a line feed by adding the number of characters per line to the current cursor position stored in R14 and R15 of the CRTC. Jumps to SCROLU to see if a new line should be scrolled on the page. Whenever SPACES is reset, the scroll up routine (SCROLU) is called to determine if the cursor is still on the CRT screen. If the cursor has moved off the bottom of the CRT screen, then the Start Address Registers (R12 and R13) are adjusted to scroll a new line in at the bottom of the screen. The SCROLU routine is illustrated in Figure 15a and flowcharted in Figure 15b. Flowcharts, describing implementations of the .special features listed in Table 1, are presented in Figures 15-23. Notes at the bottom of each figure explain the algorithms employed. When the routine to generate a line feed LF (flowcharted in Figure 17) is called, the cursor is moved down one line. Because this may move the cursor off the screen, the SCROLU routine, to scroll up one line, is called. Similarly, whenever the backspace routine or the routine to move the cursor up one line (UPLINE, see flowchart in Figure 19) is called, the cursor may be moved back to the previous line. This may also move the cursor off the top of the screen requiring the routine which scrolls down one line (SCROLD, see flowchart in Figure 23) to be called. The scrolling, whether up or down, is implemented by modifying the starting address stored in CRTC Registers R12 and R13. Scrolling up is implemented by adding or subtracting the number of characters per line to the start address. Note that the CRTC Cursor Registers R14 and R15 are the only read/write registers. This requires the use of a variable to retain the current start address duplicated in R12 and R13 (write only). FIGURE 20 - PAGE Subroutine Flowchart Moves to the same position on the next page by adding PAGES to the high order byte of the starting address (R12l and the high order byte of the cursor pOSition (R14l. PAGES multiplied by $100 equals the number of characters per page. FIGURE 18 - BS Subroutine Flowchart Backspaces and blanks under cursor. Jumps to SCROLD and checks if the cursor has moved off the top of the screen. Reset Start Address to the First Line of the Current Page Reset Cursor Position to the First Line of the Current Page FIGURE 19 - UPLINE Subroutine Flowchart Moves the cursor up one line by subtracting the number of characters per line from current cursor position stored in R14 and R15 of the CRTC. Jumps to SCROLD to check if the cursor has moved off the top of the screen. FIGURE 21 - HOME Subroutine Flowchart Reset start address and cursor position to the beginning of the current page, then clear SPACES and jump to CLEAR to put blanks in each display memory element of the current page. FIGURE 22 - CLEAR Subroutine Flowchart Stores ASCII blank, code $20, into all memory locations on the current page starting at the cursor. FIGURE 23 - SCROLD Subroutine Flowchart Checks to see if the cursor is before the screen by seeing if the cursor position registers (R14 and R151 are less than the Screen Start Registers (R12 and R13l. If so, the start address of R12 and R13 is decremented by CHRPLN, the number of characters per line. A complete listing of the software appears in Figure 24 and will implement all the described features. A semi-structured approach is utilized to simplify changes or additions. The MC6845 CRTC supplies the video and sync pulses to the CRT and may be programmed by the MC6808 MPU for different screen formats. In fact, formats can be changed "onthe-fly" provided that the appropriate dot clocks are available. Additional "bells and whistles," such as page editing, block transmit, or receive could be added. Interface circuitry, not described herein, should be added for a parallel or serial interface. A programmable character generator would allow the use of semigraphics. Full graphics could also be implemented with each memory bit corresponding to a dot on the CRT screen. A non-encoded keyboard could also be used with the software expanded to decode the keyboard. Additional ICs could be added enabling the MPU and CRTC to run on different phases so that the MPU has transparent access to the display memory. The software, developed in this article, may be used as is or used as a building block to implement additional features. PAGE 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043A 00044 00045 00046 00047 00048 00049 00050 00051 00052A 00053 00054 00055 00056A 00057A 00058A 001 CRTC .SA: 1 CRTC NAM CRTC ************************************************* HARDWARE CONFIGURATION * $FCF4 ACIA * ROM $EOOO * RAM $AOOO * CRTC $4000 * SCREEN MEMORY $0000 * ************************************************* FCF4 FCF5 3000 3001 4000 47DO 0040 0004 OOFC 0002 OOAB AOOO AOOI A002 A006 A007 A006 A007 AOOA AOOE A011 A012 A013 A014 A015 A016 EOOO EOOO 8E A07F E003 4F E004 B7 AOOI E007 B7 A002 A A A A A A A A A A A * * ACIACS ACIADA CRTCAD CRTCRG * * SCRNST SCRNND MOVE PAGESZ PGMASK SCRNH SCRNL SET UP PERIPHERAL ADDRESSES EQU $FCF4 ACIA CONTROL/STATUS REG EQU ACIACS+l ACIA DATA REGISTER $3000 CRTC ADDRESS REGISTER EQU EQU CRTCAD+l CRTC DATA REGISTER SET CONSTANTS $4000 SCREEN STARTING ADDRESS EQU SCRNST+2000 SCREEN END ADDRESS EQU $40 SCREEN OFFSET EQU $04 CHARACTERS PER PAGE EQU MASK TO GET CURRENT PAGE EQU $FC EQU $02 CHARACTERS ON SCREEN EQU $AB * * * DEFINE * * * INITIALIZE VARIABLE LACATIONS $AOOO RAM STARTING ADDRESS EQU RAM+l EQU CHARACTER POINTER L EQU RAM+2 EQU RAM+6 RAM+7 BLANK POINTER L EQU BACK SPACE POSITION H BLANKH EQU BACK SPACE POSITION L BLANKL EQU HOME UP POINTER EQU RAM+I0 RAM+14 HOME END POINTER EQU EQU RAM+17 SPACE COUNTER RAM+18 DISPLAY START ADDRESS H EQU DISPLAY START ADDRESS L EQU RAM+19 END OF SCREEN EQU RAM+20 RAM+21 END OF SCREEN EQU CHARACTERS PER LINE EQU RAM+22 $EOOO STARTING ROM ADDRESS ORG ************************************************* MONITOR PROGRAM * INITIALIZES THE STACK POINTER * CODE INITIALIZES THE SELF-MODIFYING * INITIALIZES THE DISPLAY MEMORY * INITIALIZES THE CRTC * ACCEPTS INPUT CHARACTERS * ************************************************* #$A07F INITIALIZE STACK POINTER A LDS A A A A A A A A A A A A A A A A A RAM CHARH CHARL BLANKH BLANKL BSPOSH BSPOSL INDEX COMPR SPACES STARTH STARTL ENDH ENDL CHARLN CLRA STAA STAA THE SELF-MODIFYING CODE ZERO A ACCUMULATOR CHARH CHARL IN RAM PAGE 002 CRTC 00059A 00060A 00061A 00062A 00063A 00064A 00065A 00066A 00067A 00068A 00069A 00070A 0007lA OOOnA 00073A 00074A 00075A 00076A 00077A 00078A 00079A 00080A 00081A 00082A 00083A 00084A 00085A 00086A 00087A 00088A 00089A 00090A 00091 00092 00093 00094 00095A 00096A 00097A 00098A 00099A OOlOOA OOlOlA 00102 00103 00104 00105 00106A 00107A 00108A 00109A OOllOA OOlllA 001l2A OOl13A 001l4A 00115 00116 EOOA EOOD EOIO E013 E016 E019 EOIC EOIF E022 E025 E028 E02B E02D E030 E033 E035 E038 E03A E03D E03F E042 E045 E048 E04A E04D E04F E052 E054 E057 E059 E05B E05D B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 86 B7 B7 86 B7 86 B7 86 B7 B7 B7 86 B7 86 B7 86 B7 8D 8D 8D 20 E05F E061 E064 E066 E067 E06A E06C E06D E06E E07l E074 E076 E079 E07A E07B E07D .SA:l CRTC A006 A STAA BLANKH ZERO BLANKH/BSPOSH POINTER A007 A STAA BLANKL ZERO BLANKL/BSPOSL POINTER AOOA A STAA INDEX AOOB A STAA INDEX+l AOOE A STAA COMPR AOOF A STAA COMPR+l AOll A STAA SPACES A012 A STAA STARTH A013 A STAA STARTL A014 A STAA ENDH A015 A STAA ENDL B7 A LDAA #$B7 STORE "STA A" OP CODE AOOO A STAA RAM A005 A STAA RAM+5 86 A LDAA #$86 STORE "LDA A" OP CODE A003 A STAA RAM + 3 20 A LDAA #$20 STORE ASCII "BLANK" A004 A STAA RAM+4 39 A LDAA #$39 STORE "RTS" OP CODE A008 A STAA RAM+8 AOOC A STAA RAM+12 AOIO A STAA RAM+16 CE A LDAA #$CE STORE "LDX" OP CODE A009 STAA A RAM+9 8C A LDAA #$8C STORE "CPX" OP CODE AOOD A STAA RAM+13 26 A LDAA #$26 SET NO. CHAR PER LINE A016 A STAA RAM+22 06 E05F BSR BLANKR FILL SCREEN WITH BLANKS 12 E06D BSR CRTINT INITIALIZE CRTC 32 E08F RUN BSR CHARRC RUN PROGRAM FC E05B BRA RUN ************************************************* BLANKR SUBROUTINE FILLS DISPLAY MEMORY WITH * BLANK CODE ($20). * ************************************************* 86 20 A BLANKR LDAA #$20 INITIALIZE SCREEN MEMORY LDX #SCRNST DISPLAY START ADDRESS CE 4000 A A7 00 A BLANKI STAA o ,X STORE CHARACTER INX 08 NEXT SCREEN LOCATION 8C 47DO A CPX #SCRNND FINISHED? 26 F8 E064 BNE BLANKI 39 RTS ************************************************* CRINT SUBROUTINE INITIALIZES CRTC BY LOADING * THE BURRIED RIGISTERS. * ************************************************* CRTINT CLRB INITIALIZE CRTC 5F CE E07F A LDX #TABLE CRTCAD SELECT CRTC REGISTER F7 3000 A CRT STAB LDAA O,X GET TABLE VALUE A6 00 A STORE CRTC PARAMETER B7 3001 STAA CRTCRG A GET NEXT TABLE VALUE INX 08 SELECT NEXT CRTC REGISTER INCB 5C CMPB Cl 10 A #$10 LAST CRTC REGISTER 26 F2 E07l BNE CRT * * TABLE FIGURE 24 - OF VAU Complete Listing of CRTC Software (Continued) PAGE 003 00117 001l8A E07F 001l9A E080 00120A E081 00121A E082 00122A E083 00123A E084 00124A E085 00125A E086 00126A E087 00127A E088 00128A E089 00129A E08A 00130A E08B 00131A E08C 00132A E08D 00133A E08E 00134 00135 00136 00137 00138A E08F 00139A E091 00140A E093 00141A E095 00142A E097 00143A E099 00144A E09B 00145A E09E 00146A EOAO 00147A EOA2 00148A EOA5 00149A EOA7 00150A EOA9 00151A EOAC 00152A EOAE 00153A EOBO 00154A EOB3 00155A EOB5 00156A EOB7 00157A EOBA 00158A EOBC 00159A EOBE 00160A EOCI 00161A EOC3 00162A EOC5 00163A EOC8 00164A EOCA 00165A EO CD 00166A EODO 00167A EOD3 00168A EOD4 00169A EOD7 00170A EODA 00171A EODC 00172A EODF 00173A EOE2 00174A EOE4 CRTC .SA:l CRTC * 30 26 2B 02 14 01 12 13 00 OB 40 08 00 00 00 00 A TABLE A A A A A A A A A A A A A A A FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB $30 $26 $2B $02 $14 $01 $12 $13 $00 $OB $40 $08 $00 $00 $00 $00 RO Rl R2 R3 R4 R5 R6 R7 R8 R9 RIO Rll R12 R13 R14 R15 HORIZONTAL TOTLA HORIZONTAL DISPLAYED HORIZONTAL SYNC POS. HORIZONTAL SYNC WIDTH VERTICAL TOTAL VERTICAL TOTAL ADJUST VERTICAL DISPLAYED VERTICAL SYNC POSITION INTERLACE MODE MAX SCAN LINE ADDRESS CURSOR START ADDRESS CURSOR END ADDRESS START ADDRESS H START ADDRESS L START ADDRESS H START ADDRESS L ************************************************* * CHARRC SUBROUTINE ACCEPTS KEYBOARD INPUT,DECO * SPECIAL FEATURES AND CONTROLS THE CURSOR. ************************************************* 8D 81 23 20 81 26 7E 81 26 7E 81 26 7E 81 26 7E 81 26 7E 81 26 7E 81 26 7E C6 F7 F6 F7 5C F7 F7 C6 F7 F6 CA F7 7F EllO CHARRC 13 A 02 E097 31 EOC8 OD A DECODE 03 E09E El77 A 08 A DECI 03 EOA5 EIAF A OA A DEC2 03 EOAC E191 A 13 A DEC3 03 EOB3 EIEF A 04 A DEC4 03 EOBA E20C A 01 A DEC5 03 EOCI E22A A 07 A DEC6 03 EOC8 E258 A A CURSE OF 3000 A 3001 A A002 A 3001 A007 OE 3000 3001 40 AOOI A A A A A A A FIGURE 24 - BSR CMPA BLS BRA CMPA BNE JMP CMPA BNE JMP CMPA BNE JMP CMPA BNE JMP CMPA BNE JMP CMPA BNE JMP CMPA BNE JMP LDAB STAB LDAB STAB INCB STAB STAB LDAB STAB LDAB ORAB STAB INCH #$13 DECODE CURSE #$OD DECI CR #$08 DEC2 BS #$OA DEC3 LF #$13 DEC4 UPLINE #$04 DEC5 PAGE #01 DEC6 HOME #07 CURSE CLEAR #$OF CRTCAD CRTCRG CHARL CRTCRG BLANKL #$OE CRTCAD CRTCRG #MOVE CHARH GET INPUT DECODE SPECIAL CHARACTERS NOT A SPECIAL CHARACTER CARRIAGE RETURN? BACKSPACE? LINEFED? MOVE CURSOR NEXT PAGE? HOME CURSOR UP ONE LINE? CLEAR SCREEN? GET CURSOR ADDRESS SAVE CHARACTER L ADDRESS SAVE CURSOR ADDRESS FOR BL GET CURSOR ADDRESS H MOVE CURSOR TO DISPLAY SAVE CHARACTER ADDRESS Complete Listing of CRTC Software (Continued) ADD PAGE 004 CRTC 00175A 00176A 00177A 00178A 00179A 00180A 00181A 00182A 00183 00184 00185 00186 00187 00188A 00189A 00190A 00191A 00192A 00193A 00194A 00195A 00196 00197 00198 00199 00200 00201A 00202A 00203A 00204A 00205A 00206A 00207A 00208A 00209 00210 00211 00212 00213 00214A 00215A 00216A 00217A 00218A 00219A 00220A 00221A 00222A 00223A 00224A 00225A 00226A 00227A 00228A 00229A 00230A 00231A 00232A EOE7 EOEA EOEC EOEF EOFO EOF2 EOF5 EOF8 F6 26 F6 5C 20 F6 F7 F7 .SA: 1 CRTC A007 A 06 EOF2 AOOl A 03 EOF5 AOOl A NOCARY 3001 A CARRYD A006 A LDAB BNE LDAB INCB BRA LDAB STAB STAB BLANKL NOCARY CHARH CARRYD CHARH CRTCRG BLANKH BLANKL=O? INCREMENT IF CARRY REQUIRE INCREMENT