Datasheet · 2010

Microchip MCP4728 12-Bit Quad DAC with EEPROM — Datasheet (DS22187E)

The DAC in proposal AH-5 (emulating gun potentiometers).

Author: Microchip Technology
Year: 2010
Type: Datasheet
Credit: Microchip (microchip.com)

dac
i2c
potentiometer emulation

MCP4728 12-Bit, Quad Digital-to-Analog Converter with EEPROM Memory Features Description • 12-Bit Voltage Output DAC with Four Buffered Outputs • On-Board Nonvolatile Memory (EEPROM) for DAC Codes and I2C™ Address Bits • Internal or External Voltage Reference Selection • Output Voltage Range: - Using Internal VREF (2.048V): The MCP4728 device is a quad, 12-bit voltage output Digital-to-Analog Convertor (DAC) with nonvolatile memory (EEPROM). Its on-board precision output amplifier allows it to achieve rail-to-rail analog output swing. 0.000V to 2.048V with Gain Setting = 1 0.000V to 4.096V with Gain Setting = 2 - Using External VREF (VDD): 0.000V to VDD • ±0.2 Least Significant Bit (LSB) Differential Nonlinearity (DNL) (typical) • Fast Settling Time: 6 µs (typical) • Normal or Power-Down Mode • Low Power Consumption • Single-Supply Operation: 2.7V to 5.5V • I2C Interface: - Address bits: User Programmable to EEPROM - Standard (100 kbps), Fast (400 kbps) and High Speed (HS) Mode (3.4 Mbps) • 10-Lead MSOP Package • Extended Temperature Range: -40°C to +125°C Applications • Set Point or Offset Adjustment • Sensor Calibration • Closed-Loop Servo Control • Low Power Portable Instrumentation • PC Peripherals • Programmable Voltage and Current Source • Industrial Process Control • Instrumentation • Bias Voltage Adjustment for Power Amplifiers © 2010 Microchip Technology Inc. The DAC input codes, device configuration bits, and I2C address bits are programmable to the nonvolatile memory (EEPROM) by using I2C serial interface commands. The nonvolatile memory feature enables the DAC device to hold the DAC input codes during power-off time, allowing the DAC outputs to be available immediately after power-up with the saved settings. This feature is very useful when the DAC device is used as a supporting device for other devices in the application’s network. The MCP4728 device has a high precision internal voltage reference (VREF = 2.048V). The user can select the internal reference or external reference (VDD) for each channel individually. Each channel can be operated in Normal mode or Power-Down mode individually by setting the configuration register bits. In Power-Down mode, most of the internal circuits in the powered down channel are turned off for power savings, and the output amplifier can be configured to present a known low, medium, or high resistance output load. The MCP4728 device includes a Power-on Reset (POR) circuit to ensure reliable power-up and an on-board charge pump for the EEPROM programming voltage. The MCP4728 has a two-wire I2C compatible serial interface for standard (100 kHz), fast (400 kHz), or high speed (3.4 MHz) mode. The MCP4728 DAC is an ideal device for applications requiring design simplicity with high precision, and for applications requiring the DAC device settings to be saved during power-off time. The MCP4728 device is available in a 10-lead MSOP package and operates from a single 2.7V to 5.5V supply voltage. DS22187E-page 1 MCP4728 Package Type MCP4728 MSOP VDD 1 10 VSS SCL 2 9 VOUT D SDA 3 8 VOUT C LDAC 4 7 VOUT B RDY/BSY 5 6 VOUT A Functional Block Diagram LDAC EEPROM A VDD INPUT REGISTER A VSS SDA SCL I2C Interface Logic EEPROM B INPUT REGISTER B EEPROM C INPUT REGISTER C EEPROM D RDY/BSY INPUT REGISTER D Internal VREF (2.048V) OUTPUT REGISTER A UDAC OUTPUT REGISTER B UDAC OUTPUT REGISTER C UDAC OUTPUT REGISTER D VREF Selector VDD DS22187E-page 2 UDAC VREF A STRING DAC A VREF B OP AMP B VOUT B Power Down Control Output Logic OP AMP C VOUT C Power Down Control Gain Control STRING DAC D VOUT A Power Down Control Output Logic Gain Control STRING DAC C VREF D OP AMP A Gain Control STRING DAC B VREF C Output Logic Gain Control OP AMP D VREF Output Logic VOUT D Power Down Control (VREF A, VREF B, VREF C, VREF D) © 2010 Microchip Technology Inc. MCP4728 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Absolute Maximum Ratings† VDD...................................................................................6.5V All inputs and outputs w.r.t VSS ................. -0.3V to VDD+0.3V Current at Input Pins ....................................................±2 mA ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Supply Pins ............................................. ±110 mA Current at Output Pins ...............................................±25 mA Storage Temperature ...................................-65°C to +150°C Ambient Temp. with Power Applied .............-55°C to +125°C ESD protection on all pins ................ ≥ 4 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ) ......................... +150°C ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Operating Voltage VDD 2.7 Supply Current with External Reference (VREF = VDD) (Note 1) IDD_EXT — Typical Max Units Conditions 5.5 V 800 1400 µA VREF = VDD, VDD = 5.5V All 4 channels are in Normal mode. — 600 — µA 3 channels are in Normal mode, 1 channel is powered down. — 400 — µA 2 channels are in Normal mode, 2 channel are powered down. — 200 — µA 1 channel is in Normal mode, 3 channels are powered down. Power Requirements Power-Down Current with External Reference IPD_EXT — 40 — nA All 4 channels are powered down. (VREF = VDD) Supply Current with Internal Reference (VREF = Internal) (Note 1) IDD_INT — 800 1400 µA VREF = Internal Reference VDD = 5.5V All 4 channels are in normal mode. — 600 — µA 3 channels are in Normal mode, 1 channel is powered down. — 400 — µA 2 channels are in Normal mode, 2 channels are powered down. — 200 — µA 1 channel is in Normal mode, 3 channels are powered down. — 45 60 µA All 4 channels are powered down. VREF = Internal Reference Power-Down Current with Internal Reference Note 1: 2: 3: 4: 5: 6: 7: 8: 9: IPD_INT All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. © 2010 Microchip Technology Inc. DS22187E-page 3 MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units Conditions Power-on Reset Threshold Voltage VPOR — 2.2 — V All circuits, including EEPROM, are ready to operate. Power-Up Ramp Rate VRAMP 1 — — V/s Note 2, Note 4 Resolution n 12 — — Bits Code Change: 000h to FFFh Integral Nonlinearity (INL) Error INL — ±2 ±13 LSB Note 5 DNL Error DNL -0.75 ±0.2 ±0.75 LSB Note 5 VOS — 5 20 mV Code = 000h See Figure 2-24 DC Accuracy Offset Error Offset Error Drift Gain Error Gain Error Drift ΔVOS/°C — ±0.16 — ppm/°C -45°C to +25°C — ±0.44 — ppm/°C +25°C to +125°C GE -1.25 0.4 +1.25 % of FSR ΔGE/°C — -3 — ppm/°C 2.048 2.089 V Code = FFFh, Offset error is not included. Typical value is at room temperature See Figure 2-25 Internal Voltage Reference (VREF), (Note 3) Internal Voltage Reference VREF Temperature Coefficient ΔVREF/°C 2.007 — 125 — ppm/°C -40 to 0°C — 0.25 — LSB/°C — 45 — ppm/°C 0 to +125°C — 0.09 — LSB/°C Reference Output Noise ENREF — 290 — µVp-p Code = FFFh, 0.1 – 10 Hz, Gx = 1 Output Noise Density eNREF — 1.2 — Code = FFFh, 1 kHz, Gx = 1 1/f Corner Frequency fCORNER Note 1: 2: 3: 4: 5: 6: 7: 8: 9: — 1.0 — μV HZ — 400 — Hz Code = FFFh, 10 kHz, Gx = 1 All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. DS22187E-page 4 © 2010 Microchip Technology Inc. MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units Conditions Analog Output (Output Amplifier) Output Voltage Swing VOUT — FSR — V Note 7 Full Scale Range (Note 7) FSR — VDD — V VREF = VDD FSR = from 0.0V to VDD — VREF — V VREF = Internal, Gx = 1, FSR = from 0.0 V to VREF — 2 * VREF — V VREF = Internal, Gx = 2, FSR = from 0.0V to 2 * VREF Output Voltage Settling Time TSETTLING — 6 — µs Note 8 Analog Output Time Delay from Power-Down Mode TdExPD — 4.5 — µs VDD = 5V, Note 4, Note 9 Time delay to settle to new reference (Note 4, Note 6) TdREF — 26 — µs From External to Internal Reference — 44 — µs From Internal to External Reference Power Supply Rejection PSRR — -57 — dB VDD = 5V ±10%, VREF = Internal Capacitive Load Stability CL — — 1000 pF RL = 5 kΩ No oscillation, Note 4 Slew Rate SR — 0.55 — Phase Margin pM — 66 — Short Circuit Current ISC — 15 24 mA VDD = 5V, All VOUT Pins = Grounded. Tested at room temperature. Short Circuit Current Duration TSC_DUR — Infinite — hours Note 4 DC Output Impedance (Note 4) ROUT Note 1: 2: 3: 4: 5: 6: 7: 8: 9: V/µs Degree CL = 400 pF, RL = ∞ (°) — 1 — Ω Normal mode — 1 — kΩ Power-Down mode 1 (PD1:PD0 = 0:1), VOUT to VSS — 100 — kΩ Power-Down mode 2 (PD1:PD0 = 1:0), VOUT to VSS — 500 — kΩ Power-Down mode 3 (PD1:PD0 = 1:1), VOUT to VSS All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. © 2010 Microchip Technology Inc. DS22187E-page 5 MCP4728 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = +2.7V to 5.5V, VSS = 0V, RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS. Parameter Symbol Min Typical Max Units Conditions — 45 — nV-s 1 LSB code change around major carry (from 7FFh to 800h) Dynamic Performance (Note 4) Major Code Transition Glitch Digital Feedthrough — <10 — nV-s Analog Crosstalk — <10 — nV-s DAC-to-DAC Crosstalk — <10 — nV-s Digital Interface Output Low Voltage VOL — — 0.4 V IOL = 3 mA SDA and RDY/BSY pins Schmitt Trigger Low Input Threshold Voltage VIL — — 0.3VDD V VDD > 2.7V. SDA, SCL, LDAC pins — — 0.2VDD V VDD ≤ 2.7V. SDA, SCL, LDAC pins Schmitt Trigger High Input Threshold Voltage VIH 0.7VDD — — V SDA, SCL, LDAC pins Input Leakage ILI — — ±1 µA SCL = SDA = LDAC = VDD, SCL = SDA = LDAC = VSS Pin Capacitance CPIN — — 3 pF Note 4 EEPROM EEPROM Write Time TWRITE Data Retention — 25 50 ms EEPROM write time — 200 — Years At +25°C, Note 3 210 — — ns LDAC Input LDAC Low Time Note 1: 2: 3: 4: 5: 6: 7: 8: 9: TLDAC Updates analog outputs (Note 3) All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0 x 000. The power-up ramp rate measures the rise of VDD over time. This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. Test code range: 100 - 4000 codes, VREF = VDD, VDD = 5.5V. Time delay to settle to a new reference when switching from external to internal reference or vice versa. This parameter is indirectly tested by Offset and Gain error testing. Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale. This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of VOUT. This time delay is not included in the output settling time specification. DS22187E-page 6 © 2010 Microchip Technology Inc. MCP4728 TFSCL TRSCL THIGH TSU:STA SCL TLOW SDA THD:STA TSP THD:DAT 0.7VDD 0.3VDD TAA TFSDA FIGURE 1-1: TSU:STO TBUF TSU:DAT TRSDA I2C Bus Timing Data. LDAC TLDAC 0.7VDD 0.3VDD VOUT (UDAC = 1) No Update FIGURE 1-2: Update LDAC Pin Timing vs. VOUT Update. © 2010 Microchip Technology Inc. DS22187E-page 7 MCP4728 I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125°C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters Clock Frequency Bus Capacitive Loading Start Condition Setup Time (Start, Repeated Start) Start Condition Hold Time Stop Condition Setup Time Clock High Time Clock Low Time Note 1: 2: 3: 4: 5: Sym Min Typ Max Units Conditions fSCL 0 — 100 kHz Standard Mode Cb = 400 pF, 2.7V – 5.5V 0 — 400 kHz Fast Mode Cb = 400 pF, 2.7V – 5.5V 0 — 1.7 MHz High Speed Mode 1.7 Cb = 400 pF, 4.5V – 5.5V 0 — 3.4 MHz High Speed Mode 3.4 Cb = 100 pF, 4.5V – 5.5V — — 400 pF Standard Mode 2.7V – 5.5V — — 400 pF Fast Mode 2.7V – 5.5V — — 400 pF High Speed Mode 1.7 4.5V – 5.5V — — 100 pF High Speed Mode 3.4 4.5V – 5.5V Cb TSU:STA THD:STA TSU:STO THIGH TLOW 4700 — ns Standard Mode 600 — — ns Fast Mode 160 — — ns High Speed Mode 1.7 160 — — ns High Speed Mode 3.4 4000 — ns Standard Mode 600 — — ns Fast Mode 160 — — ns High Speed Mode 1.7 160 — — ns High Speed Mode 3.4 4000 — ns Standard Mode 600 — — ns Fast Mode 160 — — ns High Speed Mode 1.7 160 — — ns High Speed Mode 3.4 4000 — — ns Standard Mode 600 — — ns Fast Mode 120 — — ns High Speed Mode 1.7 60 — — ns High Speed Mode 3.4 4700 — — ns Standard Mode 1300 — — ns Fast Mode 320 — — ns High Speed Mode 1.7 160 — — ns High Speed Mode 3.4 This parameter is ensured by characterization and is not 100% tested. After a Repeated Start condition or an Acknowledge bit. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). Time between Start and Stop conditions. DS22187E-page 8 © 2010 Microchip Technology Inc. MCP4728 I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125°C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters SCL Rise Time (Note 1) SDA Rise Time (Note 1) SCL Fall Time (Note 1) SDA Fall Time (Note 1) Data Input Setup Time Data Hold Time (Input, Output) (Note 3) Output Valid from Clock (Note 4) Note 1: 2: 3: 4: 5: Sym TRSCL TRSDA TFSCL TFSDA TSU:DAT THD:DAT TAA Min Typ Max Units Conditions — — 1000 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 80 ns High Speed Mode 1.7 20 — 160 ns High Speed Mode 1.7 (Note 2) 10 — 40 ns High Speed Mode 3.4 10 — 80 ns High Speed Mode 3.4 (Note 2) — — 1000 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 80 ns High Speed Mode 1.7 10 — 40 ns High Speed Mode 3.4 — — 300 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 80 ns High Speed Mode 1.7 10 — 40 ns High Speed Mode 3.4 — — 300 ns Standard Mode 20 + 0.1Cb — 300 ns Fast Mode 20 — 160 ns High Speed Mode 1.7 10 — 80 ns High Speed Mode 3.4 250 — — ns Standard Mode 100 — — ns Fast Mode 10 — — ns High Speed Mode 1.7 10 — — ns High Speed Mode 3.4 0 — 3450 ns Standard Mode 0 — 900 ns Fast Mode 0 — 150 ns High Speed Mode 1.7 0 — 70 ns High Speed Mode 3.4 0 — 3750 ns Standard Mode 0 — 1200 ns Fast Mode 0 — 310 ns High Speed Mode 1.7 0 — 150 ns High Speed Mode 3.4 This parameter is ensured by characterization and is not 100% tested. After a Repeated Start condition or an Acknowledge bit. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). Time between Start and Stop conditions. © 2010 Microchip Technology Inc. DS22187E-page 9 MCP4728 I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +125°C, VSS = 0V, Standard and Fast Mode: VDD = +2.7V to +5.5V High Speed Mode: VDD = +4.5V to +5.5V. Parameters Bus Free Time (Note 5) Sym Min Typ Max Units TBUF 4700 — — ns Standard Mode 1300 — — ns Fast Mode — — — ns High Speed Mode 1.7 — — — ns High Speed Mode 3.4 — — — ns Standard Mode (Not Applicable) — 50 — ns Fast Mode — 10 — ns High Speed Mode 1.7 — 10 — ns High Speed Mode 3.4 Input Filter Spike Suppression (SDA and SCL) (Not Tested) Note 1: 2: 3: 4: 5: TSP Conditions This parameter is ensured by characterization and is not 100% tested. After a Repeated Start condition or an Acknowledge bit. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. Data Input: This parameter must be longer than tSP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TFSDA (OR TRSDA). Time between Start and Stop conditions. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Symbol Min Typical Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C θJA — 202 — °C/W Conditions Temperature Ranges Thermal Package Resistances Thermal Resistance, 10L-MSOP DS22187E-page 10 © 2010 Microchip Technology Inc. MCP4728 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 6 0.3 VDD = 5.5V, VREF = Internal, Gain = x1 0 -2 0 -0.2 -6 0 1024 FIGURE 2-1: 2048 Code 3072 0 4096 INL vs. Code (TA = +25°C). 6 1024 FIGURE 2-4: 0.3 VDD = 5.5V, VREF = Internal, Gain = x2 4 2048 Code 3072 4096 DNL vs. Code (TA = +25°C). VDD = 5.5V, VREF = Internal, Gain = x2 0.2 2 DNL (LSB) INL (LSB) 0.1 -0.1 -4 0 -2 0.1 0 -0.1 -4 -0.2 -6 0 1024 2048 Code 3072 0 4096 INL vs. Code (TA = +25°C). FIGURE 2-2: 1024 2048 Code 2 0.1 DNL (LSB) 0.15 0 -2 4096 VDD = 5.5V, VREF = VDD VDD = 5.5V, VREF = VDD 4 3072 DNL vs. Code (TA = +25°C). FIGURE 2-5: 0.2 6 INL (LSB) VDD = 5.5V, VREF = Internal, Gain = x1 0.2 2 DNL(LSB) INL (LSB) 4 0.05 0 -0.05 -4 -6 -0.1 0 FIGURE 2-3: 1024 2048 Code 3072 4096 INL vs. Code (TA = +25°C). © 2010 Microchip Technology Inc. 0 FIGURE 2-6: 1024 2048 Code 3072 4096 DNL vs. Code (TA = +25°C). DS22187E-page 11 MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 0.4 VDD = 2.7V, VREF = Internal, Gain = x1 4 0.3 2 0.2 DNL (LSB) INL (LSB) 6 0 -2 0 -0.2 -6 0 1024 2048 Code FIGURE 2-7: 3072 0 4096 INL vs. Code (TA = +25°C). 6 4 0.3 2 0.2 -2 2048 Code 3072 4096 DNL vs. Code (TA = +25°C). 0.4 VDD = 2.7V, VREF = VDD 0 1024 FIGURE 2-10: DNL (LSB) INL (LSB) 0.1 -0.1 -4 VDD = 2.7V, VREF = VDD 0.1 0 -0.1 -4 -0.2 -6 0 1024 2048 Code 3072 6 0 4096 INL vs. Code (TA = +25°C). FIGURE 2-8: o -40 C 2 0.4 DNL(LSB) 0 -2 o +25 C -4 -6 o +125 C FIGURE 2-9: Temperature. DS22187E-page 12 4096 DNL vs. Code (TA = +25°C). VDD = 5.5V, VREF = Internal, Gain = x1 0.2 0.1 0 +125oC -0.2 1024 3072 -0.1 -10 0 2048 Code 0.3 +85°C -8 1024 FIGURE 2-11: VDD = 5.5V, VREF = Internal, Gain = x1 4 INL (LSB) VDD = 2.7V, VREF = Internal, Gain = x1 2048 Code 3072 INL vs. Code and 4096 0 FIGURE 2-12: Temperature. - 40oC to +85oC 1024 2048 Code 3072 4096 DNL vs. Code and © 2010 Microchip Technology Inc. MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 0.4 6 V DD = 5.5V, VREF = Internal, Gain = x2 4 o - 40 C o o +25 C +85 C 0.2 DNL (LSB) INL (LSB) 2 0 -2 -4 -8 0 -0.2 o +125 C -10 +125oC - 40oC to +85oC -0.3 0 1024 2048 Code FIGURE 2-13: Temperature. 3072 4096 0 0.5 VDD = 2.7V, VREF = Internal, Gain = x1 4 1024 FIGURE 2-16: Temperature. INL vs. Code and 6 2048 Code 3072 4096 DNL vs. Code and VDD = 2.7V, VREF = Internal, Gain = x1 0.4 0.3 DNL (LSB) 2 INL (LSB) 0.1 -0.1 -6 0 -2 - 40oC -4 o +25 C -6 +125 C 0 0 +125oC -0.3 1024 FIGURE 2-14: Temperature. 0.1 -0.2 o -10 0.2 -0.1 +85oC -8 2048 Code 3072 4096 INL vs. Code and 0 - 40oC to +85oC 1024 FIGURE 2-17: Temperature. 2048 Code 3072 4096 DNL vs. Code and 0.4 6 VDD = 5.5V, VREF = VDD VDD = 5.5V, VREF = VDD 0.3 4 +85oC 2 DNL (LSB) INL (LSB) VDD = 5.5V, VREF = Internal, Gain = x2 0.3 0 o - 40 C -2 -4 o +125 C 0.2 0.1 0 -0.1 o +25 C -6 +125oC - 40oC to +85oC -0.2 0 FIGURE 2-15: Temperature. 1024 2048 Code 3072 INL vs. Code and © 2010 Microchip Technology Inc. 4096 0 FIGURE 2-18: Temperature. 1024 2048 Code 3072 4096 DNL vs. Code and DS22187E-page 13 MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 0.5 6 VDD = 2.7V, VREF = V DD 4 - 40 oC +85 C 0.3 DNL (LSB) INL (LSB) 2 0 -2 o +125 C -4 0.1 0 -0.2 -8 0 1024 FIGURE 2-19: Temperature. 2048 Code 3072 4096 INL vs. Code and +125oC -0.3 0 - 40oC to +85oC 1024 FIGURE 2-22: Temperature. 2048 Code 3072 4096 DNL vs. Code and 6 -10 VDD = 2.7V, Gain = 1 -20 VDD = 5.5V, Gain = 1 -30 -40 5 Offset Error (mV) Full Scale Error (mV) 0.2 -0.1 +25oC -6 VDD = 5.5V, Gain = 2 4 3 VDD = 5.5V, Gain = 1 2 VDD = 2.7V, Gain = 1 1 VDD = 5.5V, Gain = 2 0 -50 -40 -25 -10 5 20 35 50 65 80 Temperature (oC) -40 -25 -10 95 110 125 FIGURE 2-20: Full Scale Error vs. Temperature (Code = FFFh, VREF = Internal). 5 20 35 50 65 80 o Temperature ( C) 95 110 125 FIGURE 2-23: Zero Scale Error vs. Temperature (Code = 000h, VREF = Internal). 4 50 VDD = 5.5V, Gain = 1 40 Offset Error (mV) Full Scale Error (mV) VDD = 2.7V, VREF = VDD 0.4 o 30 VDD = 2.7V, Gain = 1 20 3 VDD = 5.5V 2 VDD = 2.7V 1 0 10 -40 -25 -10 5 20 35 50 65 80 o Temperature ( C) 95 110 125 FIGURE 2-21: Full Scale Error vs. Temperature (Code = FFFh, VREF = VDD). DS22187E-page 14 -40 -25 -10 5 20 35 50 65 80 95 110 125 o Temperature ( C) FIGURE 2-24: Error). Offset Error (Zero Scale © 2010 Microchip Technology Inc. MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 16 VREF = Internal, Gain = x2 2 o Temp = +25 C 14 12 LSB VOUT (2V/Div) Ch. D 10 Ch. A 8 Ch. B 6 Ch. C 4 LDAC 2 Time (2 µs/Div) 0 0 500 FIGURE 2-25: (VDD = 5.5V). 1000 1500 2000 Codes 2500 3000 3500 Absolute DAC Output Error VOUT (2V/Div) LDAC Time (2 µs/Div) FIGURE 2-26: Full Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: 000h to FFFh). VOUT (2V/Div) LDAC Time (2 µs/Div) FIGURE 2-27: Half Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: 000h to 7FFh). © 2010 Microchip Technology Inc. FIGURE 2-28: Full Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Gain = x1, Code Change: 000h to FFFh). VOUT (2V/Div) LDAC Time (2 µs/Div) FIGURE 2-29: Full Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: FFFh to 000h). VOUT (2V/Div) LDAC Time (2 µs/Div) FIGURE 2-30: Half Scale Settling Time (VREF = VDD, VDD = 5V, UDAC = 1, Code Change: 7FFh to 000h). DS22187E-page 15 MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. Discharging Time due to VOUT (1V/Div) internal pull-down resistor (500 kΩ) VOUT (2V/Div) Time (2 µs/Div) LDAC Time (10 µs/Div) CLK FIGURE 2-31: Full Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Gain = x1, Code Change: FFFh to 000h). VOUT (1V/Div) Time (2 µs/Div) LDAC FIGURE 2-32: Half Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Gain = x1, Code Change: 000h to 7FFh). Last ACK CLK pulse FIGURE 2-34: Entering Power Down Mode (Code: FFFh, VREF = Internal, VDD = 5V, Gain = x1, PD1= PD0 = 1, No External Load). VOUT (1V/Div) Time (2 µs/Div) LDAC FIGURE 2-35: Half Scale Settling Time (VREF = Internal, VDD = 5V, UDAC = 1, Gain = x1, Code Change: 7FFh to 000h). VOUT (2V/Div) VOUT (1V/Div) TdExPD TdExPD Time (5 µs/Div) Time (5 µs/Div) CLK Last ACK CLK pulse FIGURE 2-33: Exiting Power Down Mode (Code: FFFh, VREF = Internal, VDD = 5V, Gain = x1, for all Channels.). DS22187E-page 16 CLK Last ACK CLK pulse FIGURE 2-36: Exiting Power Down Mode (Code: FFFh, VREF = VDD, VDD = 5V, for all Channels). © 2010 Microchip Technology Inc. MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. Discharging Time due to internal pull-down resistor (500 kΩ) VOUT at Channel D (5V/Div) VOUT (2V/Div) LDAC VOUT at Channel A (100 mV/Div) Time (5 µs/Div) Time (20 µs/Div) CLK Last ACK CLK pulse FIGURE 2-37: Entering Power Down Mode (Code: FFFh, VREF = VDD, VDD = 5V, PD1= PD0 = 1, No External Load). FIGURE 2-40: Channel Cross Talk (VREF = VDD, VDD = 5V). VOUT (2V/Div) VOUT (50 mV/Div) Time (10 µs/Div) Time (2 µs/Div) CLK Last ACK CLK pulse FIGURE 2-38: VOUT Time Delay when VREF changes from Internal Reference to VDD. FIGURE 2-41: Code Change Glitch (VREF = External, VDD = 5V, No External Load), Code Change: 800h to 7FFh. VOUT (2V/Div) VOUT (50 mV/Div) Time (2 µs/Div) Time (10 µs/Div) CLK Last ACK CLK pulse FIGURE 2-39: VOUT Time Delay when VREF changes from VDD to Internal Reference. © 2010 Microchip Technology Inc. FIGURE 2-42: Code Change Glitch (VREF = Internal, VDD = 5V, Gain = 1, No External Load), Code Change: 800h to 7FFh. DS22187E-page 17 MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 900 6 5 VDD = 5V VREF = VDD Code = FFFh 3 2 700 VDD = 4.5V VDD = 3.3V 600 VDD = 2.7V 1 500 0 0 1 2 3 Load Resistance (kΩ) FIGURE 2-43: -40 -25 -10 5 600 2 Channels On 400 200 35 50 65 80 95 110 125 VDD = 5.0V All Channels On 800 IDD_INT (µA) 3 Channels On 20 FIGURE 2-46: IDD vs. Temperature (VREF = VDD, All channels are in Normal Mode, Code = FFFh). All Channels On VDD = 5.0V 5 Temperature (oC) 1000 800 IDD_EXT (µA) 4 VOUT vs. Resistive Load. 1000 3 Channels On 600 2 Channels On 400 1 Channel On 200 1 Channel On 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 FIGURE 2-44: IDD vs. Temperature (VREF = VDD, VDD = 5V, Code = FFFh). 800 20 35 50 65 80 95 110 125 Temperature (oC) o Temperature ( C) FIGURE 2-47: IDD vs. Temperature (VREF = Internal, VREF = 5V, Code = FFFh). 1000 VDD = 2.7V V DD = 2.7V All Channels On 400 2 Channels On 200 IDD_INT (µA) 3 Channels On All Channels On 800 600 IDD_EXT (µA) VDD = 5.5V VDD = 5V 800 IDD_EXT (µA) VOUT (V) 4 All Channels On 3 Channels On 600 2 Channels On 400 1 Channel On 200 1 Channel On 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 o Temperature ( C) FIGURE 2-45: IDD vs. Temperature (VREF = VDD, VDD = 2.7V, Code = FFFh). DS22187E-page 18 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) FIGURE 2-48: IDD vs. Temperature (VREF = Internal, VDD = 2.7V, Code = FFFh). © 2010 Microchip Technology Inc. MCP4728 Note: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ, CL = 100 pF. 900 6 VDD = 5.5V All Channels On Code = FFFh 5 VDD = 5V VDD = 4.5V 700 VDD = 3.3V VOUT (V) IDD_INT (µA) 800 4 3 2 600 1 VDD = 2.7V 500 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 2 4 6 o Temperature ( C) FIGURE 2-49: IDD vs. Temperature (VREF = Internal , All Channels are in Normal Mode, Code = FFFh). 10 12 14 16 FIGURE 2-51: Source Current Capability (VREF = VDD, Code = FFFh). 6 60 Code = 000h All Channels Off 50 VDD = 5V 5 VDD = 5.5V VOUT (V) IDDP_INT (µA) 8 Current (mA) V DD = 4.5V 40 30 4 3 2 1 V DD = 3.3V VDD = 2.7V 0 20 -40 -25 -10 5 20 35 50 65 o Temperature ( C) 80 95 110 125 FIGURE 2-50: IDD vs. Temperature (VREF = Internal , All Channels are in Powered Down). © 2010 Microchip Technology Inc. 0 2 4 6 8 10 12 14 Sink Current (mA) FIGURE 2-52: Sink Current Capability (VREF = VDD, Code = 000h). DS22187E-page 19 MCP4728 NOTES: DS22187E-page 20 © 2010 Microchip Technology Inc. MCP4728 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. PIN FUNCTION TABLE Name Pin Type Function 1 VDD P Supply Voltage 2 SCL OI I2C Serial Clock Input (Note 1) 3 SDA OI/OO 4 LDAC ST This pin is used for two purposes: (a) Synchronization Input. It is used to transfer the contents of the DAC input registers to the output registers (VOUT). (b) Select the device for reading and writing I2C address bits. (Note 2) 5 RDY/BSY OO This pin is a status indicator of EEPROM programming activity. An external pull-up resistor (about 100 kΩ) is needed from RDY/BSY pin to VDD line. (Note 1) 6 VOUT A AO Buffered analog voltage output of channel A. The output amplifier has rail-to-rail operation. 7 VOUT B AO Buffered analog voltage output of channel B. The output amplifier has rail-to-rail operation. 8 VOUT C AO Buffered analog voltage output of channel C. The output amplifier has rail-to-rail operation. 9 VOUT D AO Buffered analog voltage output of channel D. The output amplifier has rail-to-rail operation. 10 VSS P Ground reference. I2C Serial Data Input and Output (Note 1) Legend: P = Power, OI = Open-Drain Input, OO = Open-Drain Output, ST = Schmitt Trigger Input Buffer, AO = Analog Output Note 1: This pin needs an external pull-up resistor from VDD line. Leave this pin float if it is not used. 2: This pin can be driven by MCU. 3.1 Supply Voltage Pins (VDD, VSS) VDD is the power supply pin for the device. The voltage at the VDD pin is used as a power supply input as well as a DAC external reference. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high-frequency noise present in application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application printed circuit board (PCB), it is highly recommended that the VSS pin be tied to the analog ground path, or isolated within an analog ground plane of the circuit board. © 2010 Microchip Technology Inc. 3.2 Serial Clock Pin (SCL) SCL is the serial clock pin of the I2C interface. The MCP4728 device acts only as a slave and the SCL pin accepts only external input serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock, and output from the MCP4728 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.0 “I2C Serial Interface Communications” for more details on I2C Serial Interface communication. Typical range of the pull-up resistor value for SCL and SDA is from 5 kΩ to 10 kΩ for Standard (100 kHz) and Fast (400 kHz) modes, and less than 1 kΩ for High Speed mode (3.4 MHz). DS22187E-page 21 MCP4728 3.3 Serial Data Pin (SDA) 3.5 SDA is the serial data pin of the I2C interface. The SDA pin is used to write or read the DAC register and EEPROM data. Except for Start and Stop conditions, the data on the SDA pin must be stable during the high duration of the clock pulse. The High or Low state of the SDA pin can only change when the clock signal on the SCL pin is Low. The SDA pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Refer to Section 5.0 “I2C Serial Interface Communications” for more details on the I2C Serial Interface communication. 3.4 LDAC Pin This pin can be driven by an external control device such as an MCU I/O pin. This pin is used to: a) b) transfer the contents of the input registers to their corresponding DAC output registers and select a device of interest when reading or writing I2C address bits. 2C address For more details on reading and writing the I bits, see Section 5.4.4 “General Call Read Address Bits” and Section 5.6.8 “Write Command: Write I2C Address bits (C2=0, C1=1, C0=1)”. RDY/BSY Status Indicator Pin This pin is a status indicator of EEPROM programming activity. This pin is “High” when the EEPROM has no programming activity, and “Low” when the EEPROM is in programming mode. It goes “High” when the EEPROM program is completed. The RDY/BSY pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor (about 100 kΩ) from the VDD line to the RDY/BSY pin. Let this pin float if it is not used. 3.6 Analog Output Voltage Pins (VOUT A, VOUT B, VOUT C, VOUT D) The device has four analog voltage output (VOUT) pins. Each output is driven by its own output buffer with a gain of 1 or 2, depending on the gain and VREF selection bit settings. In Normal mode, the DC impedance of the output pin is about 1Ω. In Power-Down mode, the output pin is internally connected to 1 kΩ, 100 kΩ, or 500 kΩ, depending on the Power-Down selection bit settings. The VOUT pin can drive up to 1000 pF of capacitive load. It is recommended to use a load with RL greater than 5 kΩ. When the logic status of the LDAC pin changes from “High” to “Low”, the contents of all input registers (Channels A – D) are transferred to their corresponding output registers, and all analog voltage outputs are updated simultaneously. If this pin is permanently tied to “Low”, the content of the input register is transferred to its output register (VOUT) immediately at the last input data byte’s acknowledge pulse. The user can also use the UDAC bit instead. However, the UDAC bit updates a selected channel only. See Section 4.8 “Output Voltage Update” for more information on the LDAC pin and UDAC bit functions. DS22187E-page 22 © 2010 Microchip Technology Inc. MCP4728 4.0 THEORY OF DEVICE OPERATION 4.2 Reset Conditions The device can be reset by two independent events: The MCP4728 device is a 12-bit 4-channel buffered voltage output DAC with nonvolatile memory (EEPROM). The user can program the EEPROM with I2C address bits, configuration and DAC input data of each channel. The device has an internal charge pump circuit to provide the programming voltage of the EEPROM. a) b) When the device is first powered-up, it automatically loads the stored data in its EEPROM to the DAC input and output registers, and provides analog outputs with the saved settings immediately. This event does not require an LDAC or UDAC bit condition. After the device is powered-up, the user can update the input registers using I2C write commands. The analog outputs can be updated with new register values if the LDAC pin or UDAC bit is low. The DAC output of each channel is buffered with a low power and precision output amplifier. This amplifier provides a rail-to-rail output with low offset voltage and low noise. The factory default settings for the EEPROM prior to the device shipment are shown in Table 4-2. The device uses a resistor string architecture. The resistor ladder DAC can be driven from VDD or internal VREF, depending on the reference selection. The user can select internal (2.048V) or external reference (VDD) for each DAC channel individually by software control. The VDD is used as the external reference. Each channel is controlled