Datasheet · 2024

ST LSM6DSO 6-Axis IMU — Datasheet (DS12140)

Alternative 6-axis IMU compared in the dive.

Author: STMicroelectronics
Year: 2024
Type: Datasheet
Credit: STMicroelectronics (st.com)

imu
gyroscope
accelerometer

LSM6DSO Datasheet 6-axis IMU (inertial measurement unit): always-on 3‑axis accelerometer and 3‑axis gyroscope Features • • • • • • • • • • Product status link LSM6DSO Product summary Order code LSM6DSO LSM6DSOTR Temp. range [°C] -40 to +85 Package LGA-14L (2.5 x 3 x 0.83 mm) Packing Tray Tape and reel Product resources AN5192 (device application note) AN5226 (finite state machine) TN0018 (design and soldering) Product label • • • • • • • Supply current: 0.55 mA in combo high-performance mode “Always-on" experience with low power consumption for both accelerometer and gyroscope Smart FIFO up to 9 KB Android compliant ±2/±4/±8/±16 g full scale ±125/±250/±500/±1000/±2000 dps full scale Analog supply voltage: 1.71 V to 3.6 V Independent IO supply (1.62 V) Compact footprint: 2.5 mm x 3 mm x 0.83 mm SPI / I²C & MIPI I3CSM serial interface with main processor data synchronization Auxiliary SPI for OIS data output for gyroscope and accelerometer Advanced pedometer, step detector and step counter Significant motion detection, tilt detection Standard interrupts: free-fall, wake-up, 6D/4D orientation, click and doubleclick Programmable finite state machine: accelerometer, gyroscope, and external sensors Embedded temperature sensor ECOPACK and RoHS compliant Applications • • • • • • • Motion tracking and gesture detection Sensor hub Indoor navigation IoT and connected devices Smart power saving for handheld devices EIS and OIS for camera applications Vibration monitoring and compensation Description The LSM6DSO is a 6-axis IMU (inertial measurement unit) system-in-package featuring a 3-axis digital accelerometer and a 3-axis digital gyroscope, boosting performance at 0.55 mA in high-performance mode and enabling always-on lowpower features for an optimal motion experience for the consumer. DS12140 - Rev 3 - June 2024 For further information contact your local STMicroelectronics sales office. www.st.com LSM6DSO The LSM6DSO supports the main OS requirements, offering real, virtual, and batch sensors with 9 KB for dynamic data batching. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit that is trimmed to better match the characteristics of the sensing element. The LSM6DSO has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000 dps. The LSM6DSO fully supports EIS and OIS applications as the module includes a dedicated configurable signal processing path for OIS and an auxiliary SPI, configurable for both the gyroscope and accelerometer. High robustness to mechanical shock makes the LSM6DSO the preferred choice of system designers for the creation and manufacturing of reliable products. The LSM6DSO is available in a plastic, land grid array (LGA) package. DS12140 - Rev 3 page 2/162 LSM6DSO Overview 1 Overview The LSM6DSO is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The LSM6DSO delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode. The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, stationary/motion detection and wake-up events. The LSM6DSO supports the main OS requirements, offering real, virtual, and batch mode sensors. In addition, the LSM6DSO can efficiently run the sensor-related features specified in Android, saving power and enabling faster reaction time. In particular, the LSM6DSO has been designed to implement hardware features such as significant motion detection, stationary/motion detection, tilt, pedometer functions, timestamping and to support the data acquisition of an external magnetometer. The LSM6DSO offers hardware flexibility to connect the pins with different mode connections to external sensors to expand functionalities such as adding a sensor hub, auxiliary SPI, and so forth. Up to 9 KB of FIFO with compression and dynamic allocation of significant data (that is, external sensors, timestamp, etc.) allows overall power saving of the system. Like the entire portfolio of MEMS sensor modules, the LSM6DSO leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit that is trimmed to better match the characteristics of the sensing element. The LSM6DSO is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address ultra-compact solutions. DS12140 - Rev 3 page 3/162 LSM6DSO Embedded low-power features 2 Embedded low-power features The LSM6DSO has been designed to be fully compliant with Android, featuring the following on-chip functions: • 9 KB data buffering, data can be compressed two or three times – – • Event-detection interrupts (fully configurable) • – Free-fall – Wake-up – 6D orientation – Click and double-click sensing – Activity/inactivity recognition – Stationary/motion detection Specific IP blocks with negligible power consumption and high-performance • – Pedometer functions: step detector and step counters – Tilt – Significant motion detection – Finite state machine (FSM) for accelerometer, gyroscope, and external sensors Sensor hub – 2.1 100% efficiency with flexible configurations and partitioning Possibility to store timestamp Up to six total sensors: two internal (accelerometer and gyroscope) and four external sensors Tilt detection The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve targets of both ultralow power consumption and robustness during the short duration of dynamic accelerations. The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with different scenarios, for example: 1. Triggers when the phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting 2. Does not trigger when the phone is in a front pants pocket and the user is walking, running, or going upstairs 2.2 Significant motion detection The significant motion detection (SMD) function generates an interrupt when a ‘significant motion’, that could be due to a change in user location, is detected. In the LSM6DSO device, this function has been implemented in the hardware using only the accelerometer. SMD functionality can be used in location-based applications in order to receive a notification indicating when the user is changing location. 2.3 Finite state machine The LSM6DSO can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection such as glance gestures, absolute wrist tilt, shake and double-shake detection. Definition of finite state machine A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. Figure 1. Generic state machine shows a generic state machine. DS12140 - Rev 3 page 4/162 LSM6DSO Embedded low-power features Figure 1. Generic state machine Finite state machine in the LSM6DSO The LSM6DSO works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the sensor hub feature (mode 2). These data can be used as input for up to 16 programs in the embedded finite state machine (Figure 2. State machine in the LSM6DSO). All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed. Figure 2. State machine in the LSM6DSO DS12140 - Rev 3 page 5/162 LSM6DSO Pin description 3 Pin description Figure 3. Pin connections DS12140 - Rev 3 page 6/162 LSM6DSO Pin description 3.1 Pin connections The LSM6DSO offers flexibility to connect the pins in order to have four different mode connections and functionalities. In detail: • Mode 1: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available. • Mode 2: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface and I²C master interface for external sensor connections are available. • Mode 3: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the gyroscope ONLY. • Mode 4: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the accelerometer and gyroscope. Figure 4. LSM6DSO connection modes Mode 1 Mode 2 Mode 3 Mode 4 HOST HOST HOST HOST I 2C / SM MIPI I3C / SPI (3/4-w) LSM6DSO I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSO Master I2C LSM6DSM External LSM6DSM sensors DS12140 - Rev 3 I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSO Aux SPI (3/4-w) For gyro data only Camera module I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSO Aux SPI (3/4-w) For XL and gyro data Camera module page 7/162 LSM6DSO Pin description In the following table, each mode is described for the pin connections and function. Table 1. Pin description Pin # Name Mode 1 function Mode 2 function Mode 3 / mode 4 function SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) 1 SDO/SA0 2 SDx Connect to VDDIO or GND I²C master serial data (MSDA) Auxiliary SPI 3/4-wire interface serial data input (SDI_Aux) and SPI 3-wire serial data output (SDO_Aux) 3 SCx Connect to VDDIO or GND I²C master serial clock (MSCL) Auxiliary SPI 3/4-wire interface serial port clock (SPC_Aux) 4 INT1 Programmable interrupt in I²C and SPI 5 VDDIO(1) Power supply for I/O pins 6 GND 0 V supply 7 GND 0 V supply 8 VDD(1) Power supply 9 INT2 Programmable interrupt 2 (INT2) / Data enabled (DEN) Programmable interrupt 2 (INT2)/ Data enabled (DEN)/I²C master external synchronization signal (MDRDY) Programmable interrupt 2 (INT2) / Data enabled (DEN) Enable auxiliary SPI 3/4-wire interface 10 OCS_Aux Leave unconnected(2) Leave unconnected(2) 11 Connect to VDDIO or leave SDO_Aux unconnected(2) Connect to VDDIO or leave unconnected(2) 12 13 CS SCL I²C/MIPI I3CSM/SPI mode selection (1: SPI idle mode / I²C/MIPI I3CSM communication enabled; (1: SPI idle mode / I²C/MIPI I3CSM communication enabled; 0: SPI communication mode / I²C/MIPI I3CSM disabled) 0: SPI communication mode / I²C/ 0: SPI communication mode / I²C/ MIPI I3CSM disabled) MIPI I3CSM disabled) I²C/MIPI I3CSM serial clock (SCL) I²C/MIPI I3CSM serial clock (SCL) I²C/MIPI I3CSM serial clock (SCL) SPI serial port clock (SPC) SPI serial port clock (SPC) I²C/MIPI I3CSM serial data (SDA) I²C/MIPI I3CSM serial data (SDA) SPI serial data input (SDI) SPI serial data input (SDI) 3-wire interface serial data output (SDO) 3-wire interface serial data I²C/MIPI I3CSM serial data (SDA) SDA Auxiliary SPI 4-wire interface: serial data output (SDO_Aux) I²C/MIPI I3CSM/SPI mode selection SPI serial port clock (SPC) 14 Auxiliary SPI 3-wire interface: leave unconnected(2) SPI serial data input (SDI) 3-wire interface serial data output (SDO) I²C/MIPI I3CSM/SPI mode selection (1: SPI idle mode / I²C/MIPI I3CSM communication enabled; output (SDO) 1. Recommended 100 nF filter capacitor. 2. Leave pin electrically unconnected and soldered to PCB. DS12140 - Rev 3 page 8/162 LSM6DSO Module specifications 4 Module specifications 4.1 Mechanical characteristics @VDD = 1.8 V, T = 25°C, unless otherwise noted. Table 2. Mechanical characteristics Symbol Parameter Test conditions Min. Typ.(1) Max. Unit ±2 LA_FS ±4 Linear acceleration measurement range ±8 g ±16 ±125 ±250 G_FS Angular rate measurement range ±500 dps ±1000 ±2000 LA_So G_So Linear acceleration sensitivity(2) Angular rate sensitivity(2) FS = ±2 g 0.061 FS = ±4 g 0.122 FS = ±8 g 0.244 FS = ±16 g 0.488 FS = ±125 dps 4.375 FS = ±250 dps 8.75 FS = ±500 dps 17.50 FS = ±1000 dps 35 FS = ±2000 dps 70 mg/LSB mdps/LSB G_So% Sensitivity tolerance(3) at component level ±1 % LA_SoDr Linear acceleration sensitivity change vs. temperature(4) from -40° to +85° ±0.01 %/°C G_SoDr Angular rate sensitivity change vs. temperature(4) from -40° to +85° ±0.007 %/°C LA_TyOff Linear acceleration zero-g level offset accuracy(5) ±20 mg G_TyOff Angular rate zero-rate level(5) ±1 dps LA_OffDr Linear acceleration zero-g level change vs. temperature(4) ±0.1 mg/°C G_OffDr Angular rate typical zero-rate level change vs. temperature(4) ±0.010 dps/°C Rate noise density in high-performance mode(6) 3.8 mdps/√Hz Gyroscope RMS noise in normal/low-power mode(7) 75 mdps Rn RnRMS An RMS Acceleration noise density in high-performance mode(8) Acceleration RMS noise in normal/low-power mode(9)(10) DS12140 - Rev 3 FS = ±2 g 70 FS = ±4 g 75 FS = ±8 g 80 FS = ±16 g 110 FS = ±2 g 1.8 FS = ±4 g 2.0 FS = ±8 g 2.4 µg/√Hz mg(RMS) page 9/162 LSM6DSO Module specifications Symbol RMS Parameter Test conditions Min. Typ.(1) Acceleration RMS noise in normal/low-power mode(9)(10) FS = ±16 g 3.0 Acceleration RMS noise in ultralow-power mode(9)(10) FS = ±2 g 5.5 Max. Unit mg(RMS) 1.6(11) 12.5 26 52 104 LA_ODR Linear acceleration output data rate 208 416 833 1666 3332 6664 Hz 12.5 26 52 104 G_ODR 208 Angular rate output data rate 416 833 1666 3332 6664 Linear acceleration self-test output change(12)(13)(14) Vst Top Angular rate self-test output change(15)(16) 50 1700 mg FS = ±250 dps 20 80 dps FS = ±2000 dps 150 700 dps -40 +85 °C Operating temperature range 1. Typical specifications are not guaranteed. 2. Sensitivity values after factory calibration test and trimming. 3. Subject to change. 4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production. 5. Values after factory calibration test and trimming. 6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting. 7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting. 8. Accelerometer noise density in high-performance mode is independent of the ODR. 9. Accelerometer RMS noise in normal/low-power/ultralow-power mode is independent of the ODR. 10. Noise RMS related to BW = ODR/2. 11. This ODR is available when the accelerometer is in low-power mode. 12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes. 13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale. 14. Accelerometer self-test limits are full-scale independent. 15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes. 16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale. DS12140 - Rev 3 page 10/162 LSM6DSO Module specifications 4.2 Electrical characteristics @VDD = 1.8 V, T = 25°C, unless otherwise noted. Table 3. Electrical characteristics Symbol Parameter Test conditions Min. Typ.(1) Max. Unit 1.8 3.6 V 3.6 V VDD Supply voltage 1.71 VDDIO Power supply for I/O 1.62 IddHP Gyroscope and accelerometer supply current in high-performance mode 0.55 mA LA_IddHP Accelerometer supply current in high-performance mode 170 µA LA_IddLP Accelerometer supply current in low-power mode LA_IddULP Accelerometer supply current in ultralow-power mode ODR = 52 Hz 26 ODR = 1.6 Hz 4.5 ODR = 52 Hz 9.5 ODR = 1.6 Hz 4.4 µA µA IddPD Gyroscope and accelerometer supply current during power-down 3 µA Ton Turn-on time 35 ms VIH Digital high-level input voltage VIL Digital low-level input voltage VOH High-level output voltage IOH = 4 mA(2) VOL Low-level output voltage IOL = 4 mA(2) Top Operating temperature range 0.7 * VDDIO V 0.3 * VDDIO V VDDIO 0.2 V -40 0.2 V +85 °C 1. Typical specifications are not guaranteed. 2. 4 mA is the maximum driving capability, that is, the maximum DC current that can be sourced/sunk by the digital pin in order to guarantee the correct digital output voltage levels VOH and VOL. 4.3 Temperature sensor characteristics @VDD = 1.8 V, T = 25°C unless otherwise noted. Table 4. Temperature sensor characteristics Symbol TODR(2) Parameter Test condition Min. Temperature refresh rate Toff Temperature offset(3) TSen Temperature sensitivity TST Temperature stabilization time(4) T_ADC_res Temperature ADC resolution Top Operating temperature range Typ.(1) Max. 52 -15 Hz +15 256 °C LSB/°C 500 16 -40 Unit µs bit +85 °C 1. Typical specifications are not guaranteed. 2. When the accelerometer is in low-power mode or ultra-low-power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR. 3. The output of the temperature sensor is 0 LSB (typ.) at 25°C. 4. Time from power ON to valid data based on characterization data. DS12140 - Rev 3 page 11/162 LSM6DSO Module specifications 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for VDD and Top. Table 5. SPI slave timing values (in mode 3) Symbol Parameter Value(1) Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time 5 th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) SDO output disable time Max Unit ns 100 10 MHz ns 50 5 50 1. Values are evaluated at 10 MHz clock frequency for SPI with both 3 and 4 wires, based on characterization results, not tested in production. Figure 5. SPI slave timing diagram (in mode 3) Note: DS12140 - Rev 3 Measurement points are done at 0.3·VDDIO and 0.7·VDDIO for both input and output ports. page 12/162 LSM6DSO Module specifications 4.4.2 I²C - inter-IC control interface Subject to general operating conditions for VDD and Top. Table 6. I²C slave timing values Symbol I²C standard mode(1) Parameter I²C fast mode (1) Min Max Min Max 100 0 400 f(SCL) SCL clock frequency 0 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 th(ST) START condition hold time 4 0.6 tsu(SR) Repeated START condition setup time 4.7 0.6 tsu(SP) STOP condition setup time 4 0.6 tw(SP:SR) Bus free time between STOP and START condition 4.7 1.3 3.45 Unit kHz µs ns 0 0.9 µs µs 1. Data based on standard I²C protocol requirement, not tested in production. Figure 6. I²C slave timing diagram REPEATED START START tsu(SR) tw(SP:SR) SDA tsu(SDA) START th(SDA) tsu(SP) STOP SCL th(ST) Note: DS12140 - Rev 3 tw(SCLL) tw(SCLH) Measurement points are done at 0.3·VDDIO and 0.7·VDDIO for both ports. page 13/162 LSM6DSO Module specifications 4.5 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Note: Ratings Maximum value Unit VDD Supply voltage -0.3 to +4.8 V TSTG Storage temperature range -40 to +125 °C Sg Acceleration g for 0.2 ms 20,000 g ESD Electrostatic discharge protection (HBM) 2 kV Vin Input voltage on any control pin (including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) -0.3 to VDDIO +0.3 V Supply voltage on any pin should never exceed 4.8 V. This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. DS12140 - Rev 3 page 14/162 LSM6DSO Module specifications 4.6 Terminology 4.6.1 Sensitivity Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky), and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors (see Table 2). An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see Table 2). 4.6.2 Zero-g and zero-rate level Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0 g on both the X-axis and Y-axis, whereas the Z-axis measures 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 2. Mechanical characteristics. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see Table 2. Mechanical characteristics). DS12140 - Rev 3 page 15/162 LSM6DSO Digital interfaces 5 Digital interfaces 5.1 I²C/SPI interface The registers embedded inside the LSM6DSO may be accessed through both the I²C and SPI serial interfaces. The latter may be software configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3. The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (that is, connected to VDDIO). Table 8. Serial interface pin description Pin name Pin description Enable SPI CS I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled; 0: SPI communication mode / I²C disabled) I²C serial clock (SCL) SCL/SPC SPI serial port clock (SPC) I²C serial data (SDA) SDA/SDI/SDO SPI serial data input (SDI) 3-wire interface serial data output (SDO) SDO/SA0 5.1.1 SPI serial data output (SDO) I²C less significant bit of the device address I²C serial interface The LSM6DSO I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back. The relevant I²C terminology is provided in the table below. Table 9. I²C terminology Term Description Transmitter The device that sends data to the bus Receiver The device that receives data from the bus Master The device that initiates a transfer, generates clock signals, and terminates a transfer Slave The device addressed by the master There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to VDDIO through external pull-up resistors. When the bus is free, both the lines are high. The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the standard mode. In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h). I²C operation The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. DS12140 - Rev 3 page 16/162 LSM6DSO Digital interfaces The slave address (SAD) associated to the LSM6DSO is 110101x. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is 1 (address 1101011); else if the SDO/SA0 pin is connected to ground, the LSb value is 0 (address 1101010b). This solution permits connecting and addressing two different inertial modules to the same I²C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver that has been addressed is obliged to generate an acknowledge after each byte of data received. The I²C embedded inside the LSM6DSO behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit subaddress (SUB) is transmitted. The increment of the address is configured by the CTRL3_C (12h) (IF_INC). The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must be issued after the two subaddress bytes; if the bit is 0 (write) the master transmits to the slave with direction unchanged. Table 10 explains how the SAD+read/write bit pattern is composed, listing all the possible configurations. Table 10. SAD+read/write patterns Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W Read 110101 0 1 11010101 (D5h) Write 110101 0 0 11010100 (D4h) Read 110101 1 1 11010111 (D7h) Write 110101 1 0 11010110 (D6h) Table 11. Transfer when master is writing one byte to slave Master ST SAD + W SUB Slave DATA SAK SP SAK SAK Table 12. Transfer when master is writing multiple bytes to slave Master ST SAD + W SUB Slave DATA SAK DATA SAK SP SAK SAK Table 13. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave SUB SR SAK SAD + R SAK NMAK SAK SP DATA Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave Master ST Slave SAD+ W SUB SAK SR SAK SAD+ R MAK SAK DATA MAK DATA NMAK SP DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver does not acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by the generation of a stop (SP) condition. In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge. DS12140 - Rev 3 page 17/162 LSM6DSO Digital interfaces 5.1.2 SPI bus interface The LSM6DSO SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface communicates with the application using four wires: CS, SPC, SDI, and SDO. Figure 7. Read and write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS enables the serial port and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods are added. When the CTRL3_C (12h) (IF_INC) bit is 0, the address used to read/write data remains the same for every block. When the CTRL3_C (12h) (IF_INC) bit is 1, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. DS12140 - Rev 3 page 18/162 LSM6DSO Digital interfaces 5.1.2.1 SPI read Figure 8. SPI read protocol (in mode 3) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). bit 16-...: data DO(...-8). Further data in multiple byte reads. Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8 DS12140 - Rev 3 page 19/162 LSM6DSO Digital interfaces 5.1.2.2 SPI write Figure 10. SPI write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writes. Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 DS12140 - Rev 3 page 20/162 LSM6DSO Digital interfaces 5.1.2.3 SPI read in 3-wire mode A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to 1 (SPI serial interface mode selection). Figure 12. SPI read protocol in 3-wire mode (in mode 3) CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. DS12140 - Rev 3 page 21/162 LSM6DSO Digital interfaces 5.2 MIPI I3CSM interface 5.2.1 MIPI I3CSM slave interface The LSM6DSO interface includes a MIPI I3CSM SDR only slave interface (compliant with release 1.0 of the specification) with MIPI I3CSM SDR embedded features: • • • • • • • • Note: DS12140 - Rev 3 CCC command Direct CCC communication (SET and GET) Broadcast CCC communication Private communications Private read and write for single byte Multiple read and write In-band interrupt request Error detection and recovery methods (S0-S6) Refer to Section 5.3: I²C/MIPI I3CSM coexistence in LSM6DSO for details regarding the choice of the interface when powering up the device. page 22/162 LSM6DSO Digital interfaces 5.2.2 MIPI I3CSM CCC supported commands The list of MIPI I3CSM CCC commands supported by the device is detailed in the following table. Table 15. MIPI I3CSM CCC commands Command Command code Default Description ENTDAA 0x07 DAA procedure SETDASA 0x87 Assign dynamic address using static address 0x6B/0x6A depending on SDO pin ENEC 0x80 / 0x00 Slave activity control (direct and broadcast) DISEC 0x81/ 0x01 Slave activity control (direct and broadcast) ENTAS0 0x82 / 0x02 Enter activity state (direct and broadcast) ENTAS1 0x83 / 0x03 Enter activity state (direct and broadcast) ENTAS2 0x84 / 0x04 Enter activity state (direct and broadcast) ENTAS3 0x85 / 0x05 Enter activity state (direct and broadcast) SETXTIME 0x98 / 0x28 Timing information exchange 0x07 GETXTIME 0x99 0x00 0x05 Timing information exchange 0x92 RSTDAA 0x86 / 0x06 Reset the assigned dynamic address (direct and broadcast) SETMWL 0x89 / 0x08 Define maximum write length during private write (direct and broadcast) SETMRL 0x8A / 0x09 Define maximum read length during private read (direct and broadcast) SETNEWDA 0x88 GETMWL 0x8B Change dynamic address 0x00 0x08 Get maximum write length during private write (2 byte) 0x00 GETMRL 0x8C 0x10 0x09 Get maximum read length during private read (3 byte) 0x02 0x08 GETPID 0x8D 0x00 0x6C Device ID register 0x10 0x0B GETBCR 0x8E GETDCR 0x8F GETSTATUS 0x90 0x07 (1 byte) 0x44 default Bus characteristics register MIPI I3CSM device characteristics register 0x00 0x00 Status register (2 byte) 0x00 GETMXDS 0x94 0x20 Return max data speed (2 byte) DS12140 - Rev 3 page 23/162 LSM6DSO Digital interfaces 5.3 I²C/MIPI I3CSM coexistence in LSM6DSO In the LSM6DSO, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires antispike filters on the SDA and SCL pins that are not compatible with I3C timing. The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up: • • INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 13 INT1 pin connected to VDDIO: only I3C active, see Figure 14 Figure 13. I²C and I3C both active (INT1 pin not connected) INT1 pin not connected I²C/I3C both active I²C/I3C (both active) I3C bus case I²C bus case Master sends I²C R/W Slave performs requested R/W Master assigns DA to the slave (1) Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery 1. Address assignment (DAA or ENTDA) must be performed with I²C fast mode plus timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications. Figure 14. Only I3C active (INT1 pin connected to VDDIO) INT1 pin connected to VDDIO Only I3C active I²C/I3C I3C bus case Dynamic Address Assignment (1) Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery 1. When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using MIPI I3CSM SDR timing. DS12140 - Rev 3 page 24/162 LSM6DSO Digital interfaces 5.4 Master I²C interface If the LSM6DSO is configured in mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins. Table 16. Master I²C pin details Pin name 5.5 Pin description MSCL I²C serial clock master MSDA I²C serial data master MDRDY I²C master external synchronization signal Auxiliary SPI interface If the LSM6DSO is configured in mode 3 or mode 4, the auxiliary SPI is available. The auxiliary SPI interface is mapped to the following dedicated pins. Table 17. Auxiliary SPI pin details Pin name OCS_Aux Pin description Auxiliary SPI 3/4-wire enable SDx Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux) SCx Auxiliary SPI 3/4-wire interface serial port clock SDO_Aux Auxiliary SPI 4-wire data output (SDO_Aux) When the LSM6DSO is configured in mode 3 or mode 4, the auxiliary SPI can be connected to a camera module for OIS/EIS support. In this configuration, the auxiliary SPI can write only to the dedicated registers INT_OIS (6Fh), CTRL1_OIS (70h), CTRL2_OIS (71h), CTRL3_OIS (72h). All the registers are accessible in read mode from both the primary interface and auxiliary SPI. Mode 3 is enabled when the OIS_EN_SPI2 bit in the CTRL1_OIS (70h) register is set to 1. M