Datasheet · 2019

TI LM66100 5.5-V 1.5-A Ideal Diode with Input Polarity Protection — Datasheet (SLVSEZ8A)

Ideal-diode ORing (WP-8).

Author: Texas Instruments
Year: 2019
Type: Datasheet
Credit: Texas Instruments (ti.com)

ideal diode
oring

Product Folder Order Now Tools & Software Technical Documents Support & Community LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 LM66100 5.5-V, 1.5-A 79-mΩ, Low IQ Ideal Diode With Input Polarity Protection 1 Features • • 1 • • • • • Wide operating voltage range: 1.5 V – 5.5 V Reverse voltage standoff on VIN: –6-V absolute maximum Maximum continuous current (IMAX): 1.5 A On-Resistance (RON): – 5-V VIN = 79-mΩ (typical) – 3.6-V VIN = 91-mΩ (typical) – 1.8-V VIN = 141-mΩ (typical) Comparator chip enable (CE) Channel status indication (ST) Low current consumption: – 3.6-V VIN Shutdown current (ISD,VIN): 120-nA (typical) – 3.6-V VIN Quiescent current (IQ, VIN): 150-nA (typical) The chip enable works by comparing the CE pin voltage to the input voltage. When the CE pin voltage is higher than VIN, the device is disabled and the MOSFET is off. When the CE pin voltage is lower, the MOSFET is on. The LM66100 also comes with reverse polarity protection (RPP) that can protect the device from a miswired input, such as a reversed battery. Two LM66100 devices can be used in an ORing configuration similar to a dual diode ORing implementation. In this configuration, the devices pass the highest input voltage to the output while blocking reverse current flow into the input supplies. These devices can compare input and output voltages to make sure that reverse current is blocked through an internal voltage comparator. The LM66100 is available in a standard SC-70 package characterized for operation over a junction temperature range of –40°C to 125°C. Device Information(1) 2 Applications • • • • Smart meters Building automation GPS and tracking Primary and backup batteries PART NUMBER LM66100 PACKAGE SC-70 (6) BODY SIZE (NOM) 2.1 mm x 2.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application 3 Description The LM66100 is a Single-Input, Single-Output (SISO) integrated ideal diode that is well suited for a variety of applications. The device contains a P-channel MOSFET that can operate over an input voltage range of 1.5 V to 5.5 V and can support a maximum continuous current of 1.5 A. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications......................................................... 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 8 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Switching Characteristics .......................................... 5 Typical Characteristics .............................................. 6 Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 9 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 10 9.1 Application Information............................................ 10 9.2 Typical Applications ................................................ 10 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 14 11.1 Layout Guidelines ................................................. 14 11.2 Layout Example .................................................... 14 12 Device and Documentation Support ................. 15 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates 15 Community Resources.......................................... 15 Trademarks ........................................................... 15 Electrostatic Discharge Caution ............................ 15 Glossary ................................................................ 15 13 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History Changes from Original (March 2019) to Revision A • 2 Page Changed from Advance Information to Production Data ....................................................................................................... 1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 5 Pin Configuration and Functions DCK Package 6-Pin SC-70 Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 VIN I Device input 2 GND - Device ground 3 CE I Active-low chip enable. Can be connected to VOUT for reverse current protection. Do not leave floating. 4 N/C - Not internally connected, can be tied to GND or left floating. 5 ST O Active-low open-drain output, pulled low when the chip is disabled. Hi-Z when the chip is enabled. Connect to GND if not required. 6 VOUT O Device output Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 3 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VIN Maximum Input Voltage Range –6 6 V VOUT Maximum Output Voltage Range –0.3 6 V VCE Maximum CE Pin Voltage –0.3 6 V VST Maximum ST Pin Voltage –0.3 6 V ISW, MAX Maximum Continuous Switch Current 1.5 A ISW, PLS Maximum Pulsed Switch Current (≤120 ms, 2% Duty Cycle) 2.5 A ID, PLS Maximum Pulsed Body Diode Current (≤0.1 ms, 0.2% Duty Cycle) 2.5 A ICE Maximum CE Pin Current –1 IST Maximum ST Pin Current –1 TJ Junction temperature –40 125 °C TSTG Storage temperature –65 150 °C TLEAD Maximum Lead Temperature (10 s soldering time) 300 °C (1) UNIT mA mA Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, allpins (1) ±2000 Charged device model (CDM), per JEDEC specificationJESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less is possible with the necessary precautions. Pins listed may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MAX UNIT VIN Input Voltage Range MIN 1.5 TYP 5.5 V VOUT Output Voltage Range 1 5.5 V VCE CE Pin Voltage Range 0 5.5 V VST ST Pin Voltage Range 0 5.5 V 6.4 Thermal Information LM66100 THERMAL METRIC (1) DCK (SC-70) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 192 °C/W RθJC(top) Junction-to-case (top) thermal resistance 124 °C/W RθJB Junction-to-board thermal resistance 52 °C/W ΨJT Junction-to-top characterization parameter 34 °C/W ΨJB Junction-to-board characterization parameter 52 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 6.5 Electrical Characteristics Typical values are at 25°C with an input voltage of 3.6V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Supply (VIN) VIN Shutdown Current VOUT = VIN VCE > VIN + 80mV IOUT = 0 A (VOUT = open) 25°C ISD,VIN VIN Quiescent Current VOUT = VIN VCE < VIN - 250mV IOUT = 0 A (VOUT = open) 25°C IQ,VIN 0.12 -40°C to 105°C 0.15 -40°C to 105°C 25°C IOUT, OFF OUT to IN Leakage Current (Current out of VIN) µA 0.3 µA 0.3 µA 0.3 µA 0.5 µA -40°C to 85°C 2.7 µA -40°C to 105°C 8 µA VOUT - VIN ≤ 4.5 V VCE > VIN + 80mV -40°C to 85°C 1.7 µA -40°C to 105°C 5.1 µA VOUT - VIN ≤ 1.0 V VCE > VIN + 80mV -40°C to 85°C 0.7 µA -40°C to 105°C 2.1 µA VOUT - VIN ≤ 5.5 V VCE > VIN + 80mV 0.2 0.3 ON-Resistance (RON) 25°C RON ON-State Resistance IOUT = -200 mA VIN = 5 V 79 -40°C to 85°C -40°C to 125°C ON-State Resistance IOUT = -200 mA VIN = 3.6 V 91 ON-State Resistance IOUT = -200 mA VIN = 1.8 V 110 -40°C to 85°C 125 -40°C to 125°C 140 25°C RON mΩ 120 25°C RON 95 110 141 mΩ 180 -40°C to 85°C 210 -40°C to 125°C 230 mΩ Comparator Chip Enable (CE) VON Turn ON Threshold VCE - VIN -40°C to 125°C –80 mV VOFF Turn OFF Threshold VCE - VIN -40°C to 125°C –250 –150 0 35 80 mV ICE CE Pin Leakage Current VCE < VIN - 250mV -40°C to 125°C 0 160 300 nA ICE CE Pin Leakage Current VCE > VIN + 80mV -40°C to 125°C 0 400 610 nA 0.5 1 A 0.5 1.1 V Reverse Current Blocking (RCB) and Body Diode Characteristics IRCB Reverse Activation Current VCE = VOUT -40°C to 125°C VFWD Body Diode Forward Voltage IOUT = 10 mA VCE > VIN + 80mV -40°C to 125°C 0.1 Status Indication (ST) VOL, ST Output Low Voltage IST = 1 mA -40°C to 125°C tST Status Delay Time VCE transitions from low to high -40°C to 125°C IST ST Pin Leakage Current VCE < VIN - 250mV -40°C to 125°C 0.1 1 –20 V µs 20 nA 6.6 Switching Characteristics Unless otherwise noted, the typical characteristics in the following table applies over the entire recommended operating voltage at an ambient temperature of 25°C and a load of CL = 100 nF and RL = 1kΩ PARAMETER tON tOFF Turn ON Time Turn OFF Time TEST CONDITIONS MIN TYP MAX UNIT VIN = 1.8 V 90 µs VIN = 3.6 V 40 µs VIN = 5 V 27 µs VIN = 1.8 V 2 µs VIN = 3.6 V 2 µs VIN = 5 V 2 µs Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 5 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com Switching Characteristics (continued) Unless otherwise noted, the typical characteristics in the following table applies over the entire recommended operating voltage at an ambient temperature of 25°C and a load of CL = 100 nF and RL = 1kΩ PARAMETER TEST CONDITIONS MIN VIN = 1.8 V tFALL Output Fall Time TYP MAX UNIT 20 µs VIN = 3.6 V 10 µs VIN = 5 V 7.5 µs 6.7 Typical Characteristics 200 240 200 -40qC 25qC 85qC 105qC 180 Quiescent Current (nA) Shutdown Current (nA) 220 180 160 140 120 100 140 120 100 80 60 80 40 60 1.5 20 1.5 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 2 2.5 D001 3 3.5 4 Input Voltage (V) 4.5 5 5.5 D002 VCE > VIN VCE < VIN Figure 1. Shutdown Current vs Input Voltage Figure 2. Quiescent Current vs Input Voltage 180 1000 VOUT - VIN = 1V VOUT - VIN = 4.5V VOUT - VIN = 5.5V 160 On-Resistance (m:) VOUT to VIN Leakage Current (nA) 1200 800 600 400 -20 0 20 40 60 Temperature (qC) 80 100 120 100 -20 0 D003 VCE < VIN Figure 3. Reverse Leakage Current vs Junction Temperature 20 40 60 Temperature (qC) 80 100 120 D004 IOUT = 200mA Figure 4. On-Resistance vs Junction Temperature 65 -50 -40qC 25qC 85qC 105qC -40qC 25qC 85qC 105qC 60 Turn OFF Threshold (V) -75 Turn ON Threshold (V) 140 60 -40 120 VCE > VIN -100 -125 -150 -175 -200 1.5 VIN = 1.8V VIN = 3.6V VIN = 5V 80 200 0 -40 55 50 45 40 35 30 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 25 1.5 5.5 D007 Figure 5. Turn ON Threshold vs Input Voltage 6 160 -40qC 25qC 85qC 105qC 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 D008 Figure 6. Turn OFF Threshold vs Input Voltage Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 0.6 120 0.5 100 Turn ON Time (Ps) Forward Voltage (V) Typical Characteristics (continued) 0.4 0.3 0.2 -40qC 25qC 85qC 105qC 0.1 0 1.5 2 2.5 VCE > VIN 3 3.5 4 Input Voltage (V) 4.5 5 VIN = 1.8V VIN = 3.6V VIN = 5V 80 60 40 20 0 -40 5.5 -20 0 D005 IOUT = 10mA CL = 100nF Figure 7. Body Diode Forward Voltage vs Input Voltage 20 40 60 80 Junction Temperature (qC) 120 D009 RL = 1kΩ Figure 8. Turn ON Time vs Junction Temperature 10 22 VIN = 1.8V VIN = 3.6V VIN = 5V 20 18 Fall Time (Ps) 8 Turn OFF Time (Ps) 100 6 4 16 14 12 10 8 6 2 4 -40 0 -40 -20 CL = 100nF 0 20 40 60 80 Junction Temperature (qC) RL = 1kΩ 100 -20 0 20 40 60 80 Junction Temperature (qC) 100 120 D011 120 D010 VIN = 1.8V to 5V Figure 9. Turn OFF Time vs Junction Temperature CL = 100nF RL = 1kΩ Figure 10. Fall Time vs Junction Temperature 7 Parameter Measurement Information Figure 11. Timing Diagram Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 7 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com 8 Detailed Description 8.1 Overview The LM66100 is a Single-Input, Single-Output (SISO) integrated ideal diode that is well suited for a variety of applications. The device contains a P-channel MOSFET that can operate over an input voltage range of 1.5 V to 5.5 V and can support a maximum continuous current of 1.5 A. The chip enable works by comparing the CE pin voltage to the input voltage. When the CE pin voltage is higher than VIN by 80 mV, the device is disabled and the MOSFET is off. When the CE pin voltage is lower than VIN by 250 mV, the MOSFET is on. The LM66100 also comes with reverse polarity protection (RPP) that can protect the device from a miswired input, such as a reversed battery. 8.2 Functional Block Diagram 8 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 8.3 Feature Description 8.3.1 Reverse Polarity Protection (RPP) In the event a negative input voltage is applied, the ideal diode will stay off and prevent current flow to protect the system load. For a stand-alone, always on application, CE can be tied to GND so it will not go negative with respect to GND see Figure 12. Figure 12. RPP Protection Circuit 8.3.2 Always-ON Reverse Current Blocking (RCB) By connecting the CE pin to VOUT, this allows the comparator to detect reverse current flow through the switch. If the output is forced above the selected input by VOFF, the channel will switch off to stop the reverse current IRCB within tOFF. Once the output falls to below VIN by VON, the device will turn back on. Figure 13. RCB Circuit Figure 14. RCB Waveforms Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 9 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com 8.4 Device Functional Modes Table 1 summarizes the Device Functional Modes: Table 1. Device Functional Modes State IN-to-OUT Power Dissipation OFF Diode IOUT x VFWD ST State L ON Switch IOUT2 x RON H 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LM66100 Ideal Diode can be used in a variety of stand-alone and multi-channel applications. 9.2 Typical Applications 9.2.1 Dual Ideal Diode ORing Two LM66100 Ideal Diodes can be used together for ORing between two power supplies. Figure 15. Dual Ideal Diode ORing 9.2.1.1 Design Requirements Design a circuit that allows the highest input voltage to power a downstream system while providing reverse current protection. 9.2.1.2 Detailed Design Procedure This circuit ties the CE of each device to the opposite power source. In this configuration, the highest supply will always be selected using a make-before-break logic. This prevents any reverse current flow between the supplies and avoids the need of a dedicated reverse current blocking comparator. For ORing applications that need RPP, it is recommended to use a series resistor (RCE) to limit the current into the CE pin during a negative voltage event. 10 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 Typical Applications (continued) 9.2.1.3 Application Curves The below scope shot shows the output voltage (VOUT) being initially powered by VIN1. When VIN2 is applied, it powers VOUT because it is a higher voltage. When VIN2 is removed, VOUT is once again powered by VIN1. Figure 16. Dual Ideal Diode ORing Behavior 9.2.2 Dual Ideal Diode ORing for Continuous Output Power VOUT VIN VIN1 (5V) + - Logic CE GND ST CL VIN2 (3.3V) + - RL Logic CE GND ST Status Indication Figure 17. Dual Ideal Diode ORing for Continuous Output Power 9.2.2.1 Design Requirements The shortcoming of the previous implementation happens when both input voltages are the same for a long period of time, then both devices will completely turn off, powering down the output load. To avoid this case, the status output from the priority supply and a pull up resistor can be used causing both devices to switchover at the same time. For ORing applications that need RPP, it is recommended to use a series resistor (RCE) to limit the current into the CE pin during a negative voltage event. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 11 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com Typical Applications (continued) 9.2.2.2 Application Curves The figures below show the switchover performance between VIN1 and VIN2. Figure 18. Switchover from VIN1 (5 V) to VIN2 (3.3 V) Figure 19. Switchover from VIN2 (3.3V) to VIN1 (5V) 9.2.3 ORing with Discrete MOSFET Figure 20. ORing with a Discrete MOSFET 9.2.3.1 Design Requirements Similar to the Dual Ideal Diode circuit, the Status Output can also be used to control a discrete P-Channel MOSFET. This can be useful in applications that want to minimize the leakage current on the secondary supply, such as battery backup systems. This configuration can also be used on systems that require a lower RON on the secondary rail, useful for higher current applications. When the Ideal Diode path is enabled, the status will be Hi-Z and pull up the gate of the external PFET to keep it off. When the main supply (VIN1) drops such that backup supply (VIN2) is higher than VIN1, the ideal diode will be disabled and pull the ST pin and the PFET gate low to turn on the discrete MOSFET path. 12 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 Typical Applications (continued) 9.2.3.2 Application Curves The figures below show the switchover performance between VIN1 and VIN2. Figure 21. Switchover from VIN1 5 V to VIN2 3.3 V Figure 22. Switchover from VIN2 3.3 V to VIN1 5 V 10 Power Supply Recommendations The device is designed to operate with a VIN range of 1.5 V to 5.5 V. The VIN power supply must be well regulated and placed as close to the device terminal as possible. The power supply must be able to withstand all transient load current steps. In most situations, using an input capacitance (CIN) of 1 μF is sufficient to prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is slow to respond to a large transient current or large load current step, additional bulk capacitance may be required on the input. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 13 LM66100 SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 www.ti.com 11 Layout 11.1 Layout Guidelines For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT and GND helps minimize the parasitic electrical effects. 11.2 Layout Example Figure 23. LM66100 Layout Example 14 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 LM66100 www.ti.com SLVSEZ8A – MARCH 2019 – REVISED JUNE 2019 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks E2E is a trademark of Texas Instruments. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: LM66100 15 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number (1) Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) LM66100DCKR Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1CU LM66100DCKR.A Active Production SC70 (DCK) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 1CU LM66100DCKT Active Production SC70 (DCK) | 6 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 1CU LM66100DCKT.A Active Production SC70 (DCK) | 6 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 1CU Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM66100 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2025 • Automotive : LM66100-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2026 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.45 1.2 4.0 8.0 Q3 LM66100DCKR SC70 DCK 6 3000 178.0 8.4 2.25 LM66100DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 LM66100DCKT SC70 DCK 6 250 180.0 8.4 2.3 2.55 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM66100DCKR SC70 DCK 6 3000 208.0 191.0 35.0 LM66100DCKT SC70 DCK 6 250 180.0 180.0 18.0 LM66100DCKT SC70 DCK 6 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DCK0006A SOT - 1.1 max height SCALE 5.600 SMALL OUTLINE TRANSISTOR C 2.4 1.8 1.4 1.1 PIN 1 INDEX AREA 1 0.1 C B 1.1 0.8 A 6 4X 0.65 1.3 2.15 1.85 2 4 0.30 0.15 C A B NOTE 5 3 6X 0.1 4X 0 -12 0.1 TYP 0.0 4X 4 -15 0.15 0.22 TYP 0.08 GAGE PLANE 8 TYP 0 0.46 TYP 0.26 SEATING PLANE 4214835/D 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Falls within JEDEC MO-203 variation AB. www.ti.com EXAMPLE BOARD LAYOUT DCK0006A SOT - 1.1 max height SMALL OUTLINE TRANSISTOR 6X (0.9) PKG 1 6 6X (0.4) SYMM 2 4X (0.65) 4 3 (R0.05) TYP (2.2) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214835/D 11/2024 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DCK0006A SOT - 1.1 max height SMALL OUTLINE TRANSISTOR PKG 6X (0.9) 1 6 6X (0.4) SYMM 2 4X(0.65) 4 3 (R0.05) TYP (2.2) SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X 4214835/D 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. 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