Datasheet · 2019

TI LM5060 High-Side Protection Controller — Datasheet (SNVS628H)

Rail switch: enable behaviour and quiescent current.

Author: Texas Instruments
Year: 2019
Type: Datasheet
Credit: Texas Instruments (ti.com)

high-side switch
protection
rail switch

Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 LM5060 High-Side Protection Controller With Low Quiescent Current 1 Features 2 Applications • • • • 1 • • • • • • • • • • • • Available in Automotive Grade / AEC Q-100 Wide operating input voltage range: 5.5 V to 65 V Functional safety capable – Documentation available to aid functional safety system design Less than 15-µA quiescent current in disabled mode Controlled output rise time for safe connection of capacitive loads Charge pump gate driver for external N-Channel MOSFET Adjustable Undervoltage Lockout (UVLO) with hysteresis UVLO Serves as second enable input for systems requiring safety redundancy Programmable fault detection delay time MOSFET latched off after load fault is detected Active low open drain POWER GOOD (nPGD) output Adjustable input Overvoltage Protection (OVP) Immediate restart after overvoltage shutdown 10-Lead VSSOP Automotive body electronics Industrial power distribution and control 3 Description The LM5060 high-side protection controller provides intelligent control of a high-side N-channel MOSFET during normal on/off transitions and fault conditions. In-rush current is controlled by the nearly constant rise time of the output voltage. A POWER GOOD output indicates when the output voltage reaches the input voltage and the MOSFET is fully on. Input UVLO (with hysteresis) is provided as well as programmable input OVP. An enable input provides remote on or off control. The programmable UVLO input can be used as second enable input for safety redundancy. A single capacitor programs the initial start-up VGS fault detection delay time, the transition VDS fault detection delay time, and the continuous over-current VDS fault detection delay time. When a detected fault condition persists longer than the allowed fault delay time, the MOSFET is latched off until either the enable input or the UVLO input is toggled low and then high. Device Information(1) PART NUMBER PACKAGE LM5060 VSSOP (10) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit VIN VOUT SENSE GATE OUT VIN LM5060 UVLO OVP STATUS EN GND TIMER High = Fault, Low= OK nPGD High = On, Low= Off GND EN GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications......................................................... 4 6.1 6.2 6.3 6.4 6.5 6.6 7 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics........................................... 5 Typical Characteristics .............................................. 7 Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Applications ................................................ 18 9 Power Supply Recommendations...................... 30 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 31 10.3 Thermal Considerations ........................................ 32 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ 33 Community Resources.......................................... 33 Trademarks ........................................................... 33 Electrostatic Discharge Caution ............................ 33 Glossary ................................................................ 33 12 Mechanical, Packaging, and Orderable Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (January 2016) to Revision H Page • Added Functional safety capable link to the Features section ............................................................................................... 1 • Changed the GATE to GND Absolute Maximum from 75 V to 79 V ..................................................................................... 4 • Added GATE to GND to the Recommended Operating Conditions table .............................................................................. 4 Changes from Revision F (April 2013) to Revision G • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision E (April 2013) to Revision F • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 27 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 5 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View VIN 2 OVP 3 UVLO 4 EN 5 10 GATE LM5060Q1MM SENSE 1 9 OUT 8 nPGD 7 TIMER 6 GND Pin Functions PIN TYPE (1) DESCRIPTION SENSE I Input voltage sense: a constant current sink (16 μA typical) at the SENSE pin flows through an external resistor to set the threshold for fault detection. 2 VIN P Supply voltage input: the operating voltage range is 5.5 V to 65 V. The internal power-on-reset (POR) circuit typically switches to the active state when the VIN pin is greater than 5.1 V. A small ceramic bypass capacitor close to this pin is recommended to suppress noise. 3 OVP I Over-voltage protection comparator input: an external resistor divider from the system input voltage sets the Over-Voltage turn-off threshold. The GATE pin is pulled low when OVP exceeds the typical 2.0-V threshold, but the controller is not latched off. Normal operation resumes when the OVP pin falls below typically 1.76 V. I Under-voltage lock-out comparator input: the UVLO pin is used as an input under-voltage lock-out by connecting this pin to a resistor divider between input supply voltage and ground. The UVLO comparator is activated when EN is high. A voltage greater than typically 1.6 V at the UVLO pin will release the pull down devices on the GATE pin and allow the output to gradually rise. A constant current sink (5.5 µA typical) is provided to ensure the UVLO pin is low in an open circuit condition. NO. NAME 1 4 UVLO 5 EN I Enable input: a voltage less than 0.8 V on the EN pin switches the LM5060 to a low current shutdown state. A voltage greater than 2.0 V on the EN pin enables the internal bias circuitry and the UVLO comparator. The GATE pin pull-up bias is enabled when both EN and UVLO are in the high state. A constant current sink (6 µA typical) is provided to ensure the EN pin is low in an open circuit condition. 6 GND – Circuit ground 7 TIMER I/O Timing capacitor: an external capacitor connected to this pin sets the VDS fault detection delay time. If the TIMER pin exceeds the 2.0-V threshold condition, the LM5060 will latch off the MOSFET and remain off until either the EN, UVLO or VIN (POR) input is toggled low and then high. 8 nPGD O Fault status: an open drain output. When the external MOSFET VDS decreases such that the OUT pin voltage exceeds the SENSE pin voltage, the nPGD indicator is active (low = no fault). 9 OUT I Output voltage sense: connect to the output rail (external MOSFET source). Internally used to detect VDS and VGS conditions. 10 GATE O Gate drive output: connect to the external MOSFET’s gate. A charge-pump driven constant current source (24 µA typical) charges the GATE pin. An internal zener clamps the GATE pin at typically 16.8 V above the OUT pin. The ΔV/Δt of the output voltage can be reduced by connecting a capacitor from the GATE pin to ground. (1) I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 3 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VIN to GND (3) (4) SENSE, OUT to GND (5) MIN MAX UNIT –0.3 75 V –0.3 75 V GATE to GND (3) (5) –0.3 79 V EN, UVLO to GND (4) –0.3 75 V nPGD, OVP to GND –0.3 75 V TIMER to GND –0.3 7 V 260 °C 150 °C 150 °C Peak reflow temperature Operating junction temperature Storage temperature, Tstg (1) (2) (3) (4) (5) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The Absolute Maximum Rating for VIN (75 V) applies only when the LM5060 is disabled. The minimum voltage of –1 V is allowed if the current is limited to below –25 mA. Also it is assumed that the negative voltage on the pins only occur during reverse battery condition when a positive supply voltage (Vin) is not applied. The minimum voltage of –25 V is allowed if the current is limited to below –25 mA. Also it is assumed that the negative voltage on the pins only occur during reverse battery condition when a positive supply voltage (VIN) is not applied. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MAX UNIT VIN Supply voltage MIN 5.5 65 V EN Enable voltage 0 65 V 0 79 V Undervoltage lock-out voltage 0 65 V POWER GOOD off voltage 0 65 V GATE to GND UVLO nPGD TJ 4 NOM POWER GOOD sink current 0 5 mA Operating junction temperature –40 125 °C Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 6.4 Thermal Information LM5060 THERMAL METRIC (1) DGS (VSSOP) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 162.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 57.3 °C/W RθJB Junction-to-board thermal resistance 81.9 °C/W ψJT Junction-to-top characterization parameter 5.8 °C/W ψJB Junction-to-board characterization parameter 80.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). 6.5 Electrical Characteristics Unless otherwise stated the following conditions apply: VIN = 14 V, EN = 2.00 V, UVLO = 2.00 V, OVP = 1.50 V, and TJ = 25°C. Limits in standard type are for TJ = 25°C except where noted. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN PIN TJ = 25°C IIN-EN Input current, enabled mode IIN-DIS Input current, disabled mode EN = 0.50 V IIN-STB Input current, standby mode UVLO = 0.00 V POREN Power on reset threshold at VIN VIN rising POREN-HYS POREN hysteresis VIN falling IOUT-EN OUT pin bias current, enabled OUT = VIN, normal operation IOUT-DIS OUT pin leakage current, disabled (1) Disabled, OUT = 0 V, SENSE = VIN ISENSE Threshold programming current SENSE pin bias current VOFFSET VDS comparator offset voltage SENSE - OUT voltage for fault detection IRATIO ISENSE and IOUT-EN current ratio ISENSE / IOUT-EN 1.4 TJ = –40°C to 125°C 1.7 TJ = 25°C 9 TJ = –40°C to 125°C 15 TJ = 25°C 0.56 TJ = –40°C to 125°C 0.80 TJ = 25°C 5.1 TJ = –40°C to 125°C 5.46 500 mA µA mA V mV OUT PIN TJ = 25°C 8 TJ = –40°C to 125°C 5.0 11.0 0 µA μA SENSE PIN (1) TJ = 25°C 16 TJ = –40°C to 125°C 13.6 TJ = 25°C 18.0 0 TJ = –40°C to 125°C –7.0 TJ = 25°C 7.0 µA mV 2.0 TJ = –40°C to 125°C 1.70 2.30 The GATE pin voltage is typically 12 V above the VIN pin when the LM5060 is enabled. Therefore, the Absolute Maximum Rating for VIN (75 V) applies only when the LM5060 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 75 V. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 5 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Electrical Characteristics (continued) Unless otherwise stated the following conditions apply: VIN = 14 V, EN = 2.00 V, UVLO = 2.00 V, OVP = 1.50 V, and TJ = 25°C. Limits in standard type are for TJ = 25°C except where noted. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVP INPUT OVPTH OVP threshold OVPHYS OVP hysteresis OVPDEL OVP delay time OVPBIAS OVP pin threshold voltage rising TJ = 25°C TJ = –40°C to 125°C 2.0 1.88 Delay from OVP pin > OVPTH to GATE low OVP pin bias current OVP = 1.9 V UVLOTH UVLO threshold UVLO pin threshold voltage rising UVLOHYS UVLO hysteresis UVLOBIAS UVLO pin pull-down current TJ = 25°C 2.12 V 240 mV 9.6 µs 0 TJ = –40°C to 125°C 0.50 µA UVLO INPUT TJ = 25°C TJ = –40°C to 125°C 1.6 1.45 TJ = 25°C TJ = –40°C to 125°C 1.75 180 120 TJ = 25°C 230 5.5 TJ = –40°C to 125°C 3.8 2.00 7.2 V mV µA EN INPUT ENTHH High-level input voltage TJ = –40°C to 125°C ENTHL Low-level input voltage TJ = –40°C to 125°C ENHYS EN threshold hysteresis ENBIAS EN pin pull-down current V 0.80 200 TJ = 25°C 6 TJ = –40°C to 125°C V mV 8.0 µA GATE CONTROL (GATE PIN) TJ = 25°C 24 IGATE Gate charge (sourcing) current, On-state on state IGATE-OFF Gate discharge (sinking) current, off state UVLO = 0.00 V 2.2 mA IGATE-FLT Gate discharge (sinking) current, fault state OUT < SENSE 80 mA VGATE Gate output voltage in normal operation GATE - VIN voltage GATE pin open TJ = 25°C VGS status comparator threshold voltage GATE - OUT threshold voltage for TIMER voltage reset and TIMER current change TJ = 25°C VGATE-TH VGATE-CLAMP Zener clamp between GATE pin and OUT pin IGATE-CLAMP = 0.1 mA 6 Submit Documentation Feedback TJ = –40°C to 125°C TJ = –40°C to 125°C TJ = –40°C to 125°C 17 31 12 10 14 µA V 5 3.50 6.50 16.8 V V Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 Electrical Characteristics (continued) Unless otherwise stated the following conditions apply: VIN = 14 V, EN = 2.00 V, UVLO = 2.00 V, OVP = 1.50 V, and TJ = 25°C. Limits in standard type are for TJ = 25°C except where noted. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMER (TIMER PIN) VTMRH Timer fault threshold TIMER pin voltage rising 2.0 V VTMRL Timer re-enable threshold TIMER pin voltage falling 0.30 V Timer charge current for VDS fault TIMER charge current after start-up VGS = 6.5 V TJ = 25°C ITIMERH Timer start-up charge current TIMER charge current during start-up VGS = 3.5 V TJ = 25°C ITIMERL ITIMERR Timer reset discharge current TIMER pin = 1.5 V tFAULT Fault to GATE low delay TIMER pin > 2.0 V No load on GATE pin 11 TJ = –40°C to 125°C 8.5 13.0 µA 6 TJ = –40°C to 125°C 4.0 TJ = 25°C 7.0 6 TJ = –40°C to 125°C 4.4 8.2 5 µA mA µs POWER GOOD (nPGD PIN) PGDVOL Output low voltage ISINK = 2 mA PGDIOH Off leakage current VnPGD = 10 V TJ = 25°C 80 TJ = –40°C to 125°C TJ = 25°C 205 0.02 TJ = –40°C to 125°C 1.00 mV µA 6.6 Typical Characteristics Figure 1. VIN Pin Current vs VIN Pin Voltage Figure 2. VGATE, VIN Voltage vs Input Voltage Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 7 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics (continued) 8 Figure 3. OUT Pin Current (IOUT-EN) vs VIN Voltage Figure 4. GATE Current (IGATE) vs VIN Voltage Figure 5. SENSE Current (ISENSE) vs VIN Voltage Figure 6. nPGD Low Voltage (PGDVOL vs Sink Current) Figure 7. GATE Pull-Down Current Off (IGATE-OFF) vs GATE Voltage Figure 8. EN Threshold Voltage (ENTH) vs Temperature Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 Typical Characteristics (continued) Figure 9. UVLO Threshold Voltage (UVLOTH) vs Temperature Figure 10. GATE Pull-Down Current Fault (IGATE-FLT) vs GATE Voltage Figure 11. UVLO, EN Current vs Temperature Figure 12. OVP Threshold (OVPTH), Hysteresis (OVPHYS) vs Temperature Figure 13. VGS Comparator Threshold Voltage (VGATE-TH) vs Temperature Figure 14. VDS Comparator Offset Voltage (VOFFSET) vs Temperature Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 9 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics (continued) Figure 15. GATE Current (IGATE) vs Temperature Figure 16. GATE Output Voltage (VGATE) vs Temperature Figure 17. Gate Pull-Down Current - Fault (IGATE-FLT) vs Temperature Figure 18. VIN Pin Current (IEN) vs EN Voltage Figure 19. nPGD Low Voltage (PGDVOL) vs Temperature 10 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 7 Detailed Description 7.1 Overview The LM5060 high-side protection controller features programmable current limit, turn on voltage, fault timer, and overvoltage protection. It also has an enable input and POWER GOOD output. 7.2 Functional Block Diagram GATE OUT LM5060 VIN IGATE 24 PA Charge Pump 16.8V 1 k: VGS Status Comparator IOUT-EN 8 PA VGATE-TH 5V Normal OFF OUT+5V VDS Fault Comparator IGATE-OFF 2.2 mA 500: SENSE Fault OFF ISENSE 16 PA IGATE-FLT 80 mA nPGD PGOOD 6 PA: Start-Up Fault Timer 11 PA: O-C (VDS) Fault Timer One shot OVP 5 PA 6 PA OV OVPTH 2.0V UVLO UVLOTH 1.6V TIMER ITIMERR 6 mA UVLOBIAS 5.5 PA nEN S Q Reset Latch 1.5V R EN ENBIAS 6 PA VTMRL 0.3V Enable Bias Circuit Fault GND Q S Fault Latch VTMRH 2.0V R VIN POR nEN + POR POREN 5.1V Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 11 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com 7.3 Feature Description The LM5060 is designed to drive an external high-side N-channel MOSFET. Over-Current protection is implemented by sensing the voltage drop across the MOSFET. When an adjustable voltage drop threshold is exceeded, and an adjustable time period has elapsed, the MOSFET is disabled. OVP and UVLO monitoring of the input line is also provided. A low state on the enable pin will turn off the N-channel MOSFET and switch the LM5060 into a very low quiescent current off state. An active low POWER GOOD output pin is provided to report the status of the N-channel MOSFET. The waiting time before the MOSFET is turned off after a fault condition is detected can be adjusted with an external timer capacitor. Since the LM5060 uses a constant current source to charge the gate of the external N-channel MOSFET, the output voltage rise time can be adjusted by adding external gate capacitance. This is useful when starting up into large capacitive loads. 7.4 Device Functional Modes 7.4.1 Power-Up Sequence The basic application circuit is shown in Figure 20 and a normal start-up sequence is shown in Figure 21. Startup of the LM5060 is initiated when the EN pin is above the (ENTHH) threshold (2.0 V). At start-up, the timer capacitor is charged with a 6-µA (typical) current source while the gate of the external N-channel MOSFET is charged through the GATE pin by a 24-µA (typical) current source. When the gate-to-source voltage (VGS) reaches the VGATE-TH threshold (typically 5 V) the VGS sequence ends, the timer capacitor is quickly discharged to 0.3 V, and the 5-µA current source is enabled. The timer capacitor will charge until either the VDS Comparator indicates that the drain-to-source voltage (VDS) has been reduced to a nominal value (i.e. no fault) or the voltage on the timer capacitor has reached the VTMRH threshold (i.e. fault). The VDS Comparator monitors the voltage difference between the SENSE pin and the OUT pin. The SENSE pin voltage is user programmed to be lower than the input supply voltage by selecting a suitable sense resistor value. When the OUT pin voltage exceeds the voltage at the SENSE pin, the nPGD pin is asserted low (i.e. no fault) and the timer capacitor is discharged. Q1 VIN VOUT RS SENSE GATE OUT VIN R4 R10 LM5060 UVLO R8 R11 R9 STATUS EN High = Fault, Low= OK OVP TIMER C1 nPGD GND High = On, Low= Off EN GND GND Figure 20. Basic Application Circuit 7.4.2 Status Conditions Output responses of the LM5060 to various input conditions is shown in Table 1. The input parameters include Enable (EN), UVLO, OVP, input voltage (VIN), Start-Up Fault (VGS) and Run Fault (VDS) conditions. The output responses are the VIN pin current consumption, the GATE charge current, the TIMER capacitor charge (or discharge) current, the GATE discharge current if the timer capacitor voltage has reached the VTMRH threshold (typically 2 V), as well as the status of nPGD. 12 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 Device Functional Modes (continued) VTMRH VTIMER 6 PA VTMRL VGATE-TH VGS transition region nPGD OK VGS < 5 V VGS Status EN OFF VGS > 5 V ON Figure 21. Voltages During Normal Start Up Sequence Table 1. Overview of Operating Conditions INPUTS OUTPUTS UVLO OVP (typ) VIN (typ) SENSE-OUT GATE -OUT VIN Current (typ) GATE Current (typ) TIMER GATE after TIMER > 2 V nPGD L L – >5.10 V – – 0.009 mA 2.2 mA sink Low – – Disabled L H – >5.10 V – – 0.009 mA 2.2 mA sink Low – – Disabled EN H L <2 V >5.10 V H L >2 V >5.10 V H H <2 V >5.10 V H H <2 V >5.10 V SENSE>OUT SENSE<OUT SENSE>OUT SENSE<OUT SENSE>OUT SENSE<OUT SENSE>OUT – 0.56 mA 2.2 mA sink Low – – 0.56 mA 80 mA sink Low – <5 V 1.4 mA 24-µA source 6-µA source 80 mA sink H Low – L >5 V 1.4 mA 24-µA source 11-µA source 80 mA sink H Low – L SENSE<OUT H H >2 V >5.10 V H H <2 V <5.10 V (1) SENSE>OUT SENSE<OUT – H – 1.4 mA 80 mA sink Low – – 1.4 mA 2.2 mA sink (see (1)) Low – L H L H L H STATUS Standby Standby Enabled Enabled Overvoltage Power on reset The 2.2 mA sink current is valid for with the VIN pin ≥ 5.1 V. When the VIN pin < 5.1 V the sink current is lower. See ‘GATE Pin Off Current vs. VIN’ plot in Typical Characteristics. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 13 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Gate Control A charge pump provides bias voltage above the input and output voltage to enhance the N-channel MOSFET gate. When the system voltage is initially applied and both EN and UVLO are above their respective thresholds, the GATE pin is charged by the 24-µA (typical) current source. During normal operating conditions, the GATE pin voltage is clamped to approximately 16.8 V above the OUT pin (i.e. VGS) by an internal zener. When either the UVLO input or the EN input is low, or when VIN is below the Power-On Reset voltage of 5.10 V (typical), the GATE pin is discharged with a 2.2 mA (typical) current sink. When the timer capacitor is charged up to the VTMRH threshold (typically 2 V) a fault condition is indicated and the gate of the external N-Channel MOSFET is discharged at a 80 mA (typical) rate. Additionally, when the OVP pin voltage is higher than the OVPTH threshold (typically 2 V) a fault is indicated and the gate of the external NChannel MOSFET is discharged at the same 80 mA (typical) rate. 8.1.2 Fault Timer An external capacitor connected from the TIMER pin to the GND pin sets the fault detection delay time. If the voltage on the TIMER capacitor reaches the VTMRH threshold (2 V typical) a fault condition is indicated. The LM5060 will latch off the MOSFET by discharging the GATE pin at a 80 mA (typical) rate, and will remain latched off until either the EN pin, the UVLO pin, or the VIN pin is toggled low and then high. There are three relevant components to the TIMER pin’s function: 1. A constant 6-µA (typical) current source driving the TIMER pin. This current source is active when EN, UVLO, and VIN are all high. 2. A second current source (5 µA typical) is activated, for a total charge current of 11 µA (typical), only when the VGS sequence has completed successfully. 3. A pull-down current sink for the TIMER pin which resets the timer by discharging the timer capacitor. If EN, UVLO or VIN is low, or when OVP is high, the timer capacitor is discharged. a. When the VDS Fault Comparator detects a fault, (SENSE pin voltage higher than OUT pin voltage) the timer capacitor pull down is disabled and the timer capacitor is allowed to charge at the 11-µA (typical) rate. During Start-Up, the timer behaves as follows: After applying sufficient system voltage and enabling the LM5060 by pulling the EN and UVLO pins high, the timer capacitor will be charged with a 6-µA (typical) current source. The timer capacitor is discharged when the voltage difference between the GATE pin and the OUT pin (i.e. VGS of the external N-Channel MOSFET) reaches the VGATE-TH threshold (typically 5 V). After discharging, the timer capacitor is charged with 11 µA until either the VTMRH threshold (typically 2 V) is reached, or the sensed VDS voltage falls below the threshold of the VDS Fault Comparator, indicating the output voltage has reached the desired steady state level. The timer capacitor voltage waveforms are illustrated in Figure 21, Figure 22, and Figure 23. A timer capacitor is always necessary to allow some finite amount of time for the gate to charge and the output voltage to rise during startup. If an adequate timer capacitor value is not used, then the 6 µA of charge current would cause the TIMER pin voltage to reach the VTMRH fault threshold (typically 2 V) prematurely and the LM5060 will latch off since a fault condition would have been indicated. 14 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 Application Information (continued) Although not recommended, the timer function can be disabled by connecting the TIMER pin directly to GND. With this condition the TIMER pin voltage will never reach the VTMRH fault threshold (2 V typical). The end result is that the fault latch-off protection is completely disabled, while the nPGD pin will continue to reflect the VDS Fault Comparator output. 8.1.3 VGS Considerations The VGS Status Comparator accomplishes two purposes: 1. As the gate of the external MOSFET is charged, the VGS voltage transitions from cut-off, through an active region, and into the ohmic region. The LM5060 provides two fault timer modes to monitor these transitions. The TIMER pin capacitor is initially charged with a constant 6 µA (typical) until either the MOSFET VGS reaches the VGATE–TH threshold (typically 5 V) indicating that the MOSFET channel is at least somewhat enhanced, or the voltage on the TIMER pin reaches the VTMRH threshold (typically 2 V) indicating a fault condition. If the MOSFET VGS reaches 5-V threshold before the TIMER pin reaches the typical 2 V timer fault threshold, the timer capacitor is then discharged to 300 mV, and then begins charging with 11-µA current source while the MOSFET transitions through the active region. The lower timer capacitor charge current during the initial start-up sequence allows more time before a fault is indicated. The turn-on time of the MOSFET will vary with input voltage, load capacitance, load resistance, as well as the MOSFET characteristics. 2. Figure 22 shows a start-up waveform with excessive gate leakage. The initial charge current on the timer capacitor is 6 µA (typical), while the simultaneous charge current to the gate is 24 µA (typical). Due to excessive gate leakage, the 24 µA is not able to charge the gate to the required typical 5 V VGS threshold and the VDS Fault Comparator will indicate a fault when the timer capacitor is charged to the VTMRH fault threshold. When the timer capacitor voltage reaches theVTMRH fault threshold (typically 2 V) the MOSFET gate is discharged at an 80 mA (typical) rate. VTRMRH VTIMER 6 PA Fault Latch VTRMRL GATE pin will be discharged to GND at 80 mA rate VGATE-TH VGS nPGD Fault VGS < 5V VGS Status EN OFF ON Figure 22. Voltages During Startup With VGS Gate Leakage Condition 8.1.4 VDS Fault Condition The LM5060 includes a VDS Fault Comparator that senses the voltage difference between the SENSE pin and the OUT pin. If the voltage at the OUT pin falls lower than the voltage at the SENSE pin, the VDS Fault Comparator will trip and switch the nPGD pin to a high impedance state. It will also initiate charging of the capacitor on the TIMER pin with a 6-µA (typical) current source if VGS is less than than 5-V, or a 11-µA (typical) current source if VGS is higher than 5 V. If the voltage on the TIMER pin reaches the typical 2 V fault threshold, the gate of the N-Channel MOSFET is pulled low with a 80 mA (typical) sink current. Figure 23 illustrates a VDS fault condition during start-up. The nPGD pin never switches low because the VDS fault comparator detects excessive VDS voltage throughout the entire sequence. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 15 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Application Information (continued) 8.1.5 Overcurrent Fault The VDS Fault Comparator can be used to implement an Over-Current shutdown function. The VDS Fault Comparator monitors the voltage difference between the SENSE pin and the OUT pin. This is, essentially, the same voltage that is across the N-Channel MOSFET RDS(ON) less the threshold voltage that is set by the series resistor on the SENSE pin. The value of capacitor on the TIMER pin, the capacitor charge current (ITIMERH, 11 μA typical), along with the TIMER pin fault threshold (VTMRH) will determine the how long the N-Channel MOSFET will be allowed to conduct excessive current before the MOSFET is turned-off. When this delay time expires, the gate is discharged at a 80 mA rate. The LM5060 is intended for applications where precise current sensing is not required, but some level of fault protection is needed. Examples are applications where inductance or impedance in the power path limits the current rise in a short circuit condition. The Safe Operating Area (SOA) of the external N-Channel MOSFET should be carefully considered to ensure the peak drain-to-source current and the duration of the fault delay time is within the SOA rating of the MOSFET. Also note that the RDS(ON) variations of the external N-Channel MOSFET will affect the accuracy of the OverCurrent detection. 8.1.6 Restart After Overcurrent Fault Event When a VDS fault condition has occurred and the TIMER pin voltage has reached 2 V, the LM5060 latches off the external MOSFET. In order to initiate a restart, either the EN pin, the VINpin, or the UVLO pin must be toggled low and then high. VTMRH 11 PA 6 PA VTIMER Fault Latch VTMRL GATE pin will be discharged to GND at 80 mA rate VGS = 5V VGS VGATE-TH transition region nPGD Fault VGS < 5V VGS Status EN OFF VGS > 5V ON Figure 23. Voltages During Startup with VDS Fault Condition 8.1.7 Enable The LM5060 Enable pin (EN) allows for remote On/Off control. The Enable pin on/off thresholds are CMOS compatible. The external N-Channel MOSFET can be remotely switched Off by forcing the EN pin below the lower input threshold, ENTHL (800 mV). The external N-Channel MOSFET can be remotely switched On by forcing the EN pin above the upper input threshold, ENTHH (2.00 V). Figure 24 shows the threshold levels of the Enable pin. When the EN pin is less than 0.5 V (typical) the LM5060 enters a low current (disabled) state. The current consumption of the VIN pin in this condition is 9 µA (typical). 16 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 LM5060 www.ti.com SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 Application Information (continued) up to 65V ON 2.0V (ENTHH) 1.5V (typical) 200 mV (hysterisis) 0.8V (ENTHL) 0.5V (disabled) OFF disabled Figure 24. Enable Function Threshold Levels 8.1.8 UVLO The UVLO function will turn off the external N-Channel MOSFET with a 2.2 mA (typical) current sink at the GATE pin. Figure 25 shows the threshold levels of the UVLO input. A resistor divider as shown in Figure 20 with R10 and R11 sets the voltage at which the UVLO function engages. The UVLO pin may also be used as a second enable pin for applications requiring a redundant, or secondary, shut-down control. Unlike the EN pin function, the UVLO function does not switch the LM5060 to the low current (disabled) state. If the UVLO function is not needed, the UVLO pin should be connected to the VIN pin. The UVLO pin should not be left floating as the internal pull-down will keep the UVLO active. In addition to the programmable UVLO function, an internal Power-On-Reset (POR) monitors the voltage at the VIN pin and turns the MOSFET Off when VIN falls below typically 5.10 V. up to 65V OK 1.6V (UVLOTH) 180 mV (hysterisis) UVLO Figure 25. UVLO Threshold Levels 8.1.9 OVP The OVP function will turn off the external N-Channel MOSFET if the OVP pin voltage is higher than the OVPTH threshold (typically 2 V). A resistor divider made up with R8 and R9, shown in Figure 20, sets the OVP threshold. An internal 9.6-µs timer filters the output of the over-voltage comparator to prevent noise from triggering an OVP event. An OVP event lasting longer than typically 9.6 µs will cause the GATE pin to be discharged with an 80 mA current sink and will cause the capacitor on the TIMER pin to be discharged. If the OVP function is not needed, the OVP pin should be connected to GND. The OVP pin should not be left floating. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: LM5060 17 LM5060 SNVS628H – OCTOBER 2009 – REVISED DECEMBER 2019 www.ti.com Application Information (continued) 8.1.10 Restart After OVP Event After the OVP function has been activated and the gate of the external N-Channel MOSFET has been pulled low, the OUT pin is likely to be low as well. However, an OVP condition will not cause the VDS Fault Comparator to latch off of the LM5060 because the capacitor on the TIMER pin is also discharged during an OVP event. After the OVP pin falls below the lower threshold (typically 1.76 V), the LM5060 will re-start as described in the normal start-up sequence and shown in Figure 21. The EN, VIN, or UVLO pins do not need to be toggled low to high to re-enable the MOSFET after an OVP event. 8.1.11 nPGD Pin The nPGD pin is an open drain connection that indicates when a VDS fault condition has occurred. If the SENSE pin voltage is higher than the OUT pin voltage the state of the nPGD pin will be high impedance. In the typical application, as shown in Figure 20, the voltage at the nPGD pin will be high during any VDS fault condition. The nPGD state is independent of the fault timer function. The resistance R4 should be selected large enough to safely limit the current into the nPGD pin. Limiting the nPGD low state current below 5 mA is recommended. 8.2 Typical Applications Three application examples are provided. Example Number 1: LM5060EVAL Design illustrates the process for the LM5060EVAL in Related Documentation. Example Number 2: Reverse Polarity Protection With Diodes and Example Number 3: Reverse Polarity Protection With Resistor illustrate two other applications that provide additional protection features. 8.2.1 Example Number 1: LM5060EVAL Design Figure 26 shows the schematic for the LM5060EVAL in Related Documentation. Design example number 1 illustrates the basic design procedure used for the evaluation module. Q1 INPUT R4 9.09 k 1 SENSE + R6 100 k STATUS EN D1 51V C4 22 µF High = Fault, Low= OK High = On, Low= Off OUTPUT R5 0.0 C3 10 GATE 9 OUT 2 VIN R1 200 k C2 0.1 µF + C5 22 µF LM5060 R2 38.3 k 4 UVLO R3 14.