Datasheet · 2022

TI ISO1540/ISO1541 Low-Power Bidirectional I2C Isolators — Datasheet (SLLSEB6F)

The isolator in proposal AH-5.

Author: Texas Instruments
Year: 2022
Type: Datasheet
Credit: Texas Instruments (ti.com)

isolator
i2c

ISO1540, ISO1541 SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 ISO154x Low-Power Bidirectional I2C Isolators 1 Features • • • • • • • Isolated bidirectional, I2C compatible, communication Supports up to 1-MHz operation 3-V to 5.5-V supply range Open-drain outputs With 3.5-mA Side 1 and 35mA Side 2 sink current capability –40°C to +125°C operating temperature ±50-kV/µs transient immunity (Typical) HBM ESD protection of 4 kV on all pins; 8 kV on bus pins Safety-related certifications: – 4242-VPK isolation per DIN EN IEC 60747-17 (VDE 0884-17) – 2500-VRMS isolation for 1 minute per UL 1577 – CSA approval per IEC 62368-1 end equipment standard – CQC basic insulation per GB4943.1-2011 2 Applications • • • • • • Isolated I2C buses SMBus and PMBus interfaces Open-drain networks Motor control systems Battery management I2C level shifting The ISO1540 and ISO1541 devices are low-power, bidirectional isolators that are compatible with I2C interfaces. These devices have logic input and output buffers that are separated by Texas Instruments Capacitive Isolation technology using a silicon dioxide (SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. This isolation technology provides for function, performance, size, and power consumption advantages when compared to optocouplers. The ISO1540 and ISO1541 devices enable a complete isolated I2C interface to be implemented within a small form factor. The ISO1540 has two isolated bidirectional channels for clock and data lines while the ISO1541 has a bidirectional data and a unidirectional clock channel. The ISO1541 is useful in applications that have a single controller while the ISO1540 is suitable for multi-controller applications. For applications where clock stretching by the target is possible, the ISO1540 device should be used. Isolated bidirectional communication is accomplished within these devices by offsetting the low-level output voltage on side 1 to a value greater than the highlevel input voltage on side 1, thus preventing an internal logic latch that otherwise would occur with standard digital isolators. Device Information PART NUMBER ISO1540 ISO1541 PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm × 3.91 mm VCC1 VCC2 Isolation Capacitor • 3 Description SDA1 or SCL1 GND1 SDA2 or SCL2 GND2 VREF Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 ESD Ratings............................................................... 6 6.3 Recommended Operating Conditions.........................6 6.4 Thermal Information....................................................7 6.5 Power Ratings.............................................................7 6.6 Insulation Specifications............................................. 8 6.7 Safety-Related Certifications...................................... 9 6.8 Safety Limiting Values.................................................9 6.9 Electrical Characteristics...........................................10 6.10 Supply Current Characteristics............................... 11 6.11 Timing Requirements.............................................. 11 6.12 Switching Characteristics........................................12 6.13 Insulation Characteristics Curves........................... 13 6.14 Typical Characteristics............................................ 14 7 Detailed Description......................................................19 7.1 Overview................................................................... 19 7.2 Functional Block Diagrams....................................... 19 7.3 Feature Description...................................................20 7.4 Isolator Functional Principle......................................20 7.5 Device Functional Modes..........................................21 8 Application and Implementation.................................. 22 8.1 Application Information............................................. 22 8.2 Typical Application.................................................... 23 9 Power Supply Recommendations................................25 10 Layout...........................................................................27 10.1 Layout Guidelines................................................... 27 10.2 Layout Example...................................................... 27 11 Device and Documentation Support..........................28 11.1 Documentation Support.......................................... 28 11.2 Related Links.......................................................... 28 11.3 Receiving Notification of Documentation Updates.. 28 11.4 Community Resources............................................28 11.5 Trademarks............................................................. 28 12 Mechanical, Packaging, and Orderable Information.................................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2019) to Revision F (December 2022) Page 2 • Changed all instances of legacy terminology to controller and target where I C is mentioned.......................... 1 • Editorial and cosmetic changes throughout the document................................................................................. 1 • Updated electrical and switching parameters..................................................................................................... 6 • Updated 'DIN VDE V 0884-11:2017-01' to 'DIN EN IEC 60747-17 (VDE 0884-17)' and removed references to 'CSA/IEC 60950-1'..............................................................................................................................................9 Changes from Revision D (December 2016) to Revision E (March 2019) Page • Changed VDE Standard name From: DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 To: DIN VDE V 0884-11:2017-01 in Section 1 ............................................................................................................................1 • Changed Section 1 bullet From: CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards To: CSA approval per IEC 60950-1 and IEC 62368-1 end equipment standards........... 1 • Updated certifications approval status, numbers, standard names, and details according to the latest agency certificates in Section 6.7 table........................................................................................................................... 9 • Changed both bypass capacitors From: 10 µF To: 0.1 µF in . Even though larger capacitors can be used, 0.1 µF is the minimum recommended bypass capacitor size................................................................................. 24 • Changed both bypass capacitors From: 10 µF To: 0.1 µF in . Even though larger capacitors can be used, 0.1 µF is the minimum recommended bypass capacitor size................................................................................. 24 Changes from Revision C (June 2015) to Revision D (December 2016) Page • Deleted the Device Comparison Table; see the Features List table for device comparison ..............................4 • Changed the status of CQC certification from planned to certified ....................................................................9 • Changed the Regulatory Information table to Safety-Related Certifications and updated content.....................9 • Changed formatting of supply current parameters to combine device and sides. Moved parameters to separate table .................................................................................................................................................. 11 • Added the Receiving Notification of Documentation Updates section .............................................................28 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 Changes from Revision B (May 2013) to Revision C (June 2015) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 • VDE Standard changed to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 .................................................1 • Changed minimum air gap (Clearance) parameter, L(I01), to external clearance, CLR, and minimum external tracking (creepage) parameter, L(I02), to external creepage............................................................................. 8 • Changed values and test conditions in the Insulation Specifications table.........................................................8 • Changed the descriptions of VDE and CSA information ................................................................................... 9 Changes from Revision A (October 2012) to Revision B (May 2013) Page • Change Safety Feature From: (VDE 0884 Part 2) (Pending) To: (VDE 0884 Part 2) (Approved)...................... 1 • Changed, VDE column From: File number: 40016131 (pending) To: File number: 40016131...........................9 Changes from Revision * (July 2012) to Revision A (October 2012) Page • Changed From: CSA Component Acceptance Notice 5A (Pending) To: CSA Component Acceptance Notice 5A (Approved).....................................................................................................................................................1 • Changed From: IEC 60950-1 and IEC 61010-1 End Equipment Standards (Pending) To: IEC 60950-1 and IEC 61010-1 End Equipment Standards (Approved)..........................................................................................1 • Changed Section 6.7, CSA column From: File number: 220991 (pending) To: File number: 220991................9 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 3 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 5 Pin Configuration and Functions 1 8 VCC2 SDA1 2 7 SDA2 SCL1 3 6 SCL2 GND1 4 5 GND2 Isolation VCC1 Side 1 Side 2 Not to scale Figure 5-1. ISO1540 D Package 8-Pin SOIC Top View Table 5-1. Pin Functions—ISO1540 PIN 4 I/O DESCRIPTION NAME NO. GND1 4 — Ground, side 1 GND2 5 — Ground, side 2 SCL1 3 I/O Serial clock input / output, side 1 SCL2 6 I/O Serial clock input / output, side 2 SDA1 2 I/O Serial data input / output, side 1 SDA2 7 I/O Serial data input / output, side 2 VCC1 1 — Supply voltage, side 1 VCC2 8 — Supply voltage, side 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 1 8 VCC2 SDA1 2 7 SDA2 SCL1 3 6 SCL2 GND1 4 5 GND2 Isolation VCC1 Side 1 Side 2 Not to scale Figure 5-2. ISO1541 D Package 8-Pin SOIC Top View Table 5-2. Pin Functions—ISO1541 PIN I/O DESCRIPTION NAME NO. GND1 4 — Ground, side 1 GND2 5 — Ground, side 2 SCL1 3 I Serial clock input, side 1 SCL2 6 O Serial clock output, side 2 SDA1 2 I/O Serial data input / output, side 1 SDA2 7 I/O Serial data input / output, side 2 VCC1 1 — Supply voltage, side 1 VCC2 8 — Supply voltage, side 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 5 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) Voltage MIN MAX VCC1, VCC2 –0.5 6 SDA1, SCL1 –0.5 VCC1 + 0.5(3) SDA2, SCL2 –0.5 VCC2 + 0.5(3) SDA1, SCL1 0 20 SDA2, SCL2 0 100 IO Output current TJ(MAX) Maximum junction temperature Tstg Storage temperature (1) (2) (3) –65 UNIT V mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values here within are with respect to the local ground pin (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC Bus pins JS-001(1) All pins ±8000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) ±1500 UNIT ±4000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX UNIT VCC1, VCC2 Supply voltage 3 5.5 V VSDA1, VSCL1 Input and output signal voltages, side 1 0 VCC1 V VSDA2, VSCL2 Input and output signal voltages, side 2 0 VCC2 V VIL1 Low-level input voltage, side 1 0 0.5 V VIH1 High-level input voltage, side 1 0.7 × VCC1 VCC1 V VIL2 Low-level input voltage, side 2 0 0.3 × VCC2 V VIH2 High-level input voltage, side 2 0.7 × VCC2 VCC2 V IOL1 Output current, side 1 0.5 3.5 mA IOL2 Output current, side 2 0.5 35 mA C1 Capacitive load, side 1 40 pF C2 Capacitive load, side 2 400 pF fMAX Operating frequency(1) 1 MHz TA Ambient temperature –40 125 °C TJ Junction temperature –40 136 °C TSD Thermal shutdown 139 197 °C (1) This represents the maximum frequency with the maximum bus load (C) and the maximum current sink (IO). If the system has less bus capacitance, then higher frequencies can be achieved. 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.4 Thermal Information ISO154x THERMAL METRIC(1) UNIT D (SOIC) 8 PINS RθJA Junction-to-ambient thermal resistance 114.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.6 °C/W RθJB Junction-to-board thermal resistance 55.3 °C/W ψJT Junction-to-top characterization parameter 27.2 °C/W ψJB Junction-to-board characterization parameter 54.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). 6.5 Power Ratings PARAMETER TEST CONDITIONS PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (side-1) PD2 Maximum power dissipation (side-2) VCC1 = VCC2 = 5.5 V, TJ = 150 °C, C1 = 20 pF, C2 = 400 pF; R1 = 1.4 kΩ, R2 = 94 Ω; Input a 1-MHz 50% duty cycle clock signal MIN TYP MAX UNIT 105 mW 37 mW 68 mW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 7 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.6 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest terminal-to-terminal distance through air >4 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >4 mm DTI Distance through the insulation Minimum internal gap (internal clearance) 0.014 mm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III Material group Overvoltage category II DIN EN IEC 60747-17 (VDE 0884-17)(2) VIORM VIOTM Maximum repetitive peak isolation voltage AC voltage (bipolar) Maximum transient isolation voltage Apparent charge(3) qpd Barrier capacitance, input to output(4) CIO Isolation resistance, input to output(4) RIO 566 VPK VTEST = VIOTM t = 60 s (qualification) t = 1 s (100% production) 4242 VPK Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 680 VPK, tm = 10 s <5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 906 VPK, tm = 10 s <5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 1062 VPK, tm = 1 s <5 VIO = 0.4 sin (2πft), f = 1 MHz ~1 VIO = 500 V, TA = 25°C >1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500 V at TS = 150°C >109 Pollution degree 2 Climatic category 40/125/21 pC pF Ω UL 1577 VISO (1) Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production) 2500 VRMS (3) (4) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device 8 Submit Document Feedback (2) Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.7 Safety-Related Certifications VDE CSA UL CQC Certified according to DIN EN IEC 60747-17 (VDE 0884-17) and DIN EN 61010-1 (VDE 0411-1) Certified according to CSA/IEC 62368-1 Recognized under UL 1577 Component Recognition Program Certified according to GB4943.1-2011 Basic Insulation Maximum Transient Overvoltage, 4242 VPK; Maximum Repetitive Peak Voltage, 566 VPK 2.5-kVRMS Insulation Rating; 300 VRMS Basic Insulation working voltage per CSA 62368-1-14 and IEC 62368-1:2014 Single protection, 2500 VRMS Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certificate number: 40047657 Master contract number: 220991 File number: E181974 Certificate number: CQC14001109540 6.8 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS TS Safety input, output, or supply current TEST CONDITIONS MIN TYP MAX RθJA = 114.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 6-1 198 RθJA = 114.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 6-1 303 Safety temperature UNIT mA 150 °C The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Section 6.4 table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 9 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.9 Electrical Characteristics over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SIDE 1 (ONLY) VILT1 Voltage input threshold low, SDA1 and SCL1 480 550 660 mV VIHT1 Voltage input threshold high, SDA1 and SCL1 520 610 700 mV VHYST1 Voltage input hysteresis 40 60 VOL1 Low-level output voltage, SDA1 and 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA SCL1(1) 570 ΔVOIT1 Low-level output voltage to highlevel input voltage threshold difference, SDA1 and SCL1(1) (2) 50 VIHT1 –VILT1 0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA mV 800 mV mV SIDE 2 (ONLY) VILT2 Voltage input threshold low, SDA2 and SCL2 0.3 × VCC2 0.4 × VCC2 V VIHT2 Voltage input threshold high, SDA2 and SCL2 0.4 × VCC2 0.5 × VCC2 V VHYST2 Voltage input hysteresis VOL2 Low-level output voltage, SDA2 and 0.5 mA ≤ (ISDA2 and ISCL2) ≤ 35 mA SCL2 VIHT2 – VILT2 0.05 × VCC2 V 0.4 V 10 µA BOTH SIDES |II| Input leakage currents, SDA1, SCL1, SDA2, and SCL2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2 CI Input capacitance to local ground, SDA1, SCL1, SDA2, and SCL2 VI = 0.4 × sin(2E6πt) + 2.5 V CMTI Common-mode transient immunity See Figure 7-3 VCCUV VCC undervoltage lockout threshold(3) (1) (2) (3) 10 0.01 7 pF 25 50 kV/µs 1.7 2.5 2.9 V This parameter does not apply to the ISO1541 SCL1 line as it is unidirectional. ∆VOIT1 = VOL1 – VIHT1. This represents the minimum difference between a Low-Level Output Voltage and a High-Level Input Voltage Threshold to prevent a permanent latch condition that would otherwise exist with bidirectional communication. Any VCC voltages, on either side, less than the minimum will ensure device lockout. Both VCC voltages greater than the maximum will prevent device lockout. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.10 Supply Current Characteristics over recommended operating conditions, unless otherwise noted. For more information, see Figure 7-1. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1, R2 = Open; C1, C2 = Open 2.4 7.1 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 2.5 4 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1, R2 = Open; C1, C2 = Open 2.1 6.1 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 2.3 3.6 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1, R2 = Open; C1, C2 = Open 1.7 6.7 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 1.9 3.5 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1,R2 = Open; C1,C2 = Open 3.1 7.2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 3.1 4.7 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1, R2 = Open; C1, C2 = Open 2.8 6.2 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 2.9 4.5 VSDA1, VSCL1 = GND1; VSDA2, VSCL2 = GND2; R1, R2 = Open; C1, C2 = Open 2.3 6.8 VSDA1, VSCL1 = VCC1; VSDA2, VSCL2 = VCC2; R1, R2 = Open; C1, C2 = Open 2.5 4 MIN NOM MAX UNIT 30 50 151 µs 3 V ≤ VCC1, VCC2 ≤ 3.6 V ISO1540 ICC1 Supply current, side 1 ISO1541 ICC2 Supply current, side 2 ISO1540 and ISO1541 mA mA 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V ISO1540 ICC1 Supply current, side 1 ISO1541 ICC2 Supply current, side 2 ISO1540 and ISO1541 mA mA 6.11 Timing Requirements tUVLO Time to recover from UVLO 2.7 V to 0.9 V; See Figure 7-4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 11 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.12 Switching Characteristics over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 V ≤ VCC1, VCC2 ≤ 3.6 V Output Signal Fall Time (SDA1, SCL1) See Figure 7-1 R1 = 953 Ω, C1 = 40 pF 0.7 × VCC1 to 0.3 × VCC1 8 17 29 tf1 0.9 × VCC1 to 900 mV 16 29 48 Output Signal Fall Time (SDA2, SCL2) See Figure 7-1 R2 = 95.3 Ω, C2 = 400 pF 0.7 × VCC2 to 0.3 × VCC2 14 23 47 tf2 0.9 × VCC2 to 400 mV 35 50 100 tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 0.55 V to 0.7 × VCC2 33 65 ns tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 0.7 V to 0.4 V 90 181 ns PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| 55 123 ns tPLH2-1 (1) Low-to-High Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.7 × VCC1 47 68 ns tPHL2-1 (1) High-to-Low Propagation Delay, Side 2 to Side 1 0.4 × VCC2 to 0.9 V 67 109 ns PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| 20 49 ns tLOOP1 (1) Round-trip propagation delay on Side 1 100 165 ns See Figure 7-1 R1 = 953 Ω, R2 = 95.3 Ω, C1, C2 = 10 pF See Figure 7-2; R1 = 953 Ω, C1 = 40 pF R2 = 95.3 Ω, C2 = 400 pF 0.4 V to 0.3 × VCC1 ns ns 4.5 V ≤ VCC1, VCC2 ≤ 5.5 V Output Signal Fall Time (SDA1, SCL1) See Figure 7-1 R1 = 1430 Ω, C1 = 40 pF 0.7 × VCC1 to 0.3 × VCC1 6 11 22 tf1 0.9 × VCC1 to 900 mV 13 21 48 Output Signal Fall Time (SDA2, SCL2) See Figure 7-1 R2 = 143 Ω, C2 = 400 pF 0.7 × VCC2 to 0.3 × VCC2 10 18 35 tf2 0.9 × VCC2 to 400 mV 28 41 76 tpLH1-2 Low-to-High Propagation Delay, Side 1 to Side 2 0.55 V to 0.7 × VCC2 31 62 ns tPHL1-2 High-to-Low Propagation Delay, Side 1 to Side 2 0.7 V to 0.4 V 70 139 ns PWD1-2 Pulse Width Distortion |tpHL1-2 – tpLH1-2| 38 80 ns tPLH2-1 (1) Low-to-high propagation delay, side 2 to side 1 0.4 × VCC2 to 0.7 × VCC1 55 80 ns tPHL2-1 (1) High-to-low propagation delay, Side 2 to side 1 0.4 × VCC2 to 0.9 V 47 85 ns PWD2-1 (1) Pulse Width Distortion |tpHL2-1 – tpLH2-1| 8 34 ns tLOOP1 (1) Round-trip propagation delay on side 1 110 180 ns See Figure 7-1 R1 = 1430 Ω, R2 = 143 Ω, C1,2 = 10 pF See Figure 7-2; R1 = 1430 Ω, C1 = 40 pF R2 = 143 Ω, C2 = 400 pF 0.4 V to 0.3 × VCC1 (1) This parameter does not apply to the ISO1541 SCL1 line as it is unidirectional. 12 Submit Document Feedback ns ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.13 Insulation Characteristics Curves 350 VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V Safety Limiting Current (mA) 300 250 200 150 100 50 0 0 50 100 150 Ambient Temperature (qC) 200 Figure 6-1. Thermal Derating Curve for Limiting Current per VDE Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 13 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 6.14 Typical Characteristics 0.800 3.0 IOL1 = 3.5 mA IOL1 = 0.5 mA 2.5 0.760 Output Current, IOL1 (mA) Output Voltage, VOL1 (V) 0.780 0.740 0.720 0.700 0.680 0.660 0.640 2.0 1.5 1.0 0.5 0.0 -0.5 0.620 −40 −25 −10 5 20 35 50 65 80 Free−Air Temperature (°C) 95 110 125 20 18 16 16 14 14 8 6 4 0.7 0.8 0.9 R1 = 1430 : R1 = 2.2 k: 10 8 6 -25 -10 5 20 35 50 65 80 Free-Air Temperature (qC) 95 2 0 -40 110 125 25 Fall Time tf2 (ns) 25 20 15 10 5 20 35 50 65 80 Free-Air Temperature (qC) 95 20 35 50 65 80 Free-Air Temperature (qC) 110 125 Figure 6-6. Side 2: Output Fall Time vs Free-Air Temperature 110 125 D002 15 10 0 -40 R2 = 143 : R2 = 2.2 k: -25 -10 D003 VCC2 = 3.3 V C2 = 400 pF Fall time measured from 70% to 30% VCC2 95 20 5 R2 = 95.3 : R2 = 2.2 k: -10 5 Figure 6-5. Side 1: Output Fall Time vs Free-air Temperature 30 -25 -10 VCC1 = 5 V C1 = 40 pF Fall time measured from 70% to 30% VCC1 30 5 -25 D001 Figure 6-4. Side 1: Output Fall Time vs Free-Air Temperature Fall Time tf2 (ns) 0.6 12 VCC1 = 3.3 V C1 = 40 pF Fall time measured from 70% to 30% VCC1 14 0.5 4 R1= 953 : R1= 2.2 k: 2 0 -40 0.4 Figure 6-3. Side 1: Output Low Current vs SDA1 or SCL1 Applied Voltage 18 10 0.3 TA = 25°C 20 12 0.2 Applied Voltage, VSDA1, VSCL1 (V) Fall Time, tf1 (ns) Fall Time, tf1 (ns) Figure 6-2. Side 1: Output Low Voltage vs Free-Air Temperature 0 -40 0.1 0 0.600 5 20 35 50 65 80 Free-Air Temperature (qC) 95 110 125 D004 VCC2 = 5 V C2 = 400 pF Fall time measured from 70% to 30% VCC2 Figure 6-7. Side 2: Output Fall Time vs Free-Air Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 45 120 Propagation Delay, tPHL1-2 (ns) Propagation Delay, t PLH1-2 (ns) 40 35 30 25 20 15 10 VCC1 and VCC2 = 3.3 V, R2 = 95.3 : VCC1 and VCC2 = 5 V, R2 = 143 : 5 0 -40 -25 -10 5 20 35 50 65 80 Free-Air Temperature (qC) 95 100 80 60 40 20 0 -40 110 125 20 35 50 65 80 Free-Air Temperature (qC) 95 110 125 D006 90 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 1045 80 Propagation Delay, t PHL1-2 (ns) Propagation Delay, tPLH1-2 (ns) 5 Figure 6-9. tPHL1-2 Propagation Delay vs Free-Air Temperature 1050 1040 1035 1030 1025 1020 1015 1010 1005 70 60 50 40 30 20 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 10 -25 -10 5 R2 = 2.2 kΩ 20 35 50 65 80 Free-Air Temperature (qC) 95 0 -40 110 125 C2 = 400 pF 70 Propagation Delay, t PHL2-1 (ns) 60 50 40 30 20 5 20 35 50 65 80 Free-Air Temperature (qC) 20 35 50 65 80 Free-Air Temperature (qC) 95 110 125 110 125 D008 C2 = 400 pF 50 40 30 20 0 -40 VCC1 and VCC2 = 3.3 V, R1 = 953 : VCC1 and VCC2 = 5 V, R1 = 1430 : -25 -10 D009 C1 = 10 pF 95 60 10 VCC1 and VCC2 = 3.3 V, R1 = 953 : VCC1 and VCC2 = 5 V, R1 = 1430 : -10 5 Figure 6-11. tPHL1-2 Propagation Delay vs Free-Air Temperature 80 -25 -10 R2 = 2.2 kΩ 70 10 -25 D007 Figure 6-10. tPLH1-2 Propagation Delay vs Free-Air Temperature Propagation Delay, t PHL2-1 (ns) -10 C2 = 10 pF Figure 6-8. tPLH1-2 Propagation Delay vs Free-Air Temperature 0 -40 -25 D005 C2 = 10 pF 1000 -40 VCC1 and VCC2 = 3.3 V, R2 = 95.3 : VCC1 and VCC2 = 5 V, R2 = 143 : 5 20 35 50 65 80 Free-Air Temperature (qC) 95 110 125 D010 C1 = 10 pF Figure 6-12. tPLH2-1 Propagation Delay vs Free-Air Temperature Figure 6-13. tPHL2-1 Propagation Delay vs Free-Air Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 15 ISO1540, ISO1541 www.ti.com 148 80 146 70 Propagation Delay, t PHL2-1 (ns) Propagation Delay, tPLH2-1 (ns) SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 144 142 140 138 136 134 132 -40 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V -25 -10 5 20 35 50 65 80 Free-Air Temperature (qC) R1 = 2.2 kΩ 95 60 50 40 30 20 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V 10 0 −40 −25 −10 110 125 D011 C1 = 40 pF 5 20 35 50 65 80 Free-Air Temperature (°C) R1 = 2.2 kΩ Figure 6-14. tPLH2-1 Propagation Delay vs Free-Air Temperature 95 110 125 C1 = 40 pF Figure 6-15. tPHL2-1 Propagation Delay vs Free-Air Temperature 140 600 120 595 tLOOP1 (ns) tLOOP1 (ns) 100 80 60 590 585 40 580 20 0 -40 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V VCC1 and VCC2 = 3.3 V, R1 = 953 :, R2 = 95.3 : VCC1 and VCC2 = 5 V, R1 = 1430 :, R2 = 143 : -25 -10 5 20 35 50 65 80 Free-Air Temperature (qC) C1 = 40 pF 95 110 125 -25 -10 D013 C2 = 400 pF Figure 6-16. tLOOP1 vs Free-Air Temperature Common-Mode Transient Immunity (kV/Ps) 575 -40 5 20 35 50 65 80 Free-Air Temperature (qC) C1 = 40 pF R1 = 2.2 kΩ 95 110 125 D014 C2 = 400 pF R2 = 2.2 kΩ Figure 6-17. tLOOP1 vs Free-Air Temperature 70 60 50 40 30 20 10 0 -40 VCC1 and VCC2 = 3.3 V VCC1 and VCC2 = 5 V -25 -10 5 20 35 50 65 80 Free-Air Temperature (qC) 95 110 125 D015 Figure 6-18. CMTI vs Free-Air Temperature 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 Parameter Measurement Information VCC1 R1 ± + ± + R1 VCC2 R2 SDA1 R2 SDA2 ISO1540 ISO1541 SCL2 SCL1 C1 C1 C2 C2 Copyright © 2016, Texas Instruments Incorporated Figure 7-1. Test Diagram VCC2 VCC1 R1 SDA1 or SCL1 Output C1 GND1 Isolation VCC1 tLOOP1 0.3 VCC1 SDA1 SCL1 (ISO1540 Only) 0.4 V GND1 Copyright © 2016, Texas Instruments Incorporated Figure 7-2. tLoop1 Setup and Timing Diagram VCCx VCCy 2k 2k Input Isolation + Output ± GNDx GNDy VCMTI Figure 7-3. Common-Mode Transient Immunity Test Circuit Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 17 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 VCCx VCCy VCCx SDAx or SCLx Ry I solatio n 0V Side x, Side y VCCx,VCCy Ry 1, 2 3.3 V, 3.3 V 95.3 Ω 2, 1 3.3 V, 3.3 V 953 Ω + Output GNDy GNDx or VCCx VCCy VCCy Ry SDAx or SCLx Isola tion 0V + Output GNDx GNDy VCCx or VCCy VCCx (UVLO+) t UVLO 0 .9 V Output Figure 7-4. tUVLO Test Circuit and Timing Diagrams 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 7 Detailed Description 7.1 Overview The I2C bus is used in a wide range of applications because it is simple to use. The bus consists of a two-wire communication bus that supports bidirectional data transfer between a controller device and several target devices. The controller, or processor, controls the bus, specifically the serial clock (SCL) line. Data is transferred between the controller and target through a serial data (SDA) line. This data can be transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode (0 to 3.4 Mbps). The most common speeds are the standard and fast modes. The I2C bus operates in bidirectional, half-duplex mode, while standard digital isolators are unidirectional devices. To make efficient use of one technology supporting the other, external circuitry is required that separates the bidirectional bus into two unidirectional signal paths without introducing significant propagation delay. These devices have their logic input and output buffers separated by TI's capacitive isolation technology using a silicon dioxide (SiO2) barrier. When used in conjunction with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. 7.2 Functional Block Diagrams VCC1 VCC2 SDA2 VREF Isolation Capacitor SDA1 SCL1 SCL2 GND1 GND2 VREF Figure 7-1. ISO1540 Block Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 19 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 VCC2 SDA1 SDA2 Isolation Capacitor VCC1 VREF SCL1 SCL2 GND1 GND2 Figure 7-2. ISO1541 Block Diagram 7.3 Feature Description The device enables a complete isolated I2C interface to be implemented within a small form factor having the features listed in Table 7-1. Table 7-1. Features List (1) PART NUMBER CHANNEL DIRECTION ISO1540 Bidirectional (SCL) Bidirectional (SDA) ISO1541 Unidirectional (SCL) Bidirectional (SDA) RATED ISOLATION(1) MAXIMUM FREQUENCY 2500 VRMS 4242 VPK 1 MHz See Section 6.7 for detailed Isolation specifications. 7.4 Isolator Functional Principle To isolate a bidirectional signal path (SDA or SCL), the ISO1540 internally splits a bidirectional line into two unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1540 connects to a low-capacitance I2C node, while side 2 is designed for connecting to a fully loaded I2C bus with up to 400 pF of capacitance. VCC1 VCC2 A RPU1 B SDA1 ISO1540 VC-out RPU2 SDA2 40 mV Cnode 50 mV Cbus C VSDA1 D VILT1 VIHT1 VOL1 GND1 VREF GND2 Figure 7-3. SDA Channel Design and Voltage Levels at SDA1 At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up. However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode drop to approximately 0.75 V, and the input buffer (C) that consists of a comparator with defined hysteresis. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISO1540 ISO1541 ISO1540, ISO1541 www.ti.com SLLSEB6F – JULY 2012 – REVISED DECEMBER 2022 The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V (maximum) driven directly by SDA1 and the buffered output low-level of B. Figure 7-4 demonstrate the switching behavior of the I2C isolator, ISO1540, between a controller node at SDA1 and a heavy loaded bus at SDA2. VCC2 VOL1 SDA1 50% SDA2 VIHT1 30% Receive Delay Receive Delay VCC1 Receive Delay Transmit Delay VCC1 VCC2 VCC2 SDA2 50% SDA1 VCC1 VCC1 VCC2 Transmit Delay VIHT2 30% Figure 7-4. SDA Channel Timing in Receive and Transmit Directions 7.4.1 Receive Direction (Left Diagram of ) When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the buffered output of VOL1 = 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum input-low voltage of VIL = 0.9 V at 3 V supply levels. When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 reaches VCC2 potential. 7.4.2 Transmit Direction (Right Diagram of ) When a controller drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed immediately as it is overwritten by the lower low-level of the controller. However, when the controller releases SDA1, the voltage potential increases and first must pass the upper input threshold of the comparator, VIHT1, to release SDA2. SDA1 then increa