Datasheet · 2022

Infineon EZ-PD CCG3PA USB Type-C Port Controller — Datasheet (002-16951 Rev *H)

Source-side controller, covered as a 'why not'.

Author: Infineon Technologies
Year: 2022
Type: Datasheet
Credit: Infineon (infineon.com)

usb pd
source controller

CYPD3171, CYPD3174, CYPD3175 EZ-PD™ CCG 3PA Consumer US B Type -C port con trol le r General description EZ-PD™ CCG3PA is Infineon’s highly integrated USB Type-C port controller that complies with the latest USB Type-C and PD standards and is targeted for PC power adapters, mobile chargers, car chargers, and power bank applications. In such applications, CCG3PA provides additional functionalities and BOM integration advantages. CCG3PA uses Infineon’s proprietary M0S8 technology with a 32-bit Arm® Cortex®-M0 processor, 64-KB flash, a complete Type-C USB PD transceiver, all termination resistors required for a Type-C port, integrated feedback control circuitry for voltage (VBUS) regulation, and system-level ESD protection. It is available in 24-pin QFN and 16-pin SOIC packages. Features • Type-C support and USB PD support - Supports USB PD Revision 3.1 including programmable power supply (PPS) mode - Configurable resistors RP and RD - Supports one USB Type-C port and one Type-A port • 2x legacy/proprietary charging blocks - Supports QC 4.0, Apple charging 2.4A, AFC, BC 1.2 - Integrates all required terminations on DP/DM lines • Integrated voltage (VBUS) regulation and current sense amplifier - Analog regulation of secondary side feedback node (direct feedback or opto coupler) - Integrated shunt regulator function for VBUS control - Constant current or constant voltage mode - Supports low-side current sensing for constant current control • System-level fault protection - VBUS to CC short protection - On-chip OVP, OCP, UVP, and SCP - Supports OTP through integrated ADC circuit • 32-bit MCU subsystem - Arm® Cortex®-M0 CPU - 64-KB Flash - 8-KB SRAM • Clocks and oscillators - Integrated oscillator eliminating the need for external clock • Power - 3.0-V to 24.5-V operation (30-V tolerant) • System-level ESD protection - On CC, VBUS_C_MON_DISCHARGE, DP0, DM0, P2.2, and P2.3 pins - ± 8-kV contact discharge and ±15-kV air gap discharge based on IEC61000-4-2 level 4C • Packages - 24-pin QFN and 16-pin SOIC - Supports extended industrial temperature range (–40°C to +105°C) Datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document page 1 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Logic block diagram Logi c blo ck diagram CCG3PA: Single- Chip Type - C Controller MCU Subsystem Cortex® Advanced High - Performance Bus (AHB) Arm ® - M0 Flash (64 KB) SRAM (8 KB) I/O Subsystem Programmable I/O Matrix Integrated Digital Blocks 4x TCPWM 2x SCB (I 2 C, SPI, UART) CC GPIOs USB PD Subsystem System Resources Baseband PHY OCP and OVP Protection RP , R D Low- side Current Sense Amplifier Voltage (VBUS) Regulation 2x PFET Gate Drivers 2x VBUS Discharge High Voltage Regulator 2x 8- bit SAR ADCs 2x Charger Detect In ternal block di agram VBUS_P_CTRL VBUS_IN_DISCHARGE VBUS_C_CTRL OV/UV, R-Div VDDD R-Div HV Reg DISCH 3.3 V VCCD VBUS_C_MON_DISCHARGE 1.8 V Prog DISCH LDO BMC PHY MCU Subsystem Advanced High- Performance Bus (AHB) FB Cortex®-M0 CATH/ COMP LSCSA 2x ADCs Flash (64 KB) 4x TCPWM SRAM (8 KB) 2x SCB Charger Detect0 Charger Detect1 CC1 CC2 DP0 / GPIO DM0 / GPIO DP1 / GPIO DM1 / GPIO POR AXRES / GPIO GPIO GPIO (I2C, SPI, UART) CSP GND Type-C Connector Ground Rs Datasheet 2 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Table of contents Table of contents General description ...........................................................................................................................1 Features ...........................................................................................................................................1 Logic block diagram ..........................................................................................................................2 Internal block diagram ......................................................................................................................2 Table of contents ...............................................................................................................................3 1 Functional overview .......................................................................................................................4 1.1 MCU subsystem.......................................................................................................................................................4 1.1.1 CPU .......................................................................................................................................................................4 1.1.2 Flash .....................................................................................................................................................................4 1.1.3 SROM ....................................................................................................................................................................4 1.2 USB PD subsystem (SS) ..........................................................................................................................................4 1.2.1 USB PD physical layer ..........................................................................................................................................4 1.2.2 Analog-to-digital converter (ADC).......................................................................................................................4 1.2.3 Charger detection ................................................................................................................................................4 1.2.4 VBUS overcurrent and overvoltage protection ..................................................................................................4 1.2.5 VBUS short protection .........................................................................................................................................5 1.2.6 Low-side current sense amplifier (CSA)..............................................................................................................5 1.2.7 PFET gate drivers on VBUS path..........................................................................................................................5 1.2.8 VBUS discharge FETs ...........................................................................................................................................5 1.2.9 Voltage (VBUS) regulation ...................................................................................................................................5 1.3 Integrated digital blocks.........................................................................................................................................5 1.3.1 Serial Communication Blocks (SCB) ...................................................................................................................5 1.3.2 Timer/Counter/PWM Block (TCPWM)..................................................................................................................6 1.4 I/O subsystem .........................................................................................................................................................6 2 Power systems overview .................................................................................................................7 3 Pinouts ..........................................................................................................................................8 4 CCG3PA programming and bootloading ..........................................................................................12 4.1 Programming the device flash over SWD interface.............................................................................................12 4.2 Application firmware update over CC interface ..................................................................................................13 5 Application diagrams ....................................................................................................................14 6 Electrical specifications.................................................................................................................19 6.1 Absolute maximum ratings ..................................................................................................................................19 6.2 Device-level specifications ...................................................................................................................................21 6.2.1 I/O .......................................................................................................................................................................22 6.3 Digital peripherals.................................................................................................................................................25 6.3.1 Pulse Width Modulation (PWM) for GPIO pins ..................................................................................................25 6.3.2 I2C .......................................................................................................................................................................25 6.4 System resources..................................................................................................................................................27 6.4.1 Power-on-reset (POR) with brown out SWD interface .....................................................................................27 6.4.2 Internal main oscillator .....................................................................................................................................28 6.4.3 Internal low-speed oscillator power down.......................................................................................................28 6.4.4 Gate driver specifications..................................................................................................................................31 6.4.5 Analog-to-digital converter ...............................................................................................................................34 6.4.6 Memory...............................................................................................................................................................35 7 Ordering information ....................................................................................................................36 7.1 Ordering code definitions.....................................................................................................................................36 8 Packaging ....................................................................................................................................37 9 Acronyms .....................................................................................................................................40 10 Document conventions................................................................................................................42 10.1 Units of measure .................................................................................................................................................42 Revision history ..............................................................................................................................43 Datasheet 3 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Functional overview 1 Functional overview 1.1 MCU subsystem 1.1.1 CPU The Cortex®-M0 CPU in EZ-PD™ CCG3PA is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. The CPU also includes a serial wire debug (SWD) interface for programming and debugging. The debug configuration used for EZ-PD™ CCG3PA has four breakpoint (address) comparators and two watchpoint (data) comparators. 1.1.2 Flash The EZ-PD™ CCG3PA device has a flash module with one bank of 64-KB flash, a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. 1.1.3 SROM A supervisory ROM that contains boot and configuration routines is provided. 1.2 USB PD subsystem (SS) The USB PD subsystem provides the interface to the Type-C USB port. This subsystem comprises a current sense amplifier, a high-voltage regulator, OVP, OCP, and supply switch blocks. This subsystem also includes all ESD required and supported on the Type-C port. 1.2.1 USB PD physical layer The USB PD physical layer consists of a transmitter and receiver that communicate BMC-encoded data over the CC channel based on the PD 3.1 standard. All communication is half-duplex. The physical layer or PHY implements collision avoidance to minimize communication errors on the channel. The USBPD block includes all termination resistors (RP and RD) and their switches as required by the USB PD spec. RP and RD resistors are required to implement connection detection, plug orientation detection, and for establishing USB DFP/UFP roles. The RP resistor is implemented as a current source. According to the USB Type-C spec, a Type-C controller such as CCG3PA must present certain termination resistors depending on its role in its unpowered state. The sink role in a power bank application requires RD resistors to be present on the CC pins whereas the DFP role, as in a power adapter, requires both CC lines to be open. To be flexible for such applications, CCG3PA includes the resistors required in the unpowered state on separate pads or pins. The dead battery RD resistors are available on separate pads. The dead battery RD is implemented as a bond option on parts for Power Bank applications. In these parts, each CC pin is bonded out together with its corresponding dead battery RD resistor. On part numbers for the DFP application, the CC pins are not bonded with the dead battery RD. 1.2.2 Analog-to-digital converter (ADC) An 8-bit SAR ADC is available for general-purpose A-D conversion applications in the chip. This ADC can be accessed from all GPIOs and the DP/DM pins through an on-chip analog mux. CCG3PA contains two instances of the ADC. The voltage reference for the ADCs is generated either from the VDDD supply or from internal bandgap. When sensing the GPIO pin voltage with an ADC, the pin voltage cannot exceed the VDDIO supply value. 1.2.3 Charger detection The two charger detection blocks connected to the two pairs of DP/DM pins allow CCG3PA to emulate legacy battery chargers conforming to BC 1.2, and the following proprietary charger specifications: Apple, Qualcomm’s QuickCharge 4.0, and Samsung AFC. 1.2.4 VBUS overcurrent and overvoltage protection The CCG3PA chip has an integrated hardware block for VBUS overvoltage protection (OVP)/overcurrent protection (OCP) with configurable thresholds and response times on the Type C port. Datasheet 4 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Functional overview 1.2.5 VBUS short protection CCG3PA provides four VBUS pins tolerant of accidental shorts to high-voltage VBUS: CC1, CC2, P2.2, and P2.3. Accidental shorts may occur because the CC1 and CC2 pins are placed next to the VBUS pins in the USB Type-C connector. A Power Delivery controller without the high-voltage VBUS short protection will be damaged in the event of accidental shorts. When the protection circuit is triggered, CCG3PA can handle up to 17 V forever and between 17 V to 22 V DC for 1000 hours on the overvoltage tolerant (OVT) pins. When a VBUS short event occurs on the CC pins, a temporary high-ringing voltage is observed due to the RLC elements in the USB Type-C cable. Without CCG3PA connected, this ringing voltage can be twice (44 V) the maximum VBUS voltage (21.5 V). However, when CCG3PA is connected, it is capable of clamping temporary high-ringing voltage and protecting the CC pin using IEC ESD protection diodes. 1.2.6 Low-side current sense amplifier (CSA) The CCG3PA chip also has an integrated low-side current sense amplifier that is capable of detecting current levels ranging from 100 mA to 5.5 A across a 5 mΩ external resistor. It also supports constant current mode of operation in power adapter application as a provider. 1.2.7 PFET gate drivers on VBUS path CCG3PA has two integrated PFET gate drivers to drive external PFETs on the VBUS provider and consumer path. The VBUS_P_CTRL gate driver has an active pull-up, and thus can drive high, low or High-Z. The VBUS_C_CTRL gate driver can drive only low or high-Z, thus requiring an external pull-up. These pins are VBUS voltage-tolerant. 1.2.8 VBUS discharge FETs CCG3PA also has two integrated VBUS discharge FETs used to discharge VBUS to meet the USB PD specification timing on a detach condition. VBUS Discharge FET on the provider side can be used to accelerate the ramp down of VBUS to default 5V on the secondary side. 1.2.9 Voltage (VBUS) regulation CCG3PA contains integrated feedback control circuitry (for AC/DC applications) for secondary side control with analog regulation of the feedback/cathode pins to achieve the appropriate voltage on VBUS pin as per the negotiated contract with the peer device over Type-C. 1.3 Integrated digital blocks 1.3.1 Serial Communication Blocks (SCB) EZ-PD™ CCG3PA has two SCBs which can be configured to implement an I2C, SPI, or UART interface. The hardware I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode, the SCB blocks can be configured to act as master or slave. In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C that creates a mailbox address range in the memory of EZ-PD™ CCG3PA and effectively reduce I2C communication to reading from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for clock stretching caused by the CPU not having read data on time. The I2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with GPIO in open-drain modes. The I2C port on the SCB blocks of EZ-PD™ CCG3PA are not completely compliant with the I2C spec in the following aspects: • The GPIO cells for SCB 1’s I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. Datasheet 5 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Functional overview • Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a VOL maximum of 0.6 V. • Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the bus load. 1.3.2 Timer/Counter/PWM Block (TCPWM) EZ-PD™ CCG3PA has four TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals. 1.4 I/O subsystem EZ-PD™ CCG3PA has up to 12 GPIOs of which, some of them can be re-purposed to support functions of SCB (I2C, UART, SPI). GPIO pins P0.0 and P0.1 are overvoltage-tolerant (OVT) (upto 6V). The GPIO block implements the following: • Seven drive strength modes: - Input only - Weak pull-up with strong pull-down - Strong pull-up with weak pull-down - Open drain with strong pull-down - Open drain with strong pull-up - Strong pull-up with strong pull-down - Weak pull-up with weak pull-down • Input threshold select (CMOS or LVTTL) • Individual control of input and output buffer enabling/disabling in addition to the drive strength modes • Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) • Selectable slew rates for dV/dt related noise control to improve EMI During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Port pins P1.0 and P1.1 can be configured to indicate Fault for OCP/SCP/OVP/UVP conditions. Any two fault conditions can be mapped to two GPIOs or all the four faults can be OR’ed to indicate over one GPIO. Datasheet 6 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Power systems overview 2 Power systems overview CCG3PA can operate from two possible external supply sources: VBUS_IN_DISCHARGE (3.0 V–24.5 V) or VDDD (2.7 V–5.5 V). When powered through VBUS_IN_DISCHARGE, the internal regulator generates VDDD of 3.3 V for chip operation. The regulated supply, VDDD, is either used directly inside some analog blocks or further regulated down to VCCD (1.8 V), which powers a majority of the core. CCG3PA has three different power modes: Active, Sleep, and Deep Sleep. Transitions between these power modes are managed by the power system. When powered through the VBUS_IN_DISCHARGE pin, VDDD cannot be used to power external devices and should be connected to a 1-µF capacitor for the regulator stability only. These pins are not supported as power supplies. Refer to the application diagrams for capacitor connections. Table 1 CCG3PA power modes Mode Description Power-on reset (POR) Power is valid and an internal reset source is asserted or SleepController is sequencing the system out of reset. ACTIVE Power is valid and CPU is executing instructions. SLEEP Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated to save power. DEEP SLEEP Main regulator and most blocks are shut off. DeepSleep regulator powers logic, but only low-frequency clock is available. SHV Regulator VBUS_C_MON_ DISCHARGE VBUS_C_CTRL VBUS_IN_DISCHARGE UV/ OVP Gate Driver Gate Driver VBUS_P_CTRL VDDD 1 µF 1.8-V Regulator VCCD 1 µF GPIO VSS Figure 1 Datasheet Core CCG3PA CC Tx/Rx CC1, CC2 VSS Power system requirement block diagram 7 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Pinouts 3 Pinouts Table 2 CCG3PA pin descriptions 24-pin 16-pin QFN SOIC Pin name Description 1 – P1.0 Port 1 pin 0: GPIO/UART_1_CTS/I2C_SDA_1[1] / TCPWM_line_0[2], Programmable SCP/OCP/OVP/UVP Fault indication 2 – P1.1 Port 1 pin 1: GPIO/UART_1_RTS/I2C_SCL_1[1] / TCPWM_line_1[3], Programmable SCP/OCP/OVP/UVP Fault indication 3 5 VBUS_P_CTRL Provider (PMOS) FET control (30-V tolerant) 0: Path ON 1: Path OFF 4 – VBUS_C_CTRL VBUS consumer (PMOS) FET Control (30-V tolerant) 0: Path ON Z: Path OFF 5 – DP1/P1.2 USB D+/Port 1 pin 2: GPIO/UART_1_TX1/AFC/QC/BC 1.2/Apple Charging/No IEC 6 – DM1/P1.3 USB D-/Port 1 pin 3: GPIO/UART_1_RX1/AFC/QC/BC 1.2/Apple Charging/No IEC 7 6 SWD_DAT_0/P0.0 Port 0 pin 0: GPIO/OVT/I2C_SDA_0/TCPWM_line_0/UART_0_CTS 8 7 SWD_CLK_0/P0.1 Port 0 pin 1: GPIO/OVT/I2C_SCL_0/TCPWM_line_1/UART_0_RTS 9 8 AXRES/P2.0 10 – P2.1 Port 2 pin 1: GPIO/TCPWM_line_1//UART_0_RX0 11 9 VBUS_C_MON_ DISCHARGE Type C VBUS monitor with internal discharge FET 12 – P2.2 Port 2 pin 2: GPIO with open drain with pull-up assist. Configurable as GPIO_20VT/I2C_SDA_1/IEC. Tolerant to temporary short to VBUS pin. 13 – P2.3 Port 2 pin 3: GPIO with open drain with pull-up assist. Configurable as GPIO_20VT/I2C_SCL_1/IEC. Tolerant to temporary short to VBUS pin. 14 10 CC2 Communication channel 2 with dead-battery Rd bonding option/IEC. Tolerant to temporary short to VBUS pin. 15 11 CC1 Communication channel 1 with dead-battery Rd bonding option/IEC. Tolerant to temporary short to VBUS pin. 16 12 DM0/P3.1 USB D-/Port 3 pin 1: GPIO/UART_1_RX0/AFC/QC/BC 1.2/Apple Charging/IEC 17 13 DP0/P3.0 USB D+/Port 3 pin 0: GPIO/UART_1_TX0/AFC/QC/BC 1.2/Apple Charging/IEC 18 14 VBUS_IN_DIS CHARGE Port 2 pin 0: GPIO/Alternate XRES[4]/TCPWM_line_0//UART_0_TX0 VBUS Power IN (3.0 V–24.5 V) with Internal Discharge FET Notes 1. Out of the two SCB blocks (SCB0 and SCB1), while the SCB0’s I2C functionality is mapped out to the P0.0/P0.1 GPIO pins, the I2C functionality of SCB1 provides flexibility to have it mapped either on P1.0/P1.1 OR P2.2/P2.3 GPIO pins. 2. TCPWM_line_0 can be mapped to port pins P1.0, P0.0, P2.0 or P2.2. 3. TCPWM_line_1 can be mapped to port pins P1.1, P0.1, P2.1 or P2.3. 4. AXRES pin will be internally pulled up during the Power On I/O initialization time (See Table 7 for more details). 5. See Table 10 and Table 11 for specifications related to these pins. Datasheet 8 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Pinouts Table 2 CCG3PA pin descriptions (continued) 24-pin 16-pin QFN SOIC Pin name Description 19 16 CSP CS +: Current sense input 20 1 FB Voltage regulation feedback pin 21 2 CATH/COMP 22 15 GND Ground 23 3 VDDD Power Input: 2.7 V–5.5 V 24 4 VCCD 1.8-V Core Voltage pin (not intended for use as a power source) – – EPAD Ground Cathode of voltage regulation and compensation for other applications Notes 1. Out of the two SCB blocks (SCB0 and SCB1), while the SCB0’s I2C functionality is mapped out to the P0.0/P0.1 GPIO pins, the I2C functionality of SCB1 provides flexibility to have it mapped either on P1.0/P1.1 OR P2.2/P2.3 GPIO pins. 2. TCPWM_line_0 can be mapped to port pins P1.0, P0.0, P2.0 or P2.2. 3. TCPWM_line_1 can be mapped to port pins P1.1, P0.1, P2.1 or P2.3. 4. AXRES pin will be internally pulled up during the Power On I/O initialization time (See Table 7 for more details). 5. See Table 10 and Table 11 for specifications related to these pins. Datasheet 9 of 45 002-16951 Rev. *H 2022-05-12 Port 24-QFN 16-SOIC SCB function Pin Pin# Pin# UART P0.0 7 6 UART_0_CTS P0.1 8 7 P1.0 TCPWM Fault indicator SPI_1_MOSI I2C_0_ SDA TCPWM_line_0:0 UART_0_RTS SPI_1_MISO I2C_0_ SCL 1 UART_1_CTS SPI_0_SEL P1.1 2 P1.2 Protection capability USB charging signal IEC4 10 of 45 VBUS short OVT AFC QC BC1.2 – – Yes – – – – – TCPWM_line_1:0 – – Yes – – – – – I2C_1_ SDA:1 TCPWM_line_2:1 Yes – - – – – – – UART_1_RTS SPI_0_MISO I2C_1_ SCL:1 TCPWM_line_3:1 Yes – - – – – – – 5 UART_1_TX1 SPI_0_MOSI – – – – – D+ D+ D+ D+ – P1.3 6 UART_1_RX1 SPI_0_CLK – – – – – D- D- D- D- – P2.0 9 UART_0_TX0 SPI_1_SEL – TCPWM_line_2:0 – – – – – – – – P2.1 10 UART_0_RX0 SPI_1_CLK – TCPWM_line_3:0 – – – – – – – – P2.2 12 UART_0_TX1 – I2C_1_ SDA:0 TCPWM_line_0:1 – Yes – – – – – Yes P2.3 13 UART_0_RX1 – I2C_1_ SCL:0 TCPWM_line_1:1 – Yes – – – – – Yes P3.0 17 13 UART_1_TX0 – – – – – – D+ D+ D+ D+ Yes P3.1 16 12 UART_1_RX0 – – – – – – D- D- D- D- Yes 8 SPI I2C Apple EZ-PD™ CCG3PA Consumer USB Type-C port controller GPIO ports, pins and their functionality Pinouts Datasheet Table 3 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Figure 3 Datasheet FB CSP 19 CATH/COMP 21 20 VDDD 23 22 GND VCCD SWD_CLK_0/P0.1 7 8 SWD_DAT_0/P0.0 Figure 2 DM0/P3.1 CC1 CC2 13 12 6 P2.2 DM1/P1.3 DP0/P3.0 15 14 VBUS_C_MON_DISCHARGE DP1/P1.2 4 5 VBUS_C_CTRL VBUS_IN_DISCHARGE 17 16 EPAD P2.1 VBUS_P_CTRL 2 3 18 9 10 11 P1.1 1 AXRES/P2.0 P1.0 24 Pinouts P2.3 Pinout of 24-QFN package (Top view) FB 1 16 CSP CATH/ COMP 2 15 GND VDDD 3 SOIC 14 VBUS _ IN_DISCHARGE 13 DP 0/P 3.0 12 DM0/ P 3.1 VCCD 4 VBUS _P_ CTRL 5 SWD _ DAT_0/ P0.0 6 11 CC 1 SWD _ CLK _0/ P0.1 7 10 CC 2 AXRES/ P2.0 8 9 VBUS _ C_ MON _DISCHARGE ( Top View ) Pinout of 16-SOIC package (Top view) 11 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller CCG3PA programming and bootloading 4 CCG3PA programming and bootloading There are two ways to program application firmware into a CCG3PA device: 1. Programming the device flash over SWD Interface 2. Application firmware update over CC interface Generally, the CCG3PA devices are programmed over SWD interface only during development or during the manufacturing process of the end product. Once the end product is manufactured, the CCG3PA device’s application firmware can be updated via the CC bootloader interface. 4.1 Programming the device flash over SWD interface CCG3PA family of devices can be programmed using the SWD interface. Infineon provides a programming kit (CY8CKIT-002 MiniProg3 kit) called MiniProg3 and PSoC™ Programmer software which can be used to program the flash as well as debug firmware. The flash is programmed by downloading the information from a hex file. This hex file is a binary file generated as an output of building the firmware project in PSoC™ Creator software. Click here for more information on how to use the MiniProg3 programmer. There are many third party programmers that support mass programming in a manufacturing environment. As shown in the block diagram in Figure 4, the SWD_0_DAT and SWD_0_CLK pins are connected to the host programmer’s SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the CCG3PA device has to be powered by the host programmer by connecting its VTARG (power supply to the target device) to VDDD pin of CCG3PA device. While programming over SWD interface, the CCG3PA device cannot receive power through VBUS_IN_DISCHARGE. The CCG3PA device family does not have the XRES pin. Due to that, the XRES line from the host programmer remains unconnected, and hence programming using Reset Mode is not supported. In other words, CCG3PA devices are supported by power cycle programming mode only since XRES line is not used. For more details refer to CYPDxxxx programming specifications. Programming Hardware Target Device from CCG3PA Family (Only Power Cycle Programming Mode Supported) VTARG VDDD SWDCLK SWD_0_CLK SWDIO SWD_0_DAT XRES X GND Datasheet 1 µF 10 V 1 µF 100 nF X7R X7R 10 V 10 V X7R AXRES While programming over SWD interface, device cannot receive power through VBUS_IN_DISHCARGE. VSS GND Figure 4 VCCD Connecting the programmer to CYPD317x device 12 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller CCG3PA programming and bootloading 4.2 Application firmware update over CC interface For bootloading CCG3PA applications, the CY4532 CCG3PA EVK can be used to send programming and configuration data as Infineon specific vendor defined messages (VDMs) over the CC line. The CY4532 CCG3PA EVK’s power board is connected to the system containing CCG3PA device on one end and a Windows PC running the EZ-PD™ Configuration Utility as shown in Figure 5 on the other end to bootload the CCG3PA device. USB Serial Device of CY4532 EVK Power Board PC Running EZ-PD™ Configuration Utility CC Line CCG3 Device on CY4532 EVK Power Board Mini-B Receptacle Figure 5 I2C USB Mini-B cable CY4532 CCG3PA EVK’s Power Board CYPD317x Device to be Bootloaded Type-C Receptacle Application firmware update over CC interface Application firmware (FW) update feature over CC interface is intended for use during development and manufacturing. Infineon strongly recommends customers to use the EZ-PD™ Configuration Utility to turn off the application FW update over CC interface in the firmware that is updated into CCG3PA’s flash before mass production. This prevents unauthorized firmware from being updated over CC-interface in the field. Refer to the knowledge base article KBA230192 on how to configure this in EZ-PD™ Configuration Utility. If you desire to retain the application firmware update over CC interface feature post-production for on-field firmware updates, contact Infineon support for further guidelines. Datasheet 13 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Application diagrams 5 Application diagrams Figure 6 and Figure 7 show the application diagrams of CCG3PA-based power adapter with opto-coupler feedback control using 16-pin SOIC and 24-pin QFN parts respectively. In an opto-feedback power adapter, CCG3PA implements a shunt regulator and the feedback to the primary controller is through an opto-coupler. The current drawn through the CATH path is proportional to the potential difference between FB pin and the internal bandgap reference voltage. At default 5-V VBUS, the FB pin will be held at the voltage set by the bandgap reference voltage using internal VBUS resistor dividers. If VBUS needs to be changed from default 5 V, using internal IDACs and an error amplifier, CCG3PA draws a proportional current through the CATH pin. This in turn gets coupled to the primary controller through the opto-coupler. PFET Load Switch VBUS 50 kΩ 14 5 VBUS_IN_ DISCHARGE 3 1 µF 100 nF VBUS_P_CTRL VBUS_C_MON_ 9 DISCHARGE VDDD 4 VCCD CC1 1 µF CC2 11 C1 1 390 pF 5% X7R FB DP0 DM0 C2 2 CATH/ COMP Note: R1, C1, and C2 values are selected based on primary side controller's design. AXRES/GPIO CSP GND 15 16 5 mΩ SWD_ DAT_0 SWD_ CLK_0 6 7 CC1 10 CYPD3174-16SXQ R1 VBUS CC2 390 pF 5% X7R 13 Type-C Receptacle DP0 12 DM0 8 100 nF GND To Programming Header (Not needed for final production) Figure 6 Datasheet CCG3PA based power adapter application diagram with opto coupler feedback control (16-pin SOIC device) 14 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Application diagrams PFET Load Switch VBUS 50 kΩ 18 3 VBUS_IN_ DISCHARGE 23 1 µF 100 nF 24 4 VBUS_P_CTRL VBUS_C_CTRL GPIO VDDD VBUS_C_MON_ 11 DISCHARGE 15 CC1 14 CC2 VCCD 1 µF 390 pF 5% X7R CYPD3174-24LQXQ 12, 13 R1 C1 GPIO_20VT 20 DP0 FB DM0 C2 Note: R1, C1 and, C2 values are selected based on primary side controller's design. 21 CATH/ COMP AXRES/GPIO CSP GND 22 19 SWD_ DAT_0 SWD_ CLK_0 7 8 VBUS 1, 2, 5, 6, 10 CC1 CC2 390 pF 5% X7R 17 Type-C Receptacle DP0 16 DM0 9 100 nF 5 mΩ GND To Programming Header (Not needed for final production) Figure 7 CCG3PA based power adapter application diagram with opto coupler feedback control (24-pin QFN device) Figure 8 shows the application diagram of CCG3PA based power adapter with direct feedback control. In this application, VBUS is maintained at a constant voltage. The default value of VBUS upon power up (which is usually at 5 V) is set up by choosing the appropriate resistor divider that will set the FB node at a voltage expected by the secondary controller. Feedback node is regulated using internal IDACs. Whenever a change in VBUS voltage is needed, CCG3PA will either source or sink a proportional current at feedback node, based on the amount of voltage change needed. Datasheet 15 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Application diagrams PFET Load Switch VBUS 50 kΩ 18 3 VBUS_IN_ DISCHARGE 23 100 nF 1 µF 24 1 µF VBUS_C_MON_ 11 DISCHARGE VDDD VBUS_C_CTRL VCCD CC1 21 CATH/ COMP 100 nF R1 VBUS_P_CTRL CC2 Secondary Or Integrated Controller 20 FB CYPD3175-24LQXQ 1, 2, 5, 6, 10, 12, 13, R2 Select R1, R2 to get the expected FB voltage at 5V VBUS AXRES/GPIO FB DP0 GPIO DM0 CSP GND 22 19 15 SWD_ DAT_0 SWD_ CLK_0 7 8 CC1 14 390 pF 5% X7R SR VBUS 4 CC2 390 pF 5% X7R 9 17 16 5 mΩ Type-C Receptacle DP0 DM0 GND To Programming Header (Not needed for final production) Figure 8 CCG3PA based power adapter application diagram with direct feedback control Figure 9 shows the application diagram of a CCG3PA based power adapter application with direct feedback control for two port car charger. The car charger application can charge portable devices connected to the Type-C and Type-A port simultaneously. The Type-C port supports USB PD 3.1, QC 4.0, Apple Charging 2.4A, and AFC. The Type-A port supports QC 3.0, Apple Charging, and AFC. Datasheet 16 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Application diagrams DC/DC Regulator 1 VBAT FB PWM PWMI CE Provider FET 1 9 20 2 12 V Supply 21 3.3 V/5 V Regulator 23 2.7 V to 5.5 V 0.1 µF 13 7 8 12 VBUS_C_CTRL P1.0 VBUS_P_CTRL VBUS_IN_DISCHARGE 18 11 VBUS_C_MON_DIS 15 CC1 14 CC2 P2.0/AXRES FB P1.1 COMP CYPD3175-24LQXQ VDDD 10 P0.0/SWD_DAT_0 DP1/P1.2 5 P0.1/SWD_CLK_0 DM1/P1.3 6 GND 22 CC2 390 pF 5% X7R 390 pF 5% X7R Type-C Receptacle 17 DM0/P3.1 VCCD 24 CC1 DPLUS 16 P2.3 P2.2 VBUS DMINUS GND CSP 19 10 mΩ 1% CE PWM PWMI EN P2.1 DP0/P3.0 1 µF 10 V X7R VBAT 4 3 VSEL DC/DC Regulator 2 VBUS DPLUS DMINUS Pins 7 and 8 can also be connected to the programming header (not needed for final production) Figure 9 GND Type-A Receptacle CCG3PA based power adapter application with direct feedback control for two port car charger Figure 10 shows the application diagram of a CCG3PA based power bank application. It shows dual port power bank implementation using CCG3PA device. The power bank application can charge portable devices connected to the Type-C and Type-A port simultaneously. The Type-C port can be configured to support USB PD 3.1, QC 4.0, Apple Charging 2.4A, and AFC. The Type-A port can be configured to support QC3.0, Apple Charging, and AFC. The battery can be charged from Type-C and USB PD power adapters or BC1.2 power adapters. Datasheet 17 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Application diagrams Battery Charger EN Consumer FET ILIM Reg EN Provider FET FB R1 R2 20 2 9 1 5V Regulator Battery 1S/2S 2.7 V to 5.5 V 0.1 µF VBATT 499 kΩ 1% 23 10 Select R1, R2 to get 5 V VBUS 3 FB VBUS_P_CTRL P1.1 VBUS_C_CTRL 18 VBUS_IN_DISCHARGE 11 VBUS_C_MON_DIS 15 CC1 14 CC2 4 P2.0/AXRES P1.0 VDDD P2.1 P2.3 49.9 kΩ 1% VBUS CC1 CC2 390 pF 5% X7R 13 CYPD3171-24LQXQ 21 COMP DP0/P3.0 DM0/P3.1 7 12 P0.0/SWD_DAT_0 DP1/P1.2 P2.2 DM1/P1.3 P0.1/ SWD_CLK_0 VCCD 8 1 µF 10 V X7R PWM/ GPIO FB Reg GND 24 22 17 390 pF 5% X7R Type-C Receptacle DPLUS 16 DMINUS 5 6 GND CSP 19 5 mΩ 1% EN VBUS DPLUS FET DMINUS Type-A Receptacle Pins 7 and 8 can also be connected to the programming header (not needed for final production) Type-A Connect Detect GND Rsense Figure 10 Datasheet CCG3PA power bank application diagram 18 of 45 002-16951 Rev. *H 2022-05-12 EZ-PD™ CCG3PA Consumer USB Type-C port controller Electrical specifications 6 Electrical specifications 6.1 Absolute maximum ratings Table 4 Absolute maximum ratings Parameter VBUS_MAX VDDD_MAX VCC_PIN_ABS VGPIO_ABS IGPIO_ABS IGPIO_injection Description Max supply voltage relative to VSS on VBUS_IN_DISCHARGE and VBUS_C_MON_DISCHARGE pins Max supply voltage relative to VSS Max voltage on CC1, CC2 pins and port pins P2.2 and P2.3 for applicable devices GPIO voltage Maximum current per GPIO GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS VGPIO_OVT_ABS OVT GPIO voltage ESD_HBM ESD_CDM LU Electrostatic discharge human body model Electrostatic discharge charged device model Pin current for latch-up Min Typ Max Units – – 30 V – – 6 V – – 22[6] V –0.5 –25 – – VDDD +0.5 25 V mA –0.5 – 0.5 mA –0.5 – 6 V 2200 –