Datasheet · 2026

Espressif ESP32-S3 Series Datasheet (v2.2)

Dual-core Xtensa LX7 MCU with Wi-Fi and Bluetooth LE; GPIO and ADC limits for the ESP32 alternative to the RP2040.

Author: Espressif Systems
Year: 2026
Type: Datasheet
Credit: Espressif Systems (espressif.com)

esp32-s3
microcontroller
gpio
adc

ESP32-S3 Series Datasheet Version 2.2 Xtensa® 32-bit LX7 dual-core microprocessor 2.4 GHz Wi-Fi (IEEE 802.11b/g/n) and Bluetooth® 5 (LE) Optional 1.8 V or 3.3 V flash and PSRAM in the chip’s package 45 GPIOs QFN56 (7×7 mm) Package Including: ESP32-S3 ESP32-S3FN8 ESP32-S3RH2 ESP32-S3R8 ESP32-S3R16V ESP32-S3FH4R2 ESP32-S3R8V – End of life (EOL) ESP32-S3R2 – End of life (EOL), upgraded to ESP32-S3RH2 www.espressif.com Product Overview ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor (Xtensa® 32-bit LX7), a ULP coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals. The functional block diagram of the SoC is shown below. Espressif ESP32-S3 Wi-Fi + Bluetooth® Low Energy SoC CPU and Memory RF ® JTAG ROM Interrupt Matrix RF Synthesizer SRAM 2.4 GHz Receiver Cache 2.4 GHz Transmitter 2.4 GHz Balun + Switch Xtensa Dual-core 32-bit LX7 Microprocessor Wireless Digital Circuits External Main Clock Wi-Fi MAC Fast RC Oscillator Bluetooth LE Link Controller Phase Lock Loop Bluetooth LE Baseband Peripherals System Timer GDMA Generalpurpose Timers SD/MMC Host Pulse Counter SPI0/1 SPI2/3 I2S USB OTG TWAI® I2C UART LED PWM RMT LCD Interface World Controller Wi-Fi Baseband Security GPIO RTC GPIO DIG ADC RTC ADC HMAC USB Serial/ JTAG eFuse Controller Secure Boot Main System Watchdog Timers RTC Watchdog Timer MCPWM Super Watchdog Touch Sensor Camera Interface RTC I2C Temperature Sensor SHA RSA AES RNG RSA_DS Flash Encryption Permission Control RTC RTC Memory PMU ULP Coprocessor Power consumption Normal Low power consumption components capable of working in Deep-sleep mode ESP32-S3 Functional Block Diagram For more information on power consumption, see Section 4.1.3.5 Power Management Unit (PMU). Espressif Systems 2 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Features Wi-Fi • Complies with IEEE 802.11b/g/n • Supports 20 MHz and 40 MHz bandwidth in 2.4 GHz band • 1T1R mode with data rate up to 150 Mbps • Wi-Fi Multimedia (WMM) • TX/RX A-MPDU, TX/RX A-MSDU • Immediate Block ACK • Fragmentation and defragmentation • Automatic Beacon monitoring (hardware TSF) • Four virtual Wi-Fi interfaces • Simultaneous support for Infrastructure BSS in Station, SoftAP, or Station + SoftAP modes Note that when ESP32-S3 scans in Station mode, the SoftAP channel will change along with the Station channel • Antenna diversity • 802.11mc FTM Bluetooth® • Bluetooth LE: Bluetooth 5, Bluetooth Mesh • High-power mode with up to 20 dBm transmission power • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps • LE Advertising Extensions • Multiple Advertising Sets • LE Channel Selection Algorithm #2 • Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna CPU and Memory • Xtensa® dual-core 32-bit LX7 microprocessor • Clock speed: up to 240 MHz • CoreMark® score: – Two cores at 240 MHz: 1329.92 CoreMark; 5.54 CoreMark/MHz • Five-stage pipeline • 128-bit data bus and dedicated SIMD instructions • Single precision floating point unit (FPU) Espressif Systems 3 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 • Ultra-Low-Power (ULP) coprocessors: – ULP-RISC-V coprocessor – ULP-FSM coprocessor • General DMA controller, with 5 transmit channels and 5 receive channels • L1 cache • ROM: 384 KB • SRAM: 512 KB • SRAM in RTC: 16 KB • 4096-bit eFuse memory, up to 1792 bits for users • Supported SPI protocols: SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to flash, external RAM, and other SPI devices • Flash controller with cache is supported • Flash in-Circuit Programming (ICP) is supported Peripherals • 45 programmable GPIOs – 4 strapping GPIOs – GPIOs allocated for in-package memory: * 6 GPIOs for either in-package flash or PSRAM * 7 GPIOs when both in-package flash and PSRAM are integrated • Connectivity interfaces: – Three UART interfaces – Two I2C interfaces – Two I2S interfaces – LCD interface – 8-bit ~ 16-bit DVP camera interface – Two SPI ports for communication with flash and RAM – Two general-purpose SPI ports – TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) – Full-speed USB OTG – USB Serial/JTAG controller – SD/MMC host controller with 2 slots – LED PWM controller, up to 8 channels – Two Motor Control PWM (MCPWM) Espressif Systems 4 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 – RMT (TX/RX) – Pulse count controller • Analog signal processing: – Two 12-bit SAR ADCs, up to 20 channels – Temperature sensor – 14 capacitive touch sensing IOs • Timers: – Four 54-bit general-purpose timers – 52-bit system timer – Three watchdog timers Power Management • Fine-resolution power control, including clock frequency, duty cycle, Wi-Fi operating modes, and individual internal component control • Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep • Power consumption in Deep-sleep mode is 7 µA • RTC memory remains powered on in Deep-sleep mode Security • Secure boot - permission control on accessing internal and external memory • Flash encryption - memory encryption and decryption • Cryptographic hardware acceleration: – SHA Accelerator (FIPS PUB 180-4) – AES Accelerator (FIPS PUB 197) – RSA Accelerator – HMAC Accelerator – RSA Digital Signature Peripheral (RSA_DS) – Random Number Generator (RNG) RF Module • Antenna switches, RF balun, power amplifier, low-noise receive amplifier • Up to +21 dBm of power for an 802.11b transmission • Up to +19.5 dBm of power for an 802.11n transmission • Up to -104.5 dBm of sensitivity for Bluetooth LE receiver (125 Kbps) Espressif Systems 5 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Applications With low power consumption, ESP32-S3 is an ideal choice for IoT devices in the following areas: • Smart Home • Generic Low-power IoT Sensor Hubs • Industrial Automation • Generic Low-power IoT Data Loggers • Health Care • Cameras for Video Streaming • Consumer Electronics • USB Devices • Smart Agriculture • Speech Recognition • POS Machines • Image Recognition • Service Robot • Wi-Fi + Bluetooth Networking Card • Audio Devices • Touch and Proximity Sensing Espressif Systems 6 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Contents Note: Check the link or the QR code to make sure that you use the latest version of this document: https://www.espressif.com/documentation/esp32-s3_datasheet_en.pdf Contents Product Overview 2 Features 3 Applications 6 1 ESP32-S3 Series Comparison 13 1.1 Nomenclature 13 1.2 Comparison 13 1.3 Chip Revision 14 2 Pins 15 2.1 Pin Layout 15 2.2 Pin Overview 16 2.3 IO Pins 20 2.3.1 IO MUX Functions 20 2.3.2 RTC Functions 23 2.3.3 Analog Functions 24 2.3.4 Restrictions for GPIOs and RTC_GPIOs 25 2.3.5 Peripheral Pin Assignment 26 2.4 Analog Pins 28 2.5 Power Supply 29 2.5.1 Power Pins 29 2.5.2 Power Scheme 29 2.5.3 Chip Power-up and Reset 30 2.6 Pin Mapping Between Chip and Flash/PSRAM 31 3 Boot Configurations 32 3.1 Chip Boot Mode Control 33 3.2 VDD_SPI Voltage Control 34 3.3 ROM Messages Printing Control 34 3.4 JTAG Signal Source Control 34 4 Functional Description 36 4.1 System 36 4.1.1 Microprocessor and Master 36 4.1.1.1 CPU 36 4.1.1.2 Processor Instruction Extensions (PIE) 36 Espressif Systems 7 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Contents 4.1.2 4.1.3 4.1.4 4.2 4.1.1.3 Ultra-Low-Power Coprocessor (ULP) 37 4.1.1.4 GDMA Controller (GDMA) 37 Memory Organization 38 4.1.2.1 Internal Memory 38 4.1.2.2 External Flash and RAM 39 4.1.2.3 Cache 39 4.1.2.4 eFuse Controller 40 System Components 40 4.1.3.1 IO MUX and GPIO Matrix 40 4.1.3.2 Reset 41 4.1.3.3 Clock 41 4.1.3.4 Interrupt Matrix 42 4.1.3.5 Power Management Unit (PMU) 42 4.1.3.6 System Timer 44 4.1.3.7 General Purpose Timers 44 4.1.3.8 Watchdog Timers 45 4.1.3.9 XTAL32K Watchdog Timers 45 4.1.3.10 Permission Control 45 4.1.3.11 World Controller 46 4.1.3.12 System Registers 47 Cryptography and Security Component 47 4.1.4.1 SHA Accelerator 47 4.1.4.2 AES Accelerator 48 4.1.4.3 RSA Accelerator 48 4.1.4.4 Secure Boot 48 4.1.4.5 HMAC Accelerator 49 4.1.4.6 RSA Digital Signature Peripheral (RSA_DS) 49 4.1.4.7 External Memory Encryption and Decryption 49 4.1.4.8 Clock Glitch Detection 50 4.1.4.9 Random Number Generator 50 Peripherals 4.2.1 4.2.2 51 Connectivity Interface 51 4.2.1.1 UART Controller 51 4.2.1.2 I2C Interface 51 4.2.1.3 I2S Interface 52 4.2.1.4 LCD and Camera Controller 52 4.2.1.5 Serial Peripheral Interface (SPI) 53 ® 4.2.1.6 Two-Wire Automotive Interface (TWAI ) 54 4.2.1.7 USB 2.0 OTG Full-Speed Interface 55 4.2.1.8 USB Serial/JTAG Controller 56 4.2.1.9 SD/MMC Host Controller 56 4.2.1.10 Motor Control PWM (MCPWM) 57 4.2.1.11 Remote Control Peripheral (RMT) 58 4.2.1.12 Pulse Count Controller (PCNT) 58 Analog Signal Processing 59 4.2.2.1 59 Espressif Systems SAR ADC 8 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Contents 4.3 4.2.2.2 Temperature Sensor 59 4.2.2.3 Touch Sensor 59 Wireless Communication 61 4.3.1 61 4.3.2 4.3.3 Radio 4.3.1.1 2.4 GHz Receiver 61 4.3.1.2 2.4 GHz Transmitter 61 4.3.1.3 Clock Generator 61 Wi-Fi 61 4.3.2.1 Wi-Fi Radio and Baseband 62 4.3.2.2 Wi-Fi MAC 62 4.3.2.3 Networking Features 62 Bluetooth LE 62 4.3.3.1 Bluetooth LE PHY 63 4.3.3.2 Bluetooth LE Link Controller 63 5 Electrical Characteristics 64 5.1 Absolute Maximum Ratings 64 5.2 Recommended Operating Conditions 64 5.3 VDD_SPI Output Characteristics 65 5.4 DC Characteristics (3.3 V, 25 °C) 65 5.5 ADC Characteristics 66 5.6 Current Consumption 66 5.6.1 Current Consumption in Active Mode 66 5.6.2 Current Consumption in Other Modes 67 5.7 Memory Specifications 68 5.8 Reliability 69 6 RF Characteristics 70 6.1 Wi-Fi Radio 70 6.1.1 Wi-Fi RF Transmitter (TX) Characteristics 70 6.1.2 Wi-Fi RF Receiver (RX) Characteristics 71 6.2 7 Bluetooth LE Radio 72 6.2.1 Bluetooth LE RF Transmitter (TX) Characteristics 73 6.2.2 Bluetooth LE RF Receiver (RX) Characteristics 74 Packaging 77 ESP32-S3 Consolidated Pin Overview 79 Datasheet Versioning 80 Glossary 81 Related Documentation and Resources 82 Revision History 83 Espressif Systems 9 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 List of Tables List of Tables 1-1 ESP32-S3 Series Comparison 13 2-1 Pin Overview 16 2-2 Power-Up Glitches on Pins 18 2-3 Peripheral Signals Routed via IO MUX 20 2-4 IO MUX Functions 21 2-5 RTC Peripheral Signals Routed via RTC IO MUX 23 2-6 RTC Functions 23 2-7 Analog Signals Routed to Analog Functions 24 2-8 Analog Functions 24 2-9 Peripheral Pin Assignment 27 2-10 Analog Pins 28 2-11 Power Pins 29 2-12 Voltage Regulators 29 2-13 Description of Timing Parameters for Power-up and Reset 30 2-14 Pin Mapping Between Chip and Flash or PSRAM 31 3-1 Default Configuration of Strapping Pins 32 3-2 Description of Timing Parameters for the Strapping Pins 33 3-3 Chip Boot Mode Control 33 3-4 VDD_SPI Voltage Control 34 3-5 JTAG Signal Source Control 35 4-1 Components and Power Domains 44 5-1 Absolute Maximum Ratings 64 5-2 Recommended Operating Conditions 64 5-3 VDD_SPI Internal and Output Characteristics 65 5-4 DC Characteristics (3.3 V, 25 °C) 65 5-5 ADC Characteristics 66 5-6 ADC Calibration Results 66 5-7 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode 66 5-8 Current Consumption for Bluetooth LE in Active Mode 67 5-9 Current Consumption in Modem-sleep Mode 67 5-10 Current Consumption in Low-Power Modes 68 5-11 Flash Specifications 68 5-12 PSRAM Specifications 69 5-13 Reliability Qualifications 69 6-1 Wi-Fi RF Characteristics 70 6-2 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 6-3 TX EVM Test1 70 6-4 RX Sensitivity 71 6-5 Maximum RX Level 72 6-6 RX Adjacent Channel Rejection 72 6-7 Bluetooth LE Frequency 72 6-8 Transmitter Characteristics - Bluetooth LE 1 Mbps 73 6-9 Transmitter Characteristics - Bluetooth LE 2 Mbps 73 Espressif Systems 10 Submit Documentation Feedback 70 ESP32-S3 Series Datasheet v2.2 List of Tables 6-10 Transmitter Characteristics - Bluetooth LE 125 Kbps 73 6-11 Transmitter Characteristics - Bluetooth LE 500 Kbps 74 6-12 Receiver Characteristics - Bluetooth LE 1 Mbps 74 6-13 Receiver Characteristics - Bluetooth LE 2 Mbps 75 6-14 Receiver Characteristics - Bluetooth LE 125 Kbps 75 6-15 Receiver Characteristics - Bluetooth LE 500 Kbps 76 7-1 79 Consolidated Pin Overview Espressif Systems 11 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 List of Figures List of Figures 1-1 ESP32-S3 Series Nomenclature 13 2-1 ESP32-S3 Pin Layout (Top View) 15 2-2 ESP32-S3 Power Scheme 30 2-3 Visualization of Timing Parameters for Power-up and Reset 30 3-1 Visualization of Timing Parameters for the Strapping Pins 33 4-1 Address Mapping Structure 38 4-2 Components and Power Domains 43 7-1 77 QFN56 (7×7 mm) Package 7-2 QFN56 (7×7 mm) Package (Only for ESP32-S3FH4R2) Espressif Systems 12 Submit Documentation Feedback 78 ESP32-S3 Series Datasheet v2.2 1 ESP32-S3 Series Comparison 1 ESP32-S3 Series Comparison 1.1 Nomenclature ESP32-S3 F H/N x R H x V 1.8 V external SPI flash only PSRAM size (MB) PSRAM temperature H: High temperature PSRAM Flash size (MB) Flash temperature H: High temperature N: Normal temperature Flash Chip series Figure 1-1. ESP32-S3 Series Nomenclature 1.2 Comparison Table 1-1. ESP32-S3 Series Comparison Part Number1 ESP32-S3 In-Package Flash 2 In-Package PSRAM Ambient Temp. 3 VDD_SPI Voltage 4 Chip Revision –40 ∼ 105 °C 3.3 V/1.8 V v0.1/v0.2 — –40 ∼ 85 °C 3.3 V v0.1/v0.2 2 MB (Quad SPI) –40 ∼ 105 °C 3.3 V v0.2 8 MB (Octal SPI) –40 ∼ 65 °C 3.3 V v0.1/v0.2 — 16 MB (Octal SPI) –40 ∼ 65 °C 1.8 V v0.2 4 MB (Quad SPI) 2 MB (Quad SPI) –40 ∼ 85 °C 3.3 V v0.1/v0.2 — 8 MB (Octal SPI) –40 ∼ 65 °C 1.8 V v0.1/v0.2 — 2 MB (Quad SPI) –40 ∼ 85 °C 3.3 V v0.1/v0.2 — ESP32-S3FN8 8 MB (Quad SPI)5 ESP32-S3RH2 — ESP32-S3R8 — ESP32-S3R16V ESP32-S3FH4R2 ESP32-S3R8V (EOL) ESP32-S3R2 (EOL)6 — 1 For details on chip marking and packing, see Section 7 Packaging. 2 For information about in-package flash, see also Section 4.1.2.1 Internal Memory. By default, the SPI flash on the chip operates at a maximum clock frequency of 80 MHz and does not support the auto suspend feature. If you have a requirement for a higher flash clock frequency of 120 MHz or if you need the flash auto suspend feature, please contact us. 3 Ambient temperature specifies the recommended temperature range of the environment immediately outside an Espressif chip. For chips with Octal SPI PSRAM (ESP32-S3R8, ESP32-S3R8V, and ESP32-S3R16V), if the PSRAM ECC function is enabled, the maximum ambient temperature can be improved to 85 °C, while the usable size of PSRAM will be reduced by 1/16. 4 For more information on VDD_SPI, see Section 2.5 Power Supply. 5 For details about SPI modes, see Section 2.6 Pin Mapping Between Chip and Flash/PSRAM. 6 ESP32-S3R2 has been upgraded to ESP32-S3RH2. For more information, see PCN. Espressif Systems 13 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 1 ESP32-S3 Series Comparison 1.3 Chip Revision As shown in Table 1-1 ESP32-S3 Series Comparison, ESP32-S3 now has multiple chip revisions available on the market using the same part number. For chip revision identification, ESP-IDF release that supports a specific chip revision, and errors fixed in each chip revision, please refer to ESP32-S3 Series SoC Errata. Espressif Systems 14 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2 Pins 43 GPIO38 44 MTCK 45 MTDO 46 VDD3P3_CPU 47 MTDI 48 MTMS 49 U0TXD 50 U0RXD 51 GPIO45 52 GPIO46 53 XTAL_N 54 XTAL_P 55 VDDA 56 VDDA 2.1 Pin Layout LNA_IN 1 42 GPIO37 VDD3P3 2 41 GPIO36 VDD3P3 3 40 GPIO35 CHIP_PU 4 39 GPIO34 GPIO0 5 38 GPIO33 GPIO1 6 37 SPICLK_P GPIO2 7 36 SPICLK_N GPIO3 8 35 SPID GPIO4 9 ESP32-S3 34 SPIQ GPIO5 10 33 SPICLK GPIO6 11 32 SPICS0 GPIO7 12 31 SPIWP GPIO8 13 30 SPIHD 57 GND SPICS1 28 GPIO21 27 GPIO20 26 GPIO19 25 GPIO18 24 GPIO17 23 XTAL_32K_N 22 XTAL_32K_P 21 VDD3P3_RTC 20 GPIO14 19 GPIO13 18 GPIO12 17 GPIO11 16 29 VDD_SPI GPIO10 15 GPIO9 14 Figure 2-1. ESP32-S3 Pin Layout (Top View) Espressif Systems 15 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.2 Pin Overview The ESP32-S3 chip integrates multiple peripherals that require communication with the outside world. To keep the chip package size reasonably small, the number of available pins has to be limited. So the only way to route all the incoming and outgoing signals is through pin multiplexing. Pin muxing is controlled via software programmable registers (see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix). All in all, the ESP32-S3 chip has the following types of pins: • IO pins with the following predefined sets of functions to choose from: – Each IO pin has predefined IO MUX functions – see Table 2-4 IO MUX Functions – Some IO pins have predefined RTC functions – see Table 2-6 RTC Functions – Some IO pins have predefined analog functions – see Table 2-8 Analog Functions Predefined functions means that each IO pin has a set of direct connections to certain on-chip peripherals. During run-time, the user can configure which peripheral from a predefined set to connect to a certain pin at a certain time via memory mapped registers (see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO pins). • Analog pins that have exclusively-dedicated analog functions – see Table 2-10 Analog Pins • Power pins that supply power to the chip components and non-power pins – see Table 2-11 Power Pins Table 2-1 Pin Overview gives an overview of all the pins. For more information, see the respective sections for each pin type below, or ESP32-S3 Consolidated Pin Overview. Table 2-1. Pin Overview Pin Settings 6 Pin Providing Power 2-5 Pin No. Pin Name Pin Type 1 LNA_IN Analog 2 VDD3P3 Power 3 VDD3P3 Power 4 CHIP_PU Analog VDD3P3_RTC 5 GPIO0 IO 6 GPIO1 7 8 Pin Function Sets 1 At Reset After Reset IO MUX RTC IO MUX Analog VDD3P3_RTC WPU, IE WPU, IE IO MUX RTC IO MUX IO VDD3P3_RTC IE IE IO MUX RTC IO MUX Analog GPIO2 IO VDD3P3_RTC IE IE IO MUX RTC IO MUX Analog GPIO3 IO VDD3P3_RTC IE IE IO MUX RTC IO MUX Analog 9 GPIO4 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 10 GPIO5 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 11 GPIO6 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 12 GPIO7 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 13 GPIO8 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 14 GPIO9 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog 15 GPIO10 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog 16 GPIO11 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog 17 GPIO12 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog 18 GPIO13 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog Cont’d on next page Espressif Systems 16 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins Cont’d from previous page Pin Settings 6 Pin No. Pin Name Pin Type Pin Providing Power 2-5 19 GPIO14 IO VDD3P3_RTC 20 VDD3P3_RTC Power 21 XTAL_32K_P IO 22 XTAL_32K_N 23 24 At Reset Pin Function Sets 1 After Reset IO MUX RTC IO MUX Analog IE IO MUX RTC IO MUX Analog VDD3P3_RTC IO MUX RTC IO MUX Analog IO VDD3P3_RTC IO MUX RTC IO MUX Analog GPIO17 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog GPIO18 IO VDD3P3_RTC IE IO MUX RTC IO MUX Analog 25 GPIO19 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 26 GPIO20 IO VDD3P3_RTC IO MUX RTC IO MUX Analog 27 GPIO21 IO VDD3P3_RTC IO MUX RTC IO MUX 28 SPICS1 IO VDD_SPI WPU, IE WPU, IE IO MUX 29 VDD_SPI Power 30 SPIHD IO VDD_SPI WPU, IE WPU, IE IO MUX 31 SPIWP IO VDD_SPI WPU, IE WPU, IE IO MUX 32 SPICS0 IO VDD_SPI WPU, IE WPU, IE IO MUX 33 SPICLK IO VDD_SPI WPU, IE WPU, IE IO MUX 34 SPIQ IO VDD_SPI WPU, IE WPU, IE IO MUX 35 SPID IO VDD_SPI WPU, IE WPU, IE IO MUX 36 SPICLK_N IO VDD_SPI/VDD3P3_CPU IE IE IO MUX 37 SPICLK_P IO VDD_SPI/VDD3P3_CPU IE IE IO MUX 38 GPIO33 IO VDD_SPI/VDD3P3_CPU IE IO MUX 39 GPIO34 IO VDD_SPI/VDD3P3_CPU IE IO MUX 40 GPIO35 IO VDD_SPI/VDD3P3_CPU IE IO MUX 41 GPIO36 IO VDD_SPI/VDD3P3_CPU IE IO MUX 42 GPIO37 IO VDD_SPI/VDD3P3_CPU IE IO MUX 43 GPIO38 IO VDD3P3_CPU IE IO MUX IO MUX USB_PU USB_PU 44 MTCK IO VDD3P3_CPU IE 7 45 MTDO IO VDD3P3_CPU IE IO MUX 46 VDD3P3_CPU Power 47 MTDI IO VDD3P3_CPU IE IO MUX 48 MTMS IO VDD3P3_CPU IE IO MUX 49 U0TXD IO VDD3P3_CPU WPU, IE WPU, IE IO MUX 50 U0RXD IO VDD3P3_CPU WPU, IE WPU, IE IO MUX 51 GPIO45 IO VDD3P3_CPU WPD, IE WPD, IE IO MUX 52 GPIO46 IO VDD3P3_CPU WPD, IE WPD, IE IO MUX 53 XTAL_N Analog 54 XTAL_P Analog 55 VDDA Power 56 VDDA Power 57 GND Power 1. Bold marks the pin function set in which a pin has its default function in the default boot mode. For more information about the boot mode，see Section 3.1 Chip Boot Mode Control. 2. In column Pin Providing Power, regarding pins powered by VDD_SPI: • Power actually comes from the internal power rail supplying power to VDD_SPI. For details, see Section 2.5.2 Power Scheme. 3. In column Pin Providing Power, regarding pins powered by VDD3P3_CPU / VDD_SPI: Espressif Systems 17 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins • Pin Providing Power (either VDD3P3_CPU or VDD_SPI) is decided by eFuse bit EFUSE_PIN_POWER_SELECTION (see ESP32-S3 Technical Reference Manual > Chapter eFuse Controller) and can be configured via the IO_MUX_PAD_POWER_CTRL bit (see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO pins). 4. For ESP32-S3R8V and ESP32-S3R16V chip, as the VDD_SPI voltage has been set to 1.8 V, the working voltage for pins SPICLK_N and SPICLK_P (GPIO47 and GPIO48) would also be 1.8 V, which is different from other GPIOs. 5. The default drive strengths for each pin are as follows: • GPIO17 and GPIO18: 10 mA • GPIO19 and GPIO20: 40 mA • All other pins: 20 mA 6. Column Pin Settings shows predefined settings at reset and after reset with the following abbreviations: • IE – input enabled • WPU – internal weak pull-up resistor enabled • WPD – internal weak pull-down resistor enabled • USB_PU – USB pull-up resistor enabled – By default, the USB function is enabled for USB pins (i.e., GPIO19 and GPIO20), and the pin pull-up is decided by the USB pull-up. The USB pull-up is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up resistor value is controlled by USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-S3 Technical Reference Manual > Chapter USB Serial/JTAG Controller). – When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_FUN_ WPU/WPD). For details, see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix. 7. Depends on the value of EFUSE_DIS_PAD_JTAG • 0 - WPU is enabled • 1 - pin floating Some pins have glitches during power-up. See details in Table 2-2. Table 2-2. Power-Up Glitches on Pins Pin Glitch1 GPIO1 Low-level glitch 60 GPIO2 Low-level glitch 60 GPIO3 Low-level glitch 60 GPIO4 Low-level glitch 60 GPIO5 Low-level glitch 60 GPIO6 Low-level glitch 60 GPIO7 Low-level glitch 60 GPIO8 Low-level glitch 60 GPIO9 Low-level glitch 60 GPIO10 Low-level glitch 60 GPIO11 Low-level glitch 60 GPIO12 Low-level glitch 60 GPIO13 Low-level glitch 60 GPIO14 Low-level glitch 60 XTAL_32K_P Low-level glitch 60 XTAL_32K_N Low-level glitch 60 GPIO17 Low-level glitch 60 Typical Time Period (µs) Cont’d on next page Espressif Systems 18 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins Pin GPIO18 GPIO19 GPIO20 Table 2-2 – cont’d from previous page Glitch1 Typical Time Period (µs) Low-level glitch 60 High-level glitch 60 Low-level glitch 60 High-level glitch2 60 Pull-down glitch High-level glitch2 60 60 1 Low-level glitch: the pin is at a low level output status during the time period; High-level glitch: the pin is at a high level output status during the time period; Pull-down glitch: the pin is at an internal weak pulled-down status during the time period; Pull-up glitch: the pin is at an internal weak pulled-up status during the time period. Please refer to Table 5-4 DC Characteristics (3.3 V, 25 °C) for detailed parameters about low/high-level and pull-down/up. 2 GPIO19 and GPIO20 pins both have two high-level glitches during chip power-up, each lasting for about 60 µs. The total duration for the glitches and the delay are 3.2 ms and 2 ms respectively for GPIO19 and GPIO20. Espressif Systems 19 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.3 IO Pins 2.3.1 IO MUX Functions The IO MUX allows multiple input/output signals to be connected to a single input/output pin. Each IO pin of ESP32-S3 can be connected to one of the five signals (IO MUX functions, i.e., F0-F4), as listed in Table 2-4 IO MUX Functions. Among the five sets of signals: • Some are routed via the GPIO Matrix (GPIO0, GPIO1, etc.), which incorporates internal signal routing circuitry for mapping signals programmatically. It gives the pin access to almost any peripheral signals. However, the flexibility of programmatic mapping comes at a cost as it might affect the latency of routed signals. For details about connecting to peripheral signals via GPIO Matrix, see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix. • Some are directly routed from certain peripherals (U0TXD, MTCK, etc.), including UART0/1, JTAG, SPI0/1, and SPI2 - see Table 2-3 Peripheral Signals Routed via IO MUX. Table 2-3. Peripheral Signals Routed via IO MUX Pin Function Signal U…TXD Transmit data Description U…RXD Receive data U…RTS Request to send U…CTS Clear to send MTCK Test clock MTDO Test Data Out MTDI Test Data In MTMS Test Mode Select SPIQ Master in, slave out SPID Master out, slave in SPI0/1 interface (powered by VDD_SPI) for connection to in-package or SPIHD Hold off-package flash/PSRAM via the SPI bus. It supports 1-, 2-, 4-line SPI SPIWP Write protect modes. See also Section 2.6 Pin Mapping Between Chip and SPICLK Clock Flash/PSRAM SPICS… Chip select SPIIO… Data SPI0/1 interface (powered by VDD_SPI or VDD3P3_CPU) for the higher SPIDQS Data strobe/data mask 4 bits data line interface and DQS interface in 8-line SPI mode SPICLK_N_DIFF Negative clock signal Differential clock negative/positive for the SPI bus SPICLK_P_DIFF Positive clock signal SUBSPIQ Master in, slave out SUBSPID Master out, slave in SUBSPIHD Hold SUBSPIWP Write protect SUBSPICLK Clock SUBSPICS… Chip select SUBSPICLK_N_DIFF Negative clock signal SUBSPICLK_P_DIFF Positive clock signal UART0/1 interface JTAG interface for debugging SPI0/1 interface (powered by VDD3P3_RTC or VDD3V3_CPU) for connection to in-package or off-package flash/PSRAM via the SUBSPI bus. It supports 1-, 2-, 4-line SPI modes Differential clock negative/positive for the SUBSPI bus Cont’d on next page Espressif Systems 20 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins Table 2-3 – cont’d from previous page Pin Function Signal FSPIQ Master in, slave out Description FSPID Master out, slave in FSPIHD Hold SPI2 interface for fast SPI connection. It supports 1-, 2-, 4-line SPI FSPIWP Write protect modes FSPICLK Clock FSPICS0 Chip select FSPIIO… Data The higher 4 bits data line interface and DQS interface for SPI2 interface FSPIDQS Data strobe/data mask in 8-line SPI mode CLK_OUT… Clock output Output clock signals generated by the chip’s internal components Table 2-4 IO MUX Functions shows the IO MUX functions of IO pins. Table 2-4. IO MUX Functions IO MUX Function 1, 2, 3 Pin No. GPIO 2 F0 Type 3 F1 Type F2 5 GPIO0 GPIO0 I/O/T GPIO0 I/O/T 6 GPIO1 GPIO1 I/O/T GPIO1 I/O/T 7 GPIO2 GPIO2 I/O/T GPIO2 I/O/T 8 GPIO3 GPIO3 I/O/T GPIO3 I/O/T 9 GPIO4 GPIO4 I/O/T GPIO4 I/O/T 10 GPIO5 GPIO5 I/O/T GPIO5 I/O/T 11 GPIO6 GPIO6 I/O/T GPIO6 I/O/T 12 GPIO7 GPIO7 I/O/T GPIO7 I/O/T 13 GPIO8 GPIO8 I/O/T GPIO8 I/O/T SUBSPICS1 O/T 14 GPIO9 GPIO9 I/O/T GPIO9 I/O/T SUBSPIHD 15 GPIO10 GPIO10 I/O/T GPIO10 I/O/T FSPIIO4 I1/O/T SUBSPICS0 O/T 16 GPIO11 GPIO11 I/O/T GPIO11 I1/O/T SUBSPID 17 GPIO12 GPIO12 I/O/T GPIO12 I/O/T FSPIIO6 I1/O/T SUBSPICLK O/T 18 GPIO13 GPIO13 I/O/T GPIO13 I/O/T FSPIIO7 I1/O/T SUBSPIQ I1/O/T FSPIQ I1/O/T 19 GPIO14 GPIO14 I/O/T GPIO14 I/O/T FSPIDQS O/T SUBSPIWP I1/O/T FSPIWP I1/O/T 21 GPIO15 GPIO15 I/O/T GPIO15 I/O/T U0RTS O 22 GPIO16 GPIO16 I/O/T GPIO16 I/O/T U0CTS I1 23 GPIO17 GPIO17 I/O/T GPIO17 I/O/T U1TXD O 24 GPIO18 GPIO18 I/O/T GPIO18 I/O/T U1RXD I1 CLK_OUT3 O 25 GPIO19 GPIO19 I/O/T GPIO19 I/O/T U1RTS O CLK_OUT2 O 26 GPIO20 GPIO20 I/O/T GPIO20 I/O/T U1CTS I1 CLK_OUT1 O 27 GPIO21 GPIO21 I/O/T GPIO21 I/O/T 28 GPIO26 SPICS1 O/T GPIO26 I/O/T 30 GPIO27 SPIHD I1/O/T GPIO27 I/O/T 31 GPIO28 SPIWP I1/O/T GPIO28 I/O/T 32 GPIO29 SPICS0 O/T GPIO29 I/O/T 33 GPIO30 SPICLK O/T GPIO30 I/O/T 34 GPIO31 I1/O/T GPIO31 SPIQ I/O/T FSPIIO5 Type F3 Type F4 Type I1/O/T FSPIHD I1/O/T FSPICS0 I1/O/T I1/O/T FSPID I1/O/T FSPICLK I1/O/T I/O/T Cont’d on next page Espressif Systems 21 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins Cont’d from previous page IO MUX Function 1, 2, 3 Pin No. GPIO 2 F0 Type 3 F1 35 GPIO32 SPID I1/O/T 36 GPIO48 SPICLK_N_DIFF O/T GPIO48 I/O/T SUBSPICLK_N_DIFF O/T 37 GPIO47 SPICLK_P_DIFF O/T GPIO47 I/O/T SUBSPICLK_P_DIFF O/T 38 GPIO33 GPIO33 I/O/T GPIO33 I/O/T FSPIHD I1/O/T SUBSPIHD 39 GPIO34 GPIO34 I/O/T GPIO34 I/O/T FSPICS0 I1/O/T SUBSPICS0 O/T 40 GPIO35 GPIO35 I/O/T GPIO35 I/O/T FSPID I1/O/T SUBSPID 41 GPIO36 GPIO36 I/O/T GPIO36 I/O/T FSPICLK I1/O/T SUBSPICLK O/T 42 GPIO37 GPIO37 I/O/T GPIO37 I/O/T FSPIQ 43 GPIO38 GPIO38 I/O/T 44 GPIO39 MTCK 45 GPIO40 47 GPIO41 48 Type F2 Type F3 Type F4 Type GPIO32 I/O/T I1/O/T SPIIO4 I1/O/T SPIIO5 I1/O/T I1/O/T SPIIO6 I1/O/T SPIIO7 I1/O/T I1/O/T SUBSPIQ I1/O/T SPIDQS I0/O/T GPIO38 I/O/T FSPIWP I1/O/T SUBSPIWP I1/O/T I1 GPIO39 I/O/T CLK_OUT3 O MTDO O/T GPIO40 I/O/T CLK_OUT2 O MTDI I1 GPIO41 O GPIO42 MTMS I1 GPIO42 I/O/T 49 GPIO43 U0TXD O GPIO43 I/O/T CLK_OUT1 O 50 GPIO44 U0RXD I1 GPIO44 I/O/T CLK_OUT2 O 51 GPIO45 GPIO45 I/O/T GPIO45 I/O/T 52 GPIO46 GPIO46 I/O/T GPIO46 I/O/T I/O/T CLK_OUT1 SUBSPICS1 O/T 1 Bold marks the default pin functions in the default boot mode. For more information about the boot mode，see Section 3.1 Chip Boot Mode Control. 2 Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and RTC_GPIOs. 3 Each IO MUX function (Fn, n = 0 ~ 4) is associated with a type. The description of type is as follows: • I – input. O – output. T – high impedance. • I1 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always 1. • I0 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always 0. Espressif Systems 22 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.3.2 RTC Functions When the chip is in Deep-sleep mode, the IO MUX described in Section 2.3.1 IO MUX Functions will not work. That is where the RTC IO MUX comes in. It allows multiple input/output signals to be a single input/output pin in Deep-sleep mode, as the pin is connected to the RTC system and powered by VDD3P3_RTC. RTC IO pins can be assigned to RTC functions. They can • Either work as RTC GPIOs (RTC_GPIO0, RTC_GPIO1, etc.), connected to the ULP coprocessor • Or connect to RTC peripheral signals (sar_i2c_scl_0, sar_i2c_sda_0, etc.) - see Table 2-5 RTC Peripheral Signals Routed via RTC IO MUX Table 2-5. RTC Peripheral Signals Routed via RTC IO MUX Pin Function Signal Description sar_i2c_scl… Serial clock sar_i2c_sda… Serial data RTC I2C0/1 interface Table 2-6 RTC Functions shows the RTC functions of RTC IO pins. Table 2-6. RTC Functions RTC Function 2 Pin RTC No. IO Name 1 F0 5 RTC_GPIO0 RTC_GPIO0 sar_i2c_scl_0 6 RTC_GPIO1 RTC_GPIO1 sar_i2c_sda_0 7 RTC_GPIO2 RTC_GPIO2 sar_i2c_scl_1 8 RTC_GPIO3 RTC_GPIO3 sar_i2c_sda_1 9 RTC_GPIO4 RTC_GPIO4 10 RTC_GPIO5 RTC_GPIO5 11 RTC_GPIO6 RTC_GPIO6 12 RTC_GPIO7 RTC_GPIO7 13 RTC_GPIO8 RTC_GPIO8 14 RTC_GPIO9 RTC_GPIO9 15 RTC_GPIO10 RTC_GPIO10 16 RTC_GPIO11 RTC_GPIO11 17 RTC_GPIO12 RTC_GPIO12 18 RTC_GPIO13 RTC_GPIO13 19 RTC_GPIO14 RTC_GPIO14 21 RTC_GPIO15 RTC_GPIO15 22 RTC_GPIO16 RTC_GPIO16 23 RTC_GPIO17 RTC_GPIO17 24 RTC_GPIO18 RTC_GPIO18 25 RTC_GPIO19 RTC_GPIO19 26 RTC_GPIO20 RTC_GPIO20 27 RTC_GPIO21 RTC_GPIO21 F1 F2 F3 1 This column lists the RTC GPIO names, since RTC functions are configured with RTC GPIO registers that use RTC GPIO numbering. 2 Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and RTC_GPIOs. Espressif Systems 23 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.3.3 Analog Functions Some IO pins also have analog functions, for analog peripherals (such as ADC) in any power mode. Internal analog signals are routed to these analog functions, see Table 2-7 Analog Signals Routed to Analog Functions. Table 2-7. Analog Signals Routed to Analog Functions Pin Function Signal Description TOUCH… Touch sensor channel … signal Touch sensor interface ADC…_CH… ADC1/2 channel … signal ADC1/2 interface XTAL_32K_N Negative clock signal 32 kHz external clock input/output XTAL_32K_P Positive clock signal connected to ESP32-S3’s oscillator USB_D- Data - USB_D+ Data + USB OTG and USB Serial/JTAG function Table 2-8 Analog Functions shows the analog functions of IO pins. Table 2-8. Analog Functions Analog Function 1, 2 Pin No. GPIO 3 F0 F1 6 RTC_GPIO1 TOUCH1 ADC1_CH0 7 RTC_GPIO2 TOUCH2 ADC1_CH1 8 RTC_GPIO3 TOUCH3 ADC1_CH2 9 RTC_GPIO4 TOUCH4 ADC1_CH3 10 RTC_GPIO5 TOUCH5 ADC1_CH4 11 RTC_GPIO6 TOUCH6 ADC1_CH5 12 RTC_GPIO7 TOUCH7 ADC1_CH6 13 RTC_GPIO8 TOUCH8 ADC1_CH7 14 RTC_GPIO9 TOUCH9 ADC1_CH8 15 RTC_GPIO10 TOUCH10 ADC1_CH9 16 RTC_GPIO11 TOUCH11 ADC2_CH0 17 RTC_GPIO12 TOUCH12 ADC2_CH1 18 RTC_GPIO13 TOUCH13 ADC2_CH2 19 RTC_GPIO14 TOUCH14 ADC2_CH3 21 RTC_GPIO15 XTAL_32K_P ADC2_CH4 22 RTC_GPIO16 XTAL_32K_N ADC2_CH5 23 RTC_GPIO17 ADC2_CH6 24 RTC_GPIO18 ADC2_CH7 25 RTC_GPIO19 USB_D- ADC2_CH8 26 RTC_GPIO20 USB_D+ ADC2_CH9 1 Bold marks the default pin functions in the default boot mode. For more information about the boot mode，see Section 3.1 Chip Boot Mode Control. 2 This column lists the RTC GPIO names, since analog functions are configured with RTC GPIO registers that use RTC GPIO numbering. 3 Regarding highlighted cells, see Section 2.3.4 Restrictions for GPIOs and RTC_GPIOs. Espressif Systems 24 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.3.4 Restrictions for GPIOs and RTC_GPIOs All IO pins of ESP32-S3 have GPIO and some have RTC_GPIO pin functions. However, the IO pins are multiplexed and can be configured for different purposes based on the requirements. Some IOs have restrictions for usage. It is essential to consider the multiplexed nature and the limitations when using these IO pins. In tables of this chapter, some pin functions are in red or yellow . These functions indicate pins that require extra caution when used as GPIO / GPIO : • IO Pins – allocated for communication with in-package flash/PSRAM and NOT recommended for other uses. For details, see Section 2.6 Pin Mapping Between Chip and Flash/PSRAM. • IO Pins – have one of the following important functions: – Strapping pins – need to be at certain logic levels at startup. See Section 3 Boot Configurations. Note: Strapping pins are highlighted by Pin Name or configurations At Reset, instead of the pin functions. – USB_D+/- – by default, connected to the USB Serial/JTAG Controller. To function as GPIOs, these pins need to be reconfigured via the IO_MUX_MCU_SEL bit (see ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix for details). – JTAG interface – often used for debugging. See Table 2-4 IO MUX Functions. To free these pins up, the pin functions USB_D+/- of the USB Serial/JTAG Controller can be used instead. See also Section 3.4 JTAG Signal Source Control. – UART0 interface – often used for debugging. See Table 2-4 IO MUX Functions. – 8-line SPI interface – no restrictions, unless the chip is connected to flash/PSRAM using 8-line SPI mode. For more information about assigning pins, please see Section 2.3.5 Peripheral Pin Assignment and ESP32-S3 Consolidated Pin Overview. Espressif Systems 25 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 2 Pins 2.3.5 Peripheral Pin Assignment Table 2-9 Peripheral Pin Assignment highlights which pins can be assigned to each peripheral interface according to the following priorities: • Priority 1 (P1) : Fixed pins connected directly to peripheral signals via IO MUX or RTC IO MUX. If a peripheral interface does not have priority 1 pins, such as UART2, it can be assigned to any GPIO pins from priority 2 to priority 4. • Any GPIO pins mapping to peripheral signals via GPIO Matrix, can be priority 2, 3, or 4. – Priority 2 (P2) : GPIO pins can be freely used without restrictions. – Priority 3 (P3) : GPIO pins should be used with caution, as they may conflict with the following important functions described in Section 2.3.4 Restrictions for GPIOs and RTC_GPIOs: * GPIO0, GPIO3, GPIO45, GPIO46 : Strapping pins. * GPIO19, GPIO20 : USB Serial/JTAG interface. * GPIO39, GPIO40, GPIO41, GPIO42 : JTAG interface. * GPIO43, GPIO44 : UART0 interface. * GPIO33, GPIO34, GPIO35, GPIO36, GPIO37 : The higher 4 bits data line interface and DQS interface for the SPI0/1 interface in 8-line SPI mode, and can be GPIO pins if the chip is not connected to flash or PSRAM in 8-line SPI mode. – Priority 4 (P4) : GPIO pins already allocated or not recommended for use, as described in Section 2.3.4 Restrictions for GPIOs and RTC_GPIOs: * GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31, GPIO32 : SPI0/1 interface connected to the in-package flash and PSRAM, or recommended for the off-package flash and PSRAM. If a peripheral interface does not have priority 2 to 4 pins, such as USB Serial/JTAG, it means it can be assigned only to priority 1 pins. Note: • For details about which peripheral signals are connected to IO MUX or RTC IO MUX pins, please refer to Section 2.3.1 IO MUX Functions or Section 2.3.2 RTC Functions. • For details about which peripheral signals can be assigned to GPIO pins, please refer to ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix > Section Peripheral Signal List. Espressif Systems 26 Submit Documentation Feedback ESP32-S3 Series Datasheet v2.2 Pin No. Pin Name USB Serial/JTAG Full-speed USB OTG JTAG ADC1 ADC2 Touc