Datasheet · 2019
H-bridge driver with current sense and regulation; the rejected alternative to the DRV8251A for the solenoid stage (40 V absolute maximum).
Product Order Technical Tools & Support & Folder Now Documents Software Community DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 DRV8874 H-Bridge Motor Driver With Integrated Current Sense and Regulation 1 Features 3 Description 1• N-channel H-bridge motor driver The DRV8874 is an integrated motor driver with N- channel H-bridge, charge pump, current sensing and – Drives one bidirectional brushed DC motor proportional output, current regulation, and protection – Two unidirectional brushed DC motors circuitry. The charge pump improves efficiency by – Other resistive and inductive loads supporting N-channel MOSFET half bridges and 100% duty cycle driving. The family of devices come • 4.5-V to 37-V operating supply voltage range in pin-to-pin RDS(on) variants to support different loads • Pin to pin RDS(on) variants with minimal design changes. – DRV8874: 200-mΩ (High-Side + Low-Side) An internal current mirror architecture on the IPROPI – DRV8876: 700-mΩ (High-Side + Low-Side) pin implements current sensing and regulation. This • High output current capability eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The – DRV8874: 6-A Peak IPROPI current-sense output allows a microcontroller – DRV8876: 3.5-A Peak to detect motor stall or changes in load conditions. • Integrated current sensing and regulation Using the external voltage reference pin, VREF, • Proportional current output (IPROPI) these devices can regulate the motor current during start-up and high-load events without interaction from • Selectable current regulation (IMODE) a microcontroller. – Cycle-by-cycle or fixed off time A low-power sleep mode achieves ultra-low quiescent • Selectable input control modes (PMODE) current draw by shutting down most of the internal – PH/EN and PWM H-bridge control modes circuitry. Internal protection features include supply – Independent half-bridge control mode undervoltage lockout, charge pump undervoltage, output overcurrent, and device overtemperature. • Supports 1.8-V, 3.3-V, and 5-V logic inputs Fault conditions are indicated on nFAULT. • Ultra low-power sleep mode View our full portfolio of brushed motor drivers on – <1-µA @ VVM = 24-V, TJ = 25°C ti.com. • Spread spectrum clocking for low electromagnetic interference (EMI) Device Information (1) • Integrated protection features PART NUMBER PACKAGE BODY SIZE (NOM) – Undervoltage lockout (UVLO) DRV8874 HTSSOP (16) 5.00 mm × 4.40 mm – Charge pump undervoltage (CPUV) (1) For all available packages, see the orderable addendum at the end of the data sheet. – Overcurrent protection (OCP) xx – Automatic retry or outputs latched off Simplified Schematic (IMODE) 4.5 to 37 V – Thermal shutdown (TSD) xx – Automatic fault recovery xxx DRV887x nSLEEP – Fault indicator pin (nFAULT) x x Control Inputs xxx H-Bridge Controller Motor Driver 2 Applications nFAULT • Brushed DC motors Current Sense IPROPI • Major and small home appliances IPROPI • Vacuum, humanoid, and toy robotics RIPROPI Protection • Printers and scanners • Smart meters • ATMs, currency counters, and EPOS • Servo motors and actuators 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com Table of Contents 1 Features .................................................................. 1 8 Application and Implementation ........................ 20 2 Applications ........................................................... 1 8.1 Application Information............................................ 20 3 Description ............................................................. 1 8.2 Typical Application .................................................. 20 4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 30 5 Pin Configuration and Functions ......................... 3 9.1 Bulk Capacitance .................................................... 30 6 Specifications......................................................... 4 10 Layout................................................................... 31 6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 31 6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 31 6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 32 6.4 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 32 6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 32 6.6 Typical Characteristics .............................................. 8 11.3 Community Resources.......................................... 32 7 Detailed Description .............................................. 9 11.4 Trademarks ........................................................... 32 7.1 Overview ................................................................... 9 11.5 Electrostatic Discharge Caution ............................ 32 7.2 Functional Block Diagram ......................................... 9 11.6 Glossary ................................................................ 32 7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable 7.4 Device Functional Modes........................................ 18 Information ........................................................... 33 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2019) to Revision A Page • Changed Current Regulation section with a workaround for transients that are longer than the current regulation deglitch time.......................................................................................................................................................................... 13 • Added additional description to Fixed Off-Time Current Regulation Section ....................................................................... 13 • Changed calculations in Power Dissipation and Output Current Capability ........................................................................ 21 • Added thermal plots for and description for PWP ................................................................................................................ 22 • Added power-up plots........................................................................................................................................................... 26 2 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated DRV8874 www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 5 Pin Configuration and Functions DRV8874 PWP Package 16-Pin HTSSOP With Exposed Thermal Pad Top View EN/IN1 1 16 PMODE PH/IN2 2 15 GND nSLEEP 3 14 CPL nFAULT 4 13 CPH Thermal Pad VREF 5 12 VCP IPROPI 6 11 VM IMODE 7 10 OUT2 OUT1 8 9 PGND Pin Functions PIN TYPE DESCRIPTION NAME PWP CPH 13 PWR Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor CPL 14 PWR between the CPH and CPL pins. EN/IN1 1 I H-bridge control input. See Control Modes. Internal pulldown resistor. GND 15 PWR Device ground. Connect to system ground. Current regulation and overcurrent protection mode. See Current Regulation. Quad-level IMODE 7 I input. IPROPI 6 O Analog current output proportional to load current. See Current Sensing. Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor nFAULT 4 OD for open-drain operation. See Protection Circuits. Sleep mode input. Logic high to enable device. Logic low to enter low-power sleep mode. nSLEEP 3 I See Device Functional Modes. Internal pulldown resistor. OUT1 8 O H-bridge output. Connect to the motor or other load. OUT2 10 O H-bridge output. Connect to the motor or other load. PGND 9 PWR Device power ground. Connect to system ground. PH/IN2 2 I H-bridge control input. See Control Modes. Internal pulldown resistor. PMODE 16 I H-bridge control input mode. See Control Modes. Tri-level input. Charge pump output. Connect a X5R or X7R, 100-nF, 16-V ceramic capacitor between the VCP 12 PWR VCP and VM pins. 4.5-V to 37-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as well as VM 11 PWR sufficient Bulk Capacitance rated for VM. External reference voltage input to set internal current regulation limit. See Current VREF 5 I Regulation. PAD — — Thermal pad. Connect to system ground. Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3 DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply pin voltage VM –0.3 40 V Voltage difference between ground pins GND, PGND –0.3 0.3 V Charge pump pin voltage CPH, VCP VVM – 0.3 VVM + 7 V Charge pump low-side pin voltage CPL –0.3 VVM + 0.3 V EN/IN1, IMODE, nSLEEP, PH/IN2, Logic pin voltage –0.3 5.75 V PMODE Open-drain output pin voltage nFAULT –0.3 5.75 V Output pin voltage OUT1, OUT2 –0.9 VVM + 0.9 V Internally Internally Output pin current OUT1, OUT2 A Limited Limited –0.3 5.75 V Proportional current output pin voltage IPROPI –0.3 VVM + 0.3 V Reference input pin voltage VREF –0.3 5.75 V Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE UNIT Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V(ESD) V discharge Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VM 4.5 37 V VIN Logic input voltage EN/IN1, MODE, nSLEEP, PH/IN2 0 5.5 V fPWM PWM frequency EN/IN1, PH/IN2 0 100 kHz VOD Open drain pullup voltage nFAULT 0 5.5 V IOD Open drain output current nFAULT 0 5 mA IOUT (1) Peak output current OUT1, OUT2 0 6 A IIPROPI Current sense output current IPROPI 0 3 mA VVREF Current limit reference voltage VREF 0 3.6 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) Power dissipation and thermal limits must be observed 4 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated DRV8874 www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 6.4 Thermal Information DRV8874 THERMAL METRIC (1) PWP (HTSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 36.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.3 °C/W RθJB Junction-to-board thermal resistance 11.1 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 11.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics 4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCP, VM) VVM = 24 V, nSLEEP = 0 V, TJ = 25°C 0.75 1 µA IVMQ VM sleep mode current nSLEEP = 0 V 5 µA VVM = 24 V, nSLEEP = 5 V, IVM VM active mode current 3 7 mA EN/IN1 = PH/IN2 = 0 V tWAKE Turnon time VVM > VUVLO, nSLEEP = 5 V to active 1 ms tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms VVCP Charge pump regulator voltage VCP with respect to VM, VVM = 24 V 5 V fVCP Charge pump switching frequency 400 kHz LOGIC-LEVEL INPUTS (EN/IN1, PH/IN2, nSLEEP) VVM < 5 V 0 0.7 VIL Input logic low voltage V VVM ≥ 5 V 0 0.8 VIH Input logic high voltage 1.5 5.5 V 200 mV VHYS Input hysteresis nSLEEP 50 mV IIL Input logic low current VI = 0 V –5 5 µA IIH Input logic high current VI = 5 V 50 75 µA RPD Input pulldown resistance To GND 100 kΩ TRI-LEVEL INPUTS (PMODE) VTIL Tri-level input logic low voltage 0 0.65 V VTIZ Tri-level input Hi-Z voltage 0.9 1.1 1.2 V VTIH Tri-level input logic high voltage 1.5 5.5 V ITIL Tri-level input logic low current VI = 0 V –50 –32 µA ITIZ Tri-level input Hi-Z current VI = 1.1 V –10 10 µA ITIH Tri-level input logic high current VI = 5 V 113 150 µA RTPD Tri-level pulldown resistance To GND 44 kΩ RTPU Tri-level pullup resistance To internal 5 V 156 kΩ QUAD-LEVEL INPUTS (IMODE) VQI2 Quad-level input level 1 Voltage to set quad-level 1 0 0.45 V RQI2 Quad-level input level 2 Resistance to GND to set quad-level 2 18.6 20 21.4 kΩ RQI3 Quad-level input level 3 Resistance to GND to set quad-level 3 57.6 62 66.4 kΩ VQI4 Quad-level input level 4 Voltage to set quad-level 4 2.5 5.5 V RQPD Quad-level pulldown resistance To GND 136 kΩ RQPU Quad-level pullup resistance To internal 5 V 68 kΩ Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 5 DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com Electrical Characteristics (continued) 4.5 V ≤ VVM ≤ 37 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-DRAIN OUTPUTS (nFAULT) VOL Output logic low voltage IOD = 5 mA 0.3 V IOZ Output logic high current VOD = 5 V –2 2 µA DRIVER OUTPUTS (OUT1, OUT2) RDS(on)_HS High-side MOSFET on resistance VVM = 24 V, IO = 2 A, TJ = 25°C 100 120 mΩ RDS(on)_LS Low-side MOSFET on resistance VVM = 24 V, IO = –2 A, TJ = 25°C 100 120 mΩ VSD Body diode forward voltage ISD = 1 A 0.9 V tRISE Output rise time VVM = 24 V, OUTx rising 10% to 90% 150 ns tFALL Output fall time VVM = 24 V, OUTx falling 90% to 10% 150 ns EN/IN1, PH/IN2 to OUTx, 200 Ω from tPD Input to output propagation delay 400 ns OUTx to GND tDEAD Output dead time Body diode conducting 100 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) AIPROPI Current mirror scaling factor 450 µA/A IOUT < 0.4 A –30 30 mA 5.5 V ≤ VVM ≤ 37 V 0.4 A ≤ IOUT < 1 A –7.5 7.5 (1) 5.5 V ≤ VVM ≤ 37 V AERR Current mirror scaling error 1 A ≤ IOUT < 2 A –6 6 % 5.5 V ≤ VVM ≤ 37 V 2 A ≤ IOUT ≤ 4 A –5.5 5.5 5.5 V ≤ VVM ≤ 37 V tOFF Current regulation off time 25 µs tDELAY Current sense delay time 1.6 µs tDEG Current regulation deglitch time 0.6 µs tBLK Current regulation blanking time 1.1 µs PROTECTION CIRCUITS VVM rising 4.3 4.45 4.6 V VUVLO Supply undervoltage lockout (UVLO) VVM falling 4.2 4.35 4.5 V VUVLO_HYS Supply UVLO hysteresis 100 mV tUVLO Supply undervoltage deglitch time 10 µs VCPUV Charge pump undervoltage lockout VCP with respect to VM, VVCP falling 2.25 V IOCP Overcurrent protection trip point 6 10 A tOCP Overcurrent protection deglitch time 3 µs tRETRY Overcurrent protection retry time 2 ms TTSD Thermal shutdown temperature 160 175 190 °C THYS Thermal shutdown hysteresis 20 °C (1) At low currents, the IPROPI output has a fixed offset error with respect to the IOUT current through the low-side power MOSFETs. 6 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated DRV8874 www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 EN/IN1 or PH/IN2 tFALL tRISE ttPDt OUTx (V) ttBLKt ttOFFt ITRIP OUTx (A) tDEG VREF IPROPI (V) ttDELAYt Figure 1. Timing Parameter Diagram Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 7 DRV8874 SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 www.ti.com 6.6 Typical Characteristics 1.4 2 VVM = 4.5 V 1.2 1.75 VVM = 13.5 V VVM = 24 V IVMQ Supply Current (PA) IVMQ Supply Current (PA) 1.5 VVM = 37 V 1 1.25 0.8 1 0.6 0.75 0.4 TJ = -40°C 0.5 TJ = 25°C 0.2 TJ = 125°C 0.25 TJ = 150°C 0 0 0 5 10 15 20 25 30 35 40 -40 -20 0 20 40 60 80 100 120 140 160 VM Supply Voltage (V) 74_I Junction Temperature (°C) 74_I Figure 2. Sleep Current (IVMQ) vs. Supply Voltage (VVM)