Datasheet · 2018

TI DRV2605L 2- to 5.2-V Haptic Driver for LRA and ERM with Effect Library — Datasheet (SLOS854D)

Overdrive and braking, the ERM effect library, LRA auto-resonance 125–300 Hz.

Author: Texas Instruments
Year: 2018
Type: Datasheet
Credit: Texas Instruments (ti.com)

haptic driver
erm
lra
overdrive
braking

Product Folder Order Now Support & Community Tools & Software Technical Documents DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 DRV2605L 2- to 5.2-V Haptic Driver for LRA and ERM with Effect Library and Smart-Loop Architecture 1 Features • 1 • • • • • • • • • • Flexible Haptic and Vibration Driver – LRA (Linear Resonance Actuator) – ERM (Eccentric Rotating Mass) I2C-Controlled Digital Playback Engine – Waveform Sequencer and Trigger – Real-Time Playback Mode through I2C – I2C Dual-Mode Drive (Open and Closed Loop) Smart-Loop Architecture (Patent Pending Control Algorithm) – Automatic Overdrive and Braking – Automatic Resonance Tracking and Reporting (LRA Only) – Automatic Actuator Diagnostic – Automatic Level Calibration – Wide Support for Actuator Models Licensed Immersion TouchSense® 2200 Features: – Integrated Immersion Effect Library – Audio-to-Vibe Drive Compensation Over Battery Discharge Wide Voltage Operation (2 V to 5.2 V) Efficient Differential Switching Output Drive PWM Input with 0% to 100% Duty-Cycle Control Range Hardware Trigger Input Fast Startup Time 1.8-V Compatible, VDD-Tolerant Digital Interface 2 Applications • • • • • • Mobile Phones and Tablets Watches and Wearable Technology Remote Controls, Mice, and Peripheral Devices Touch-Enabled Devices Industrial Human-Machine Interfaces Electronic Point of Sale (ePOS) The DRV2605L device offers a licensed version of TouchSense 2200 software from Immersion which eliminates the requirement to design haptic waveforms because the software includes over 100 licensed effects (6 ERM libraries and 1 LRA library) and audio-to-vibe features. Additionally, the real-time playback mode allows the host processor to bypass the library playback engine and play waveforms directly from the host through I2C. The smart-loop architecture inside the DRV2605L device allows simple auto-resonant drive for the LRA as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. The smart-loop architecture creates a simplified input waveform interface as well as reliable motor control and consistent motor performance. The DRV2605L device also features automatic transition to an open-loop system in the event that an LRA actuator is not generating a valid back-EMF voltage. When the LRA generates a valid back-EMF voltage, the DRV2605L device automatically synchronizes with the LRA. The DRV2605L also allows for open-loop driving through the use of internally-generated PWM. Additionally, the audio-to-vibe mode automatically converts an audio input signal to meaningful tactile effects. For an important notice regarding software, see the Legal Notice section. Device Information(1) PART NUMBER The DRV2605L device is a low-voltage haptic driver that includes a haptic-effect library and provides a closed-loop actuator-control system for high-quality tactile feedback for ERM and LRA. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time and is accessible through a shared I2C compatible bus or PWM input signal. PACKAGE BODY SIZE (MAX) DRV2605L DSBGA (9) 1.50 mm × 1.50 mm DRV2605L VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic VDD ROM Supply correction SDA Gate drive OUT+ 2 I C I/F SCL 3 Description Immersion EN Control and playback engine Back-EMF detection M LRA or ERM IN/TRIG REG REG Gate drive OUT± GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 4 Specifications......................................................... 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements ................................................ 7 Switching Characteristics .......................................... 7 Typical Characteristics .............................................. 9 7 Parameter Measurement Information ................ 10 8 Detailed Description ............................................ 11 7.1 Test Setup for Graphs............................................. 10 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 20 8.5 Programming........................................................... 24 8.6 Register Map........................................................... 35 9 Application and Implementation ........................ 55 9.1 Application Information............................................ 55 9.2 Typical Application .................................................. 56 9.3 Initialization Setup ................................................... 59 10 Power Supply Recommendations ..................... 60 11 Layout................................................................... 61 11.1 Layout Guidelines ................................................. 61 11.2 Layout Example .................................................... 62 12 Device and Documentation Support ................. 63 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... 63 Documentation Support ........................................ 64 Receiving Notification of Documentation Updates 64 Community Resource............................................ 64 Trademarks ........................................................... 64 Electrostatic Discharge Caution ............................ 64 Glossary ................................................................ 64 13 Mechanical, Packaging, and Orderable Information ........................................................... 65 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2014) to Revision D Page • Changed the Handling Ratings table to ESD Ratings and moved the storage temperature to the Absolute Maximum Ratings table .......................................................................................................................................................................... 6 • Changed AC couple capacitor recommendation from 0.1 µF to 1 µF to be consistent with Recommended External Components table in the Waveform Playback Using Audio-to-Vibe Mode .......................................................................... 33 • Changed the DEFAULT value for bit 5-4 of Table 25 From: 1 To 3 ................................................................................... 48 • Changed the DEFAULT value for bit 3-2 of Table 25 From: 2 To 1 ................................................................................... 49 • Changed the DEFAULT value for bit 1-0 of Table 25 From: 2 To 1 ................................................................................... 50 • Changed the typical value of C(VDD) in Table 32 From: 0.1 µF To: 1 µF .............................................................................. 55 Changes from Revision B (June 2014) to Revision C Page • Added VSSOP package option .............................................................................................................................................. 4 • Added IN/TRIG pin connection to GND required if not used.................................................................................................. 4 • Changed connection terminal of input impedance from GND to V(CM_ANA) in Electrical Characteristics section.................... 7 • Added exceptional behavior for I2C Watchdog Timer .......................................................................................................... 19 Changes from Revision A (May 2014) to Revision B Page • Changed the view listed for the DSBGA package drawing from bottom to top...................................................................... 4 • Changed the default value of NG_THRESH[1:0] from 1 to 2 in the Register Map ............................................................. 51 2 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 Changes from Original (May 2014) to Revision A Page • Changed device status from Product Preview to Production Data ....................................................................................... 1 • Changed minimum supported resonant frequency from 50 Hz to 125 Hz ............................................................................ 6 • Added digital pulldown resistance parameter to Electrical Characteristics ............................................................................ 7 • Changed calibration diagram to include DRIVE_TIME into ERM requirements .................................................................. 28 • Changed bitfield name from "LRA_DRIVE_MODE" to "OTP_STATUS".............................................................................. 52 • Changed C(REG) from 0.1 to 1 µF in Figure 60...................................................................................................................... 56 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 3 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com 5 Pin Configuration and Functions YZF Package 9-Pin DSBGA With 0.5-mm Pitch (Top View) 1 2 3 A EN REG OUT+ B IN/TRIG SDA GND C SCL VDD OUT± Not to scale Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION A1 EN I Device enable A2 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required. A3 OUT+ O Positive haptic driver differential output B1 IN/TRIG I Multi-mode Input. I2C selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND B2 SDA I/O I2C data B3 GND P Supply ground C1 SCL I I2C clock C3 OUT– O Negative haptic-driver differential output C2 VDD P Supply input (2 to 5.2 V). A 1-µF capacitor is required. (1) 4 I = input, O = output, I/O = input and output, P = power Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 DGS Package 10-Pin VSSOP (Top View) REG 1 10 VDD SCL 2 9 OUT± SDA 3 8 GND IN/TRIG 4 7 OUT+ EN 5 6 VDD/NC Not to scale Pin Functions PIN TYPE (1) DESCRIPTION NO. NAME 1 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor required 2 SCL I I2C clock 3 SDA I/O I2C data 4 IN/TRIG I Multi-mode Input. I2C is selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND 5 EN I Device enable 6 VDD/NC P Optional supply input. This pin should be tied to VDD or left floating. 7 OUT+ O Positive haptic driver differential output 8 GND P Supply ground 9 OUT– O Negative haptic driver differential output 10 VDD P Supply Input (2 V to 5.2 V). A 1-µF capacitor is required. (1) I = input, O = output, I/O = input and output, P = power Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 5 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range, TA = 25°C (unless otherwise noted) Input voltage MIN MAX UNIT VDD –0.3 5.5 V EN –0.3 VDD + 0.3 V SDA –0.3 VDD + 0.3 V SCL –0.3 VDD + 0.3 V IN/TRIG –0.3 VDD + 0.3 V Operating free-air temperature, TA –40 85 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C 6.2 ESD Ratings VALUE UNIT 9-PIN DSBGA PACKAGE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±250 V 10-PIN VSSOP PACKAGE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 OUT+, OUT– pins (3) ±500 Other pins (1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (1) (2) (3) (2) V ±250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Supply voltage VDD 2 5.2 V ƒ(PWM) PWM input frequency (1) IN/TRIG Pin 10 250 kHz ZL Load impedance (1) VDD = 5.2 V 8 VIL Digital low-level input voltage EN, IN/TRIG, SDA, SCL VIH Digital high-level input voltage EN, IN/TRIG, SDA, SCL VI(ANA) Input voltage (analog mode) IN/TRIG ƒ(LRA) (1) LRA Frequency Range Ω 0.5 1.3 (1) V V 0 1.8 V 125 300 Hz Ensured by design. Not production tested. 6.4 Thermal Information DRV2605L THERMAL METRIC (1) YZF (DSBGA) UNIT (9-PINS) RθJA Junction-to-ambient thermal resistance 145.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W RθJB Junction-to-board thermal resistance 105 °C/W φJT Junction-to-top characterization parameter 5.1 °C/W φJB Junction-to-board characterization parameter 103.3 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 6.5 Electrical Characteristics TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER V(REG) IIL IIH TEST CONDITIONS MIN Voltage at the REG pin Digital low-level input current Digital high-level input current TYP MAX 1.83 UNIT V EN, IN/TRIG, SDA, SCL VDD = 5.2 V , VI = 0 V 1 IN/TRIG, SDA, SCL VDD = 5.2 V, VI = VDD 1 EN VDD = 5.2 V, VI = VDD 3.5 0.4 µA µA VOL Digital low-level output voltage SDAIOL= 4 mA V R(EN-GND) Digital pull-down resistance EN VDD = 5.2 V , VI = VDD 2 I(SD) Shutdown current V(EN) = 0 V 4 II(standby) Standby current V(EN) = 1.8 V, STANDBY = 1 4.1 7 µA IQ Quiescent current V(EN) = 1.8 V, STANDBY = 0, no signal 0.5 0.65 mA ZI Input impedance IN/TRIG to V(CM_ANA) 100 kΩ V(CM_ANA) IN/TRIG common-mode voltage (AC-coupled) AC_COUPLE = 1 0.9 V ZO(SD) Output impedance in shutdown OUT+ to GND, OUT– to GND 15 kΩ ZL(th) Load impedance threshold for over-current detection OUT+ to GND, OUT– to GND 4 Ω I(BAT_AV) Average battery current during operation MΩ 7 µA Duty cycle = 90%, LRA mode, no load 2.4 3.5 Duty cycle = 90%, ERM mode, no load 2.3 3.5 NOM MAX UNIT 400 kHz mA 6.6 Timing Requirements TA = 25°C, VDD = 3.6 V (unless otherwise noted) MIN ƒ(SCL) Frequency at the SCL pin with no wait states tw(H) Pulse duration, SCL high tw(L) Pulse duration, SCL low tsu(1) Setup time, SDA to SCL th(1) 0.6 µs 1.3 µs 100 ns Hold time, SCL to SDA 10 ns t(BUF) Bus free time between stop and start condition 1.3 µs tsu(2) Setup time, SCL to start condition 0.6 µs th(2) Hold time, start condition to SCL 0.6 µs tsu(3) Setup time, SCL to stop condition 0.6 µs See Figure 1. See Figure 2. 6.7 Switching Characteristics TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER t(start) ƒO(PWM) Start-up time TEST CONDITIONS MIN TYP Time from the GO bit or external trigger command to output signal 0.7 Time from EN high to output signal (PWM/Analog Modes) 1.5 PWM Output Frequency MAX ms 19.5 20.5 21.5 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L UNIT kHz 7 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com tw(H) tw(L) SCL tsu(1) th(1) SDA Figure 1. SCL and SDA Timing SCL tsu(2) tsu(3) th(2) t(BUF) SDA Start Condition Stop Condition Figure 2. Timing for Start and Stop Conditions 8 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 6.8 Typical Characteristics Voltage (2V/div) IN/TRIG Acceleration [OUT+] − [OUT−] (Filtered) Voltage (2V/div) IN/TRIG Acceleration [OUT+] − [OUT−] (Filtered) 0 40m 80m VDD = 3.6 V Strong click - 60% 120m Time (s) 160m 200m ERM open loop External edge trigger 0 40m VDD = 3.6 V Strong click - 100% Figure 3. ERM Click with and Without Braking (ROM) 80m 120m Time (s) 160m 200m LRA closed loop External level trigger Figure 4. LRA Click with Braking (ROM) Voltage (2V/div) SDA Acceleration [OUT+] − [OUT−] (Filtered) Voltage (2V/div) SDA Acceleration [OUT+] − [OUT−] (Filtered) 0 200m 400m 600m Time (s) VDD = 3.6 V Sequence = 0x01, 0x48 800m 1 ERM open loop Internal trigger 0 200m 400m 600m Time (s) VDD = 3.6 V Transition click 1 - 100% Figure 5. ERM Click-Bounce (ROM) 800m 1 LRA closed loop Internal trigger Figure 6. LRA Transition-Click (ROM) EN IN/TRIG Acceleration [OUT+] − [OUT−] (Filtered) Voltage (2V/div) Voltage (2V/div) EN SDA Acceleration [OUT+] − [OUT−] (Filtered) 0 40m VDD = 3.6 V 80m 120m Time (s) 160m ERM closed loop 200m RTP Mode 0 40m VDD = 3.6 V 80m 120m Time (s) LRA closed loop 160m 200m PWM Mode Figure 8. LRA Click With and Without Braking (PWM) Figure 7. ERM Buzz (RTP) Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 9 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com Typical Characteristics (continued) 100 ERM mode, RL = 10 : + 100 µH, 1.3 V ERM mode, RL = 25 : + 100 µH, 2 V(RMS) SDA ERM Mode LRA Mode Voltage (2V/div) Supply Current (mA) 90 80 70 60 50 0 1m 2m VDD = 4.2 V 3m 4m 5m 6m Time (s) 7m 8m 9m Closed loop 10m 2 2.4 2.8 3.2 3.6 4 Supply Voltage (V) 4.4 4.8 5.2 D013 No filter Figure 10. Supply Current vs Supply Voltage (Full Vibration) Figure 9. Startup Latency for ERM and LRA 7 Parameter Measurement Information 7.1 Test Setup for Graphs To capture the graphs displayed in the Typical Characteristics section, the following first-order RC-filter setup was used with the exception of the waveform in Figure 9 which was captured without any output filter. This filter is recommended when viewing output signals on an oscilloscope because output PWM modulation is present in all modes. Ensure that effective impedance of the filter is not too low because the closed-loop and auto resonance-tracking features can be affected. Therefore, TI recommends that this exact filter be used for output measurement. Most oscilloscopes have an input impedance of 1 MΩ on each channel and therefore have an approximately 1% loss in measured amplitude because of the voltage-divider effect with the filter. 100 k OUT+ LRA M or ERM OUT± 470 pF 100 k Ch1 Ch2 470 pF Ch1 ± Ch2 (Differential) Oscilloscope Figure 11. Test Setup 7.1.1 Default Test Conditions • VDD = 3.6 V, unless otherwise noted. • Real actuators (as opposed to modeled actuators) were used as loads for both ERM and LRA modes with exception of the Supply Voltage vs Supply Current (Full Vibration) waveform in Figure 10, which used passive RL (resistance in series with an inductance) loads for test repeatability. Real actuators vary widely in supply currents because of variation in back-EMF voltages. Because real actuators have back EMF, the real supply current is generally less than what is shown in the waveform because of the reduction in the apparent load impedance. Therefore, the curve shows the worst-case current. • All ERM library waveforms were taken with Library A in open-loop mode • All LRA library waveforms were taken with the LRA Library in closed-loop mode • All traces are 2 V/div except for the accelerometer traces • All accelerometer traces are 0.87 g/div except for the LRA Click with and without Braking (PWM) curve in Figure 8, which is 1.74 g/div. 10 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 8 Detailed Description 8.1 Overview The DRV2605L device is a low-voltage haptic driver that relies on the back-EMF produced by an actuator to provide a closed-loop system that offers extremely flexible control of LRA and ERM actuators over a shared I2Ccompatible bus or PWM input signal. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time. The improved smart-loop architecture inside the DRV2605L device provides effortless auto-resonant drive for LRA, as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. These features create a simplified input waveform paradigm as well as reliable motor control and consistent motor performance. The DRV2605L device also features an automatic transition to open-loop operation in the event that an LRA actuator is not generating a valid back-EMF voltage and automatic synchronization with the LRA when the LRA is generating a valid back-EMF voltage. The DRV2605L device also allows for open-loop driving by using internally-generated PWM. Additionally, the audio-to-vibe mode automatically converts an audio input signal to meaningful haptic effects. The DRV2605L device offers a licensed version of TouchSense 2200 software from Immersion which eliminates the requirement to design haptic waveforms because the software includes over 100 licensed effects (6 ERM libraries and 1 LRA library) and audio-to-vibe features. The waveforms can be instantly played back through an I2C or can be triggered through a hardware trigger pin. Additionally, the real-time playback mode allows the host processor to bypass the library playback engine and play waveforms directly from the host through the I2C. The DRV2605L device features a trinary-modulated output stage that provides more efficiency than linear-based output drivers. 8.2 Functional Block Diagram VDD ROM Supply correction SDA Gate drive OUT+ 2 I C I/F SCL EN Control and playback engine Back-EMF detection M LRA or ERM IN/TRIG REG REG Gate drive OUT± GND Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 11 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com 8.3 Feature Description 8.3.1 Support for ERM and LRA Actuators The DRV2605L device supports both ERM and LRA actuators. The ERM_LRA bit in register 0x1A must be configured to select the type of actuator that the device uses. 8.3.2 Smart-Loop Architecture The smart-loop architecture is an advanced closed-loop system that optimizes the performance of the actuator and allows for failure detection. The architecture consists of automatic resonance tracking and reporting (for an LRA), automatic level calibration, accelerated startup and braking, diagnostics routines, and other proprietary algorithms. 8.3.2.1 Auto-Resonance Engine for LRA The DRV2605L auto-resonance engine tracks the resonant frequency of an LRA in real time, effectively locking onto the resonance frequency after half of a cycle. If the resonant frequency shifts in the middle of a waveform for any reason, the engine tracks the frequency from cycle to cycle. The auto-resonance engine accomplishes the tracking by constantly monitoring the back-EMF of the actuator. The auto-resonance engine is not affected by the auto calibration process, which is only used for level calibration. No calibration is required for the auto resonance engine. See the Auto-Resonance Engine Programming for the LRA section for auto-resonance engine programming information. 8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA The smart-loop architecture makes the resonant frequency of the LRA available through I2C (see the LRA Resonance Period (Address: 0x22) section). Because frequency reporting occurs in real time, the frequency must be polled while the DRV2605L device synchronizes with the LRA. The data should not be polled when the actuator is idle or braking. 8.3.2.3 Automatic Switch to Open-Loop for LRA In the event that an LRA produces a non-valid back-EMF signal, the DRV2605L device automatically switches to open-loop operation and continues to deliver energy to the actuator in overdrive mode at a default and configurable frequency. Use Equation 1 to calculate the default frequency. If the LRA begins to produce a valid back-EMF signal, the auto-resonance engine automatically takes control and continues to track the resonant frequency in real time. When synchronized, the mode enjoys all of the benefits that the smart-loop architecture has to offer. 1 ¦(LRA_NO-BEMF) | u W(DRIVE_TIME[4:0]) ± W(ZC _ DET _ TIME[1:0]) (1) The DRV2605L device offers an automatic transition to open-loop mode without the re-synchronization option. The feature is enabled by setting the LRA_AUTO_OPEN_LOOP bit in register 0x1F. The transition to open-loop mode only occurs when the driver fails to synchronize with the LRA. The AUTO_OL_CNT[1:0] bit in register 0x1F can be adjusted to set the amount of non-synchronized cycles allowed before the transition to the open-loop mode. Use Equation 2 to calculate the open-loop frequency. The open-loop mode does not receive benefits from the smart-loop architecture, such as automatic overdrive and braking. 1 ¦(LRA_OL) OL_LRA_PERIOD[6:0] × 98.49 × 10 ± (2) 8.3.2.4 Automatic Overdrive and Braking A key feature of the DRV2605L is the smart-loop architecture which employs actuator feedback control for both ERMs and LRAs. The feedback control desensitizes the input waveform from the motor-response behavior by providing automatic overdrive and automatic braking. 12 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 Feature Description (continued) An open-loop haptic system typically drives an overdrive voltage at startup that is higher than the steady-state rated voltage of the actuator to decrease the startup latency of the actuator. Likewise, a braking algorithm must be employed for effective braking. When using an open-loop driver, these behaviors must be contained in the input waveform data. Figure 12 shows how two different ERMs with different startup behaviors (Motor A and Motor B) can both be driven optimally by the smart-loop architecture with a simple input for both motors. The smart-loop architecture works equally well for LRAs with a combination of feedback control and an autoresonance engine. Ideal Open-Loop Waveform for Motor A Ideal Open-Loop Waveform for Motor B Same simple input for both motors Input and output Feedback provides optimum output drive Accleration Output with feedback Figure 12. Waveform Simplification With Smart Loop 8.3.2.4.1 Startup Boost To reduce the actuator start-time performance, the DRV2605L device has an overdrive boost feature that applies higher loop gain to transient response of the actuator. The STARTUP_BOOST bit enables the feature. 8.3.2.4.2 Brake Factor To reduce the actuator brake-time performance, the DRV2605L device provides a means to increase the gain ratio between braking and driving gain. Higher feedback-gain ratios reduce the brake time, however, the gain ratios also reduce the stability of the closed-loop system. The FB_BRAKE_FACTOR[2:0] bits can be adjusted to set the brake factor. 8.3.2.4.3 Brake Stabilizer To improve brake stability at high brake-factor gain ratios, the DRV2605L device has a brake-stabilizer mechanism that automatically reduces the loop gain when the braking is near completion. The BRAKE_STABILIZER bit enables the feature. Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 13 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com Feature Description (continued) 8.3.2.5 Automatic Level Calibration The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction. Auto calibration compensates for the variation and also performs scaling for the desired actuator according to the specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal level at any of the DRV2605L input interfaces supplies the rated voltage to the actuator at steady-state. The feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking, but without allowing the output level to exceed the programmable overdrive clamp voltage. In the event where the automatic level-calibration routine fails, the DIAG_RESULT bit in register 0x00 is asserted to flag the problem. Calibration failures are typically fixed by adjusting the registers associated with the automatic level-calibration routine or, for LRA actuators, the registers associated with the automatic-resonance detection engine. See the Device and Documentation Support section for automatic-level calibration programming. 8.3.2.5.1 Automatic Compensation for Resistive Losses The DRV2605L device automatically compensates for resistive losses in the driver. During the automatic levelcalibration routine, the impedance of the actuator is checked and the compensation factor is determined and stored in the A_CAL_COMP[7:0] bit. 8.3.2.5.2 Automatic Back-EMF Normalization The DRV2605L device automatically compensates for differences in back-EMF magnitude between actuators. The compensation factor is determined during the automatic level-calibration routine and the factor is stored in the A_CAL_BEMF[7:0] bit. 8.3.2.5.3 Calibration Time Adjustment The duration of the automatic level-calibration routine has an impact on accuracy. The impact is highly dependent on the start-time characteristic of the actuator. The auto-calibration routine expects the actuator to have reached a steady acceleration before the calibration factors are calculated. Because the start-time characteristic can be different for each actuator, the AUTO_CAL_TIME[1:0] bit can change the duration of the automatic level-calibration routine to optimize calibration performance. 8.3.2.5.4 Loop-Gain Control The DRV2605L device allows the user to control how fast the driver attempts to match the back-EMF (and thus motor velocity) and the input signal level. Higher loop-gain (or faster settling) options result in less-stable operation than lower loop gain (or slower settling). The LOOP_GAIN[1:0] bit controls the loop gain. 8.3.2.5.5 Back-EMF Gain Control The BEMF_GAIN[1:0] bit sets the analog gain for the back-EMF amplifier. The auto-calibration routine automatically populates the bit with the most appropriate value for the actuator. Modifying the SAMPLE_TIME[1:0] bit also adjusts the back-EMF gain. The higher the sample time, the higher the gain. By default, the back-EMF is sampled once during a period. In the event that a twice per-period sampling is desired, assert the LRA_DRIVE_MODE bit. 8.3.2.6 Actuator Diagnostics The DRV2605L device is capable of determining whether the actuator is not present (open) or shorted. If a fault is detected during the diagnostic process, the DIAG_RESULT bit is asserted. 8.3.2.7 Automatic Re-Synchronization For the LRA, the DRV2605L device features an automatic re-synchronization mode which automatically pushes the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the actuator is at rest when the waveform begins, the DRV2605L device drives in the default direction. 14 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 Feature Description (continued) 8.3.3 Open-Loop Operation for LRA In the event that open-loop operation is desired (such as for off-resonance driving) the DRV2605L device includes an open-loop LRA drive mode that is available through the PWM input or through the digital interface. When using the PWM input in open-loop mode, the DRV2605L device employs a fixed divider that observes the PWM signal and commutates the output drive signal at the PWM frequency divided by 128. To accomplish LRA drive, the host should drive the PWM frequency at 128 times the desired operating frequency. When activated, the digital open-loop mode is available for pre-stored waveforms as well as for RTP mode. The OL_LRA_PERIOD bit in register 0x20 programs the operating frequency, which is derived from the PWM output frequency, ƒO(PWM). Use Equation 1 to calculate the driving frequency. The open-loop mode does not receive the benefits of the smart-loop architecture. 8.3.4 Open-Loop Operation for ERM The DRV2605L device offers ERM open-loop operation through the PWM input. The output voltage is based on the duty cycle of the provided PWM signal, where the OD_CLAMP[7:0] bit in register 0x17 sets the full-scale amplitude. For details see the Rated Voltage Programming section. 8.3.5 Flexible Front-End Interface The DRV2605L device offers multiple ways to launch and control haptic effects. The MODE[2:0] bit in register 0x01 is used to select the interface mode. 8.3.5.1 PWM Interface When the DRV2605L device is in PWM interface mode, the device accepts PWM data at the IN/TRIG pin. The DRV2605L device drives the actuator continuously in PWM interface mode until the user sets the device to standby mode or to enter another interface mode. In standby mode, the strength of vibration is determined by the duty cycle. For the LRA, the DRV2605L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit in register 0x1D is set. If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the frequency of the PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128. 8.3.5.2 Internal Memory Interface The DRV2605L device has seven internal-ROM libraries designed by Immersion called TS2200. The first five libraries and the last library are specifically tuned for six categories of ERMs operated in open-loop mode (see Table 1). Library 6 is a closed-loop library tuned for LRAs. The library selection occurs through register 0x03 (see the Library Selection (Address: 0x03) section). ERM Library A LIBRARY_SEL[2:0] = 1 ERM Library E LIBRARY_SEL[2:0] = 5 LRA Library LIBRARY_SEL[2:0] = 6 ERM Library F LIBRARY_SEL[2:0] = 7 Figure 13. Library Selection Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L 15 DRV2605L SLOS854D – MAY 2014 – REVISED MARCH 2018 www.ti.com Feature Description (continued) Table 1. ERM Library Table LIBRARY RATED VOLTAGE OVERDRIVE VOLTAGE RISE TIME BRAKE TIME A 1.3 V 3V 40 ms to 60 ms 20 ms to 40 ms B 3V 3V 40 ms to 60 ms 5 ms to 15 ms C 3V 3V 60 ms to 80 ms 10 ms to 20 ms D 3V 3V 100 ms to 140 ms 15 ms to 25 ms E 3V 3V > 140 ms > 30 ms F 4.5 V 5V 35 ms to 45 ms 10 ms to 20 ms 8.3.5.2.1 Waveform Sequencer The waveform sequencer queues waveform identifiers for playback. Eight sequence registers queue up to eight waveforms for sequential playback. A waveform identifier is an integer value referring to the index position of a waveform in the ROM library. Playback begins at register address 0x04 when the user asserts the GO bit (register 0x0C). When playback of that waveform ends, the waveform sequencer plays the waveform identifier held in register 0x05 if the next waveform is non-zero. The waveform sequencer continues in this way until it reaches an identifier value of zero or until all eight identifiers are played (register addresses 0x04 through 0x0B), whichever scenario is reached first. The waveform identifier range is 1 to 127. The MSB of each sequence register can implement a delay between sequence waveforms. When the MSB is high, bits [6:0] indicate the length of the wait time. The wait time for that step then becomes WAV_FRM_SEQ[6:0] × 10 ms. 8.3.5.2.2 Library Parameterization The ROM waveforms are augmented by the time offset registers (registers 0x0D to 0x10). The augmentation occurs only for the ROM waveforms and not for the other interfaces (such as PWM and RTP). The purpose of the functionality is to add time stretching (or time shrinking) to the waveform. This functionality is useful for customizing the entire library of waveforms for a specific actuator rise time and fall time. The time parameters that can be stretched or shrunk include: ODT Overdrive time SPT Sustain positive time SNT Sustain Negative Time BRT Brake Time The time values are additive offsets and are 8-bit signed values. The default offset of the time values is 0. Positive values add and negative values subtract from the time value of the effect that is currently played. The most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative value in the waveform is automatically interpreted as the brake time. The time-offset parameters are applied to both voltage-time pairs and linear ramps. For linear ramps, linear interpolation is stretched (or shrunk) over the two operative points for the period (see Equation 3). t + t(ofs) where • t(ofs) is the time offset (3) Changing the playback interval can also manipulate the waveforms stored in memory. Each waveform in memory has a granularity of 5 ms. If the user desires greater granularity, a 1-ms playback interval can be obtained by asserting the PLAYBACK_INTERVAL bit in register 0x1F. 16 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Product Folder Links: DRV2605L DRV2605L www.ti.com SLOS854D – MAY 2014 – REVISED MARCH 2018 8.3.5.3 Real-Time Playback (RTP) Interface The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When realtime playback is enabled, the real-time playback register is sent directly to the playback engine. The amplitude value is played until the user sends the device to standby mode or removes the device from RTP mode. The RTP mode operates exactly like the PWM mode except that