Datasheet · 2016
Integrated low-side peak-and-hold solenoid driver with its own switch and recirculation path.
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 DRV120 Single-Channel Relay, Solenoid, Valve Low-Side Driver With Current Regulation 1 Features 3 Description • The DRV120 device is a PWM current driver for solenoids. The device is designed to regulate the current with a well-controlled waveform to guarantee activation and to reduce power dissipation at the same time. The solenoid current is ramped up fast to ensure opening of the valve or relay. After the initial ramping, solenoid current is kept at peak value to ensure the correct operation, after which it is reduced to a lower hold level in order to avoid thermal problems and reduce power dissipation. 1 • • • • • • • Integrated MOSFET With PWM to Control Solenoid Current – Integrated Sense Resistor for Regulating Solenoid Current Fast Ramp-Up of Solenoid Current to Guarantee Activation Solenoid Current is Reduced in Hold Mode for Lower Power and Thermal Dissipation Peak Current, Keep Time at Peak Current, Hold Current, and PWM Clock Frequency Can Be Set Externally. They Can Also Be Operated at Nominal Values Without External Components. Internal Supply Voltage Regulation – Up to 28-V External Supply Protection – Thermal Shutdown – Undervoltage Lockout (UVLO) – Maximum Ramp Time – Optional STATUS Output Operating Temperature Range: –40ºC to 105ºC 8-Pin and 14-Pin TSSOP Package Options • The DRV120 can operate from an external 6-V to 28-V supply. Device Information(1) PART NUMBER DRV120 PACKAGE BODY SIZE (NOM) TSSOP (14) 5.00 mm × 4.40 mm TSSOP (8) 3.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • The peak current duration is set with an external capacitor. The current ramp peak and hold levels, as well as PWM frequency, can independently be set with external resistors. External setting resistors can also be omitted, if the default values for the corresponding parameters are suitable for the application. Electromechanical Drivers: Solenoids, Valves, Relays White Goods, Solar, Transportation ISOLENOID vs Time ISOLENOID IPEAK IHOLD t tKEEP EN t 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications......................................................... 3 6.1 6.2 6.3 6.4 6.5 6.6 7 Absolute Maximum Ratings ...................................... 3 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Typical Characteristics .............................................. 6 Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 7 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application .................................................. 10 9 Power Supply Recommendations...................... 12 10 Layout................................................................... 12 10.1 Layout Guidelines ................................................. 12 10.2 Layout Example .................................................... 12 11 Device and Documentation Support ................. 13 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ 13 Receiving Notification of Documentation Updates 13 Community Resources.......................................... 13 Trademarks ........................................................... 13 Electrostatic Discharge Caution ............................ 13 Glossary ................................................................ 13 12 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (July 2015) to Revision C Page • Changed the title of the data sheet ........................................................................................................................................ 1 • Changed the minimum ROSC value in the fPWM equation from 66.67 kΩ to 160 kΩ................................................................ 9 • Changed the PWM Clock Frequency Setting graph............................................................................................................... 9 • Added the Receiving Notification of Documentation Updates section ................................................................................. 13 Changes from Revision A (August 2012) to Revision B • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 5 Pin Configuration and Functions PW Package 8-Pin TSSOP Top View PW Package 14-Pin TSSOP Top View KEEP 1 8 EN NC 1 14 NC PEAK 2 7 OUT KEEP 2 13 EN OSC 3 6 NC PEAK 3 12 STATUS VIN 4 5 GND HOLD 4 11 OUT OSC 5 10 NC NC 6 9 NC VIN 7 8 GND Pin Functions PIN NO. NAME I/O DESCRIPTION 8-PIN PW (1) 14-PIN PW EN 8 13 I Enable GND 5 8 — Ground HOLD - 4 I Hold current set KEEP 1 2 I Keep time set NC 6 1, 6, 9, 10, 14 — No connect OSC 3 5 I PWM frequency set OUT 7 11 O Controlled current sink PEAK 2 3 I Peak current set STATUS - 12 O Open-drain fault indicator VIN 4 7 I 6-V to 28-V supply (1) In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings. 6 Specifications 6.1 Absolute Maximum Ratings See (1) and (2) MIN MAX UNIT Input voltage –0.3 28 V Voltage on EN, STATUS, PEAK, HOLD, OSC, SENSE, RAMP –0.3 7 V Voltage on OUT –0.3 28 V TJ Operating virtual junction temperature –40 125 °C Tstg Storage temperature –65 150 °C VIN (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 3 DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM IOUT Average solenoid DC current VIN Supply voltage 6 12 CIN Input capacitor 1 4.7 L Solenoid inductance TA Operating ambient temperature MAX UNIT 125 mA 26 V µF 1 H –40 105 °C 6.4 Thermal Information DRV120 THERMAL METRIC (1) PW [TSSOP] UNIT 8 PINS 14 PINS RθJA Junction-to-ambient thermal resistance 183.8 122.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.2 51.2 °C/W RθJB Junction-to-board thermal resistance 112.6 64.3 °C/W ψJT Junction-to-top characterization parameter 10.4 6.5 °C/W ψJB Junction-to-board characterization parameter 110.9 63.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 6.5 Electrical Characteristics VIN = 14 V, TA = –40°C to 105°C, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Standby current EN = 0, VIN = 14 V 100 150 Quiescent current EN = 1, VIN = 14 V 300 400 1.7 2.5 Ω 20 25 kHz µA CURRENT DRIVER ROUT OUT to GND resistance IOUT = 200 mA fPWM PWM frequency OSC = GND DMAX Maximum PWM duty cycle 100 % DMIN Minimum PWM duty cycle 9 % tD Start-up delay 15 Delay between EN going high until driver enabled (1), fPWM = 20 kHz 25 50 µs CURRENT CONTROLLER, INTERNAL SETTINGS IPEAK Peak current PEAK = GND 160 200 240 mA IHOLD Hold current HOLD = GND 40 50 60 mA CURRENT CONTROLLER, EXTERNAL SETTINGS tKEEP (2) Externally set keep time at peak current IPEAK Externally set peak current IHOLD Externally set hold current fPWM Externally set PWM frequency CKEEP = 1 µF 75 RPEAK = 50 kΩ 250 RPEAK = 200 kΩ 83 RHOLD = 50 kΩ 100 RHOLD = 200 kΩ 33 ROSC = 50 kΩ 60 ROSC = 200 kΩ 20 ms mA mA kHz LOGIC INPUT LEVELS (EN) VIL Input low level VIH Input high level 1.65 1.3 REN Input pullup resistance 350 V V 500 kΩ LOGIC OUTPUT LEVELS (STATUS) VOL Output low level Pulldown activated, ISTATUS = 2 mA IIL Output leakage current Pulldown deactivated, V(STATUS) = 5 V 0.3 V 1 µA UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold 4.6 V THERMAL SHUTDOWN TTSD Junction temperature shutdown threshold 160 °C TTSU Junction temperature start-up threshold 140 °C (1) (2) Logic HIGH between 4 V and 7 V. Note: absolute maximum voltage rating is 7 V. Either internal or external tKEEP time setting is selected to be activated during manufacturing of production version of DRV120. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 5 DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com 6.6 Typical Characteristics Figure 1. Solenoid Current, EN, and PWM vs Time 6 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 7 Detailed Description 7.1 Overview The DRV120 device provides a PWM current converter for use with solenoids. The device provides a quick ramp to a high peak current value in order to ensure opening of the valve or relay. The peak current is held for a programmable time and then released to a lower value to maintain the open state of the valve or relay while reducing the total current consumption. Peak current duration, peak current amount, hold current amount (in the 14-pin package), and PWM frequency can all be controlled by external components or used at default levels by omitting these components (except peak current duration). Enable and disable of the switch is controlled by the EN pin which has an internal pullup to VIN. The DRV120 also features a wide VIN range from 6 V to 28 V. Finally, the 14-pin package features an open-drain pulldown path on the STATUS pin which is enabled as long as undervoltage lockout or thermal shutdown has not triggered. 7.2 Functional Block Diagram ROSC <STATUS> OSC 1 VS VS VIN LDO UVLO Thermal Shutdown OSC LS 500 kW EN D1 OUT PWMCLK 1 uA PWM Control VREF GND MUX VHOLD 1 <RHOLD> RPEAK CKEEP 1 KEEP PEAK <HOLD> 1 VPEAK REF RSENSE 75 mV Available only in the 14-pin package 7.3 Feature Description The DRV120 controls the current through the solenoid as shown in Figure 2. Activation starts when EN pin voltage is pulled high either by an external driver or internal pullup. In the beginning of activation, DRV120 allows the load current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP, before reducing it to IHOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV120 allows the solenoid current to decay to zero. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 7 DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com Feature Description (continued) ISOLENOID IPEAK IHOLD t tKEEP EN t Figure 2. Typical Current Waveform Through the Solenoid tKEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage reaches 75 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. Dependency of tKEEP from the external capacitor size can be calculated with Equation 1. ésù tKEEP éës ùû = CKEEP éëF ùû × 75 × 103 ê ú ëF û (1) The current control loop regulates, cycle-by-cycle, the solenoid current by using an internal current-sensing resistor and MOSFET switch. During the ON-cycle, current flows from OUT pin to GND pin through the internal switch as long as voltage across the current-sensing resistor is less than VREF. As soon as the current sensing voltage is above VREF, the internal switch is immediately turned off until the next ON-cycle is triggered by the internal PWM clock signal. In the beginning of each ON-cycle, the internal switch is turned on and stays on for at least the time determined by the minimum PWM signal duty cycle, DMIN. IPEAK and IHOLD depend on fixed resistance values RPEAK and RHOLD approximately as shown in Figure 3. If the PEAK pin is connected to ground or if RPEAK or RHOLD is below 33.33 kΩ (typical value), then IPEAK is at its default value (internal setting) of 200 mA for IPEAK and 50 mA for IHOLD. The IPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For example, if a 50-kΩ (= RPEAK) resistor is connected between PEAK and GND, then the externally set IPEAK level will be 250 mA. If RPEAK = 200 kΩ is, then the externally set IPEAK level will be 83 mA. In the 8-pin package, IHOLD is set to 50 mA by default. In the 14-pin package, external settings of IHOLD works in the same way as IPEAK. External settings for IPEAK and IHOLD are independent of each other. Approximate IPEAK and IHOLD values can be calculated by using Equation 2 and Equation 3. 250mA IPEAK = × 66.67kW ;66.67kW < RPEAK < 550kW RPEAK (2) I HOLD = 8 100mA × 66.67kW ;66.67kW < RHOLD < 250kW RHOLD Submit Documentation Feedback (3) Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 Feature Description (continued) Figure 3. PEAK and HOLD Mode Current Settings Frequency of the internal PWM clock signal, PWMCLK, that triggers each ON-cycle can be adjusted by external resistor, ROSC, connected between OSC and GND. Frequency as a function of resistor value is shown in Figure 4. Default frequency is used when OSC is connected to GND directly. Use Equation 4 to calculate the PWM frequency as a function of the external fixed adjustment resistor value (greater than 160 kΩ). 60 kHz fPWM = ´ 66.67 kW ; 160 kW < ROSC < 2 MW ROSC (4) 40 35 30 fPWM (kHz) 160 k:, 25 kHz 25 20 15 (0 to 100 :, 20 kHz) 10 5 0 0 100 200 300 400 ROSC (k:) 500 600 700 D001 Figure 4. PWM Clock Frequency Setting Open-drain STATUS output is deactivated if either undervoltage lockout or thermal shutdown blocks have triggered. 7.4 Device Functional Modes The DRV120 transitions through three different states. The first is the OFF state, where the EN pin is low and the PWM output is off. The second is the PEAK state, which begins when the EN pin is pulled high by an external controller or internal pullup, and ends once tKEEP has been reached. During this state, the PWM operates in order to reach the IPEAK set by the RPEAK. Finally, once tKEEP has been reached, the PWM continues to operate, but at the IHOLD level. This continues until the EN pin is forced low again and the PWM turns off. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 9 DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV120 device is designed to operate a solenoid valve or relay. A typical DC input design will be outlined in Typical Application. Approximate resistor and capacitor values for the peak current, hold current, and keep time will be derived for a sample application. 8.2 Typical Application VS LS 1 <STATUS> D1 VIN VS OUT DRV120 VEN EN 1 GND KEEP CKEEP <RHOLD> RPEAK 1 PEAK OSC <HOLD> 1 ROSC Available only in the 14-pin package Figure 5. Default Configuration 8.2.1 Design Requirements The key elements to identify here are the system input voltage, peak current, hold current, and peak keep time values required for the solenoid or relay being used. With these values, approximate RS, RPEAK, RHOLD (for 14-pin package), and CKEEP values can be determined and the proper FET and diode can be identified. ROSC can be varied in order to tune the circuit to the chosen solenoid or relay. 8.2.2 Detailed Design Procedure First, with the known peak current, hold current, and peak keep time values known, the RPEAK, RHOLD (for 14-pin package), and CKEEP values can be determined. Calculation will proceed based on example values shown in Table 1. 10 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 Table 1. Sample Application Values VARIABLE VALUE Peak current 150 mA Hold current 50 mA Keep time 100 ms RPEAK and RHOLD (if applicable) can be determined using Equation 2 and Equation 3. For the sample values, RPEAK is set to 111 kΩ and RHOLD can be shorted to GND. TI recommends that a 0-Ω resistor is used for prototyping in case changes to this value are desired. Next, CKEEP can be set based on Equation 1, 1.33 µF for the sample values. ROSC can initially be shorted to GND, but again a 0-Ω resistor is recommended for prototyping. Additionally, a filter on the SENSE line may be added if it will be in a high-noise environment and is recommended for prototyping. Typical values for this are 1 kΩ and 100 pF. Finally, a current recirculation diode must be chosen based on the current values defined in Table 1. The current recirculation diode should be a fast recovery diode. 8.2.3 Application Curves Lind = 1 H Rind = 50 Ω Figure 6. ISOLENOID, EN, and VIN vs Time Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 11 DRV120 SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 www.ti.com 9 Power Supply Recommendations The input supply range must be at least 6 V and should be below 26 V. An input capacitor of 4.7 µF (typical) is required as well. Current requirements will be set by the required current from the solenoid. 10 Layout 10.1 Layout Guidelines The trace for the solenoid or relay current should be wide in order to prevent any unexpected voltage drop. Diode placement should not be far from the inductor and both should be placed close to the output. 10.2 Layout Example Figure 7. Layout Schematic 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 DRV120 www.ti.com SLVSBG3C – JUNE 2012 – REVISED JUNE 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: Current Controlled Driver for 230V AC Solenoids Reference Design DRV110 and DRV120 Evaluation Modules (EVM) 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. 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Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV120 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number (1) Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) DRV120APWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120A DRV120APWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120A DRV120APWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120A DRV120APWRG4.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120A DRV120PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120 DRV120PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 120 Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 10-Nov-2025 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV120APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 DRV120APWRG4 TSSOP PW 14 2000 330.0 DRV120PWR TSSOP PW 8 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV120APWR TSSOP PW 14 2000 353.0 353.0 32.0 DRV120APWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 DRV120PWR TSSOP PW 8 2000 353.0 353.0 32.0 Pack Materials-Page 2 PACKAGE OUTLINE PW0014A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 12X 0.65 14 1 2X 5.1 4.9 NOTE 3 3.9 4X (0 -12 ) 7 8 14X B 4.5 4.3 NOTE 4 0.30 0.17 0.1 C A B 1.2 MAX (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0 -8 0.75 0.50 DETAIL A A 20 TYPICAL 4220202/B 12/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT PW0014A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE SYMM 14X (1.5) (R0.05) TYP 1 14 14X (0.45) SYMM 12X (0.65) 8 7 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0014A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 14X (1.5) SYMM (R0.05) TYP 1 14X (0.45) 14 SYMM 12X (0.65) 8 7 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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