Manual / Guide · 1991

Amiga Hardware Reference Manual, 3rd Edition

'Reading a light pen': the beam-trigger pin 6, the VPOSR latch and port selection by model. Downsampled to 150 dpi.

Author: Commodore-Amiga, Inc. (Addison-Wesley)
Year: 1991
Type: Manual / Guide
Credit: Commodore-Amiga, Inc. (Addison-Wesley). Copy via the Internet Archive (item 'amiga-hardware-reference-manual-3rd-edition')

amiga
light pen
vposr
beam trigger

AMIGA Hardware Reference Manual AMIGA TECHNICAL REFERENCE SERIES COMMODORE-AMIGA, INC. T H I R D E D I T I O N AMIGA Hardware Reference Manual Third Edition Commodore-Amiga, Inc. AMIGA TECHNICAL REFERENCE SERIES A Addison-Wesley Publishing Company, Inc. Reading, Massachusetts Menlo Park, California New York Don Mills, Ontario Wokingham, England Amsterdam Bonn Sydney Singapore Tokyo Madrid San Juan Paris Seoul Milan Mexico City Taipei Contributors: Joe Augenbraurt, Dan Baker, Greg Berlin, Susan Deyl, Ken Farinsky, Mark Green, Larry Greenley, Dave Haynie, Lee Ho, Glenn Keller, Bill Kolb, Dale Luck, Jay Miner, Dave Needle, Bryce Nesbitt, Rob Peck, Nancy Rains, Chris Raymond, Tom Rokicki, Jez San, Carolyn Scheppner, and Bart Whitebook. Third edition by: Larry Greenley, Mark Green, and Dan Baker Cover designer: Hannus Design Associates Copyright © 1991 by Commodore-Electronics, Ltd. Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this book and Addison-Wesley was aware of a trademark claim, the designations have been printed in initial caps. Amiga, Amiga 500, Amiga 1000, Amiga 2000, and Amiga 3000 are registered trademarks of Commodore-Amiga, Inc. AmigaDOS, Workbench, and Kickstart are trademarks of Commodore-Amiga, Inc. AUTOCONFIG is a trademark of Commodore Elec tronics Limited. 68000, 68010, 68020, 68030, 68040, and Motorola are trademarks of Motorola, Inc. Commodore and the Commodore logo are registered trademarks of Com modore Electronics Limited. CAPE and Inovatronics are trademarks of Inovatronics, Inc. Centronics is a registered trademark of Centronics Data Computer Corp. Hisoft and Devpac Amiga are trademarks of HiSoft. IBM is a registered trademark of International Business Machines Corp. Macintosh is a registered trademark of Apple Computer, Inc. UNIX is a registered trademark of AT&T. All rights reserved. No part of this publication may be reproduced, stored in a retrieval systenv or transmitted, in any form or by any means, electronic, mechanical, photocopy ing, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America. Published simultaneously in Canada. Commodore item number: 327272-05 12345678 9-AL-9594939291 First printing, August 1991 ISBN 0-201-56776-8 WARNING: The information described in this manual may contain errors or bugs, and may not function as described. All information is subject to enhancement or upgrade for any reason including to fix bugs, add features, or change performance. As with all software upgrades, full compatibility, although a goal, cannot be guaranteed, and is in fact unlikely. DISCLAIMER: COMMODORE-AMIGA, INC., (‘COMMODORE1) MAKES NO WARRANTIES, EITHER EXPRESSED OR IMPLIED, OR REPESENTATIONS WITH RESPECT TO THE INFORMATION DESCRIBED HEREIN. SUCH INFORMATION IS PROVIDED ON AN “AS IS" BASIS AND IS EXPRESSLY SUBJECT TO CHANGE WITHOUT NOTICE. IN NO EVENT WILL COMMODORE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES RESULTING FROM ANY CLAIM ARISING OUT OF THE INFORMATION PRESENTED HEREIN, EVEN IF IT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF IMPLIED WARRANTIES OR LIABILITIES FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO THE ABOVE LIMITATION OR EXCLUSION MAY NOT APPLY. C ontents Chapter 1 INTRODUCTION.......................................................................................................... 1 Components of the Amiga............................................................................................................ About the Examples...................................................................................................................... General Amiga Development Guidelines....................................................................................... 1 9 11 Chapter 2 COPROCESSOR HARDWARE................................................................................. 19 About the Copper.......................................................................................................................... What is a Copper Instruction?...................................................................... The MOVE Instruction................................................................................................................. The WAIT Instruction................................................................................................................... Using the Copper Registers............................................................................................................ Putting Together a Copper Instruction List..................................................................................... Starting and Stopping the Copper.................................................................................................. Advanced Topics........................................................................................................................... Summary of Copper Instructions................................................................................................... 19 20 21 22 25 26 30 31 36 Chapter 3 PLAYFIELD HARDWARE........................................................................................... 39 About Amiga Playfields................................................................................................................ Forming a Basic Playfield............................................................................................................. Forming a Dual-playfield Display........................................................................................... Bitplanes and Display Windows of All Sizes................................................................................. Moving (Scrolling) Playfields........................................................................................................ Advanced Topics........................................................................................................................... Summary of Playfield Registers..................................................................................................... Summary of Color Selection Registers.......................................................................................... 40 44 67 73 80 86 89 92 Chapter 4 SPRITE HARDWARE................................................................................................. 97 What are Sprites?.......................................................................................................................... Forming a Sprite............................................................................................................................ Displaying a Sprite........................................................................................................................ Moving a Sprite............................................................................................................................. Creating Additional Sprites........................................................................................................... Reusing Sprite DMA Channels...................................................................................................... Overlapped Sprites........................................................................................................................ Attached Sprites............................................................................................................................ Manual Mode................................................................................................................................ Sprite Hardware Details................................................................................................................ Summary of Sprite Registers......................................................................................................... Summary of Sprite Color Registers............................................................................................... 97 98 109 113 114 116 118 120 123 124 127 130 iii Chapters AUDIO HARDWARE................................................................................................... 133 Introducing Sound Generation...................................................................................................... Forming and Playing a Sound....................................................................................................... Producing Complex Sounds.......................................................................................................... Producing High-quality Sound...................................................................................................... Using Direct (Non-DMA) Audio Output....................................................................................... The Equal-tempered Musical Scale............................................................................................... Decibel Values for Volume Ranges............................................................................................... The Audio State Machine.............................................................................................................. 134 137 147 152 157 158 163 164 Chapters BLITTER HARDWARE............................................................................................... 169 What is the Blitter?....................................................................................................................... 169 Memory Layout............................................................................................................................. 170 DMA Channels............................................................................................................................. 170 Function Generator........................................................................................................................ 174 Shifts and Masks........................................................................................................................... 179 Descending Mode.......................................................................................................................... 182 Copying Arbitrary Regions........................................................................................................... 183 Area Fill Mode............................................................................................................................. 184 Blitter Done Flag........................................................................................................................... 186 Interrupt Rag................................................................................................................................ 187 Zero Flag...................................................................................................................................... 187 Pipeline Register........................................................................................................................... 188 Line Mode.................................................................................................................................... 189 Blitter Speed................................................................................................................................. 193 Blitter Operations and System DMA............................................................................................. 194 Blitter Block Diagram................................................................................................................... 198 Blitter Key Points.......................................................................................................................... 200 Chapter 7 SYSTEM CONTROL HARDWARE............................................................................. 207 Video Priorities............................................................................................................................. 207 Collision Detection....................................................................................................................... 213 Beam Position Detection............................................................................................................... 216 Interrupts...................................................................................................................................... 217 DMA Control............................................................................................................................... 222 Reset and Early Startup Operation................................................................................................. 223 Chapters INTERFACE HARDWARE........................................................................................... 227 Controller Port Interface............................................................................................................... 227 Hoppy Disk Controller................................................................................................................. 241 The Keyboard............................................................................................................................... 251 Serial I/O Interface........................................................................................................................ 255 Parallel I/O Interface..................................................................................................................... 259 Display Output Connections......................................................................................................... 260 Appendix A REGISTER SUMMARY ALPHABETICAL ORDER............................................... 263 Appendix B REGISTER SUMMARY ADDRESS ORDER.......................................................... 287 tv Appendix C ENHANCED CHIP SET............................................................................................ 295 New Features of the Enhanced Chip Set................................. 295 ECS Registers............................................................................................................................... 298 Appendix D SYSTEM MEMORY MAPS...................................................................................... 313 Appendix E I/O CONNECTORS AND INTERFACES................................................................. 317 Appendix F 8520 COMPLEX INTERFACE ADAPTERS........................................................... 339 Chip Register Map........................................................................................................................ 340 Register Functional Description..................................................................................................... 341 Time of Day Clock........................................................................................................................ 344 Serial Shift Register (SDR)............................................................................................................ 345 Interrupt Control Register (ICR).................................................................................................... 346 Control Registers........................................................................................................................... 348 Port Signal Assignments................................................................................................................ 350 Hardware Connection Details........................................................................................................ 353 Appendix G KEYBOARD INTERFACE....................................................................................... 357 Keyboard Communications............................................................................................................ Keycodes....................................................................................................................................... Caps Lock Key.............................................................................................................................. “ Out-of-Sync” Condition............................................................................................................. Power-Up Sequence...................................................................................................................... Reset Warning............................................................................................................................... Hard Reset..................................................................................................................................... Matrix Table.................................................................................................................................. Special Codes................................................................................................................................ 357 358 359 359 360 361 361 362 364 Appendix H EXTERNAL DISK CONNECTOR INTERFACE..................................................... 367 General.......................................................................................................................................... 367 Summary Table............................................................................................................................. 367 Signals When Driving a Disk......................................................................................................... 368 Device I.D..................................................................................................................................... 370 Appendix I HARDWARE EXAMPLE INCLUDE FILE................................................................. 373 Appendix J CUSTOM CHIP PIN ALLOCATION LIST............................................................... 379 Appendix K ZORRO EXPANSION BUS...................................................................................... 383 Zorro II Compatibility.................................................................................................................... 387 Zorro III Bus Architecture............................................................................................................. 399 Signal Description......................................................................................................................... 409 Timing........................................................................................................................................... 416 Electrical Specifications................................................................................................................. 424 Mechanical Specifications.............................................................................................................. 427 AUTOCONFIG™.......................................................................................................................... 430 Physical and Logical Signal Names............................................................................................... 437 Zorro III Implementations.............................................................................................................. 439 v Glossary........................................................................................................................................... 441 Index.................................................................................................................................................. 455 vi L ist of F igures Figure 1-1 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Figure 3-25 Figure 3-26 Figure 3-27 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 5-1 Figure 5-2 Figure 5-3 Block Diagram for the Amiga Computer Family............................................................ Interlaced Bitplane in RAM........................................................................................... How the Video Display Picture Is Produced................................................................... What Is a Pixel?............................................................................................................ How Bitplanes Select a Color........................................................................................ Significance of Bitplane Data in Selecting Colors........................................................... Interlacing..................................................................................................................... Effect of Interlaced Mode on Edges of Objects.............................................................. Memory Organization for a Basic Bitplane.................................................................... Combining Bitplanes..................................................................................................... Positioning the On-screen Display.................................................................................. Data Fetched for the First Line When Modulo = 0.......................................................... Data Fetched for the Second Line When Modulo = 0 ..................................................... A Dual-playfield Display............................................................................................... How Bitplanes Are Assigned to Dual Playfields............................................................. Memory Picture Larger than the Display........................................................................ Data Fetch for the First Line When Modulo = 40............................................................ Data Fetch for the Second Line When Modulo = 40....................................................... Data Layout for First Line—Right Half of Big Picture.................................................. Data Layout for Second Line—Right Half of Big Picture.............................................. Display Window Horizontal Starting Position................................................................. Display Window Vertical Starting Position.................................................................... Display Window Horizontal Stopping Position............................................................... Display Window Vertical Stopping Position................................................................... Vertical Scrolling........................................................................................................... Horizontal Scrolling....................................................................................................... Memory Picture Larger Than the Display Window......................................................... Data for Line 1 - Horizontal Scrolling............................................................................ Data for Line 2—Horizontal Scrolling........................................................................... Defining Sprite On-screen Position................................................................................. Position of Sprites.......................................................................................................... Shape of Spaceship........................................................................................................ Sprite with Spaceship Shape Defined............................................................................. Sprite Color Definition................................................................................................... Color Register Assignments............................................................................................ Data Structure Layout.................................................................................................... Sprite Priority................................................................................................................. Typical Example of Sprite Reuse.................................................................................... Typical Data Structure for Sprite Re-use........................................................................ Overlapping Sprites (Not Attached)................................................................................ Placing Sprites Next to Each Other................................................................................. Sprite Control Circuitry................................................................................................. Sine Waveform.............................................................................................................. Digitized Amplitude Values............................................................................................ Example Sine Wave....................................................................................................... vii 8 34 40 41 43 44 50 50 54 56 58 61 61 68 69 73 74 74 75 75 77 77 78 79 81 83 84 84 84 98 100 101 101 102 103 106 115 116 117 119 120 125 134 136 142 Figure 5-4 Waveform with Multiple Cycles.................................................................................... 153 Figure 5-5 Frequency Domain Plot of Low-Pass Filter.................................................................... 155 Figure 5-6 Noise-free Output (No Aliasing Distortion)................................................................... 155 Figure 5-7 Some Aliasing Distortion............................................................................................... 156 Figure 5-8 Audio State Diagram...................................................................................................... 166 Figure 6-1 How Images are Stored in Memory................................................................................ 171 Figure 6-2 BLTxPTR and BLTxMOD calculations......................................................................... 173 Figure 6-3 Blitter Minterm Venn Diagram...................................................................................... 178 Figure 6-4 Extracting a Range of Columns..................................................................................... 181 Figure 6-5 Use of the FCI Bit - Bit Is a 0 ........................................................................................ 185 Figure 6-6 Use of the FCI Bit - Bit Is a 1........................................................................................ 185 Figure 6-7 Single-Point Vertex Example......................................................................................... 186 Figure 6-8 Octants for Line Drawing............................................................................................... 190 Figure 6-9 DMA Time Slot Allocation............................................................................................ 195 Figure 6-10 Normal 68000 Cycle...................................................................................................... 196 Figure 6-11 Time Slots Used by a Six Bitplane Display.................................................................... 197 Figure 6-12 Time Slots Used by a High Resolution Display.............................................................. 197 Figure 6-13 Blitter Block Diagram.................................................................................................... 199 Figure 7-1 Inter-Sprite Fixed Priorities........................................................................................... 208 Figure 7-2 Analogy for Video Priority............................................................................................ 209 Figure 7-3 Sprite/Playfield Priority................................................................................................. 212 Figure 7-4 Interrupt Priorities.......................................................................................................... 221 Figure 8-1 Controller Plug and Computer Connector...................................................................... 228 Figure 8-2 Mouse Quadrature.......................................................................................................... 230 Figure 8-3 Joystick to Counter Connections..................................................................................... 233 Figure 8-4 Typical Paddle Wiring Diagram..................................................................................... 234 Figure 8-5 Effects of Resistance on Charging Rate.......................................................................... 235 Figure 8-6 Potentiometer Charging Circuit...................................................................................... 237 Figure 8-7 Chinon Timing Diagram................................................................................................ 242 Figure 8-8 Chinon Timing Diagram (cortt.)...................................................................................... 243 Figure 8-9 The Amiga 1000 Keyboard, Showing Keycodes in Hexadecimal.................................... 254 Figure 8-10 The Amiga 500/2000/3000 Keyboard, Showing Keycodes in Hexadecimal.................... 254 Figure 8-11 Starting Appearance of SERDAT and Shift Register...................................................... 258 Figure 8-12 Ending Appearance of Shift Register.............................................................................. 259 Figure E-l Reading Fire Buttons..................................................................................................... 330 Figure E-2 Pot Counters.................................................................................................................. 332 Figure E-3 Light Pen....................................................................................................................... 333 Figure K-l A2000 vs A3000 Bus Termination................................................................................. 386 Figure K-3 Expansion Bus Clocks................................................................................................... 393 Figure K-4 Zorro II Bus Arbitration................................................................................................. 394 Figure K-5 Basic Zorro III Cycles.................................................................................................... 400 Figure K-6 Multiple Transfer Cycles............................................................................................... 403 Figure K-7 Zorro III Bus Arbitration................................................................................................ 405 Figure K-8 Interrupt Vector Cycle.................................................................................................... 407 Figure K-9 Zorro II Within Zorro III................................................................................................ 408 Figure K-10 Read Cycle Timing........................................................................................................ 417 Figure K-l 1 Write Cycle Timing....................................................................................................... 419 Figure K-12 Multiple Transfer Cycle Timing..................................................................................... 421 Figure K-l3 Quick Interrupt Cycle Timing......................................................................................... 423 Figure K-14 Configuration Register Mapping..................................................................................... 432 viii L ist of Tables Table 1-1 Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 6-1 Table 6-2 Table 6-3 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Summary of Amiga Memory Configurations................................................................. 5 Interrupting the 680x0.................................................................................................... 35 Copper Instruction Summary......................................................................................... 36 Colors in a Single Playfield............................................................................................ 45 Portion of the Color Table............................................................................................. 46 Contents of the Color Registers...................................................................................... 46 Sample Color Register Contents..................................................................................... 47 Setting the Number of Bitplanes..................................................................................... 48 Lines in a Normal Playfield........................................................................................... 49 Playfield Memory Requirements, NTSC........................................................................ 52 Playfield Memory Requirements, PAL........................................................................... 53 DIWSTRT and DIWSTOP Summary............................................................................. 59 Playfield 1 Color Registers — Low resolution Mode...................................................... 70 Playfield 2 Color Registers — Low resolution Mode...................................................... 70 Playfields 1 and 2 Color Registers — High resolution Mode.......................................... 71 Maximum Allowable Vertical Screen Video.................................................................. 79 Maximum Allowable Horizontal Screen Video............................................................... 80 Color Register Contents................................................................................................. 92 Some Register Values and Resulting Colors................................................................... 92 Low resolution Color Selection...................................................................................... 93 High resolution Color Selection...................................................................................... 94 Color Selection in Hold-and-modify Mode.................................................................... 95 Sprite Data Structure...................................................................................................... 105 Sprite Color Registers.................................................................................................... 108 Color Registers for Sprite Pairs...................................................................................... 115 Data Words for First Line of Spaceship Sprite................................................................ 121 Color Registers in Attached Sprites................................................................................ 122 Color Registers for Single Sprites................................................................................... 130 Color Registers for Attached Sprites.............................................................................. 131 Sample Audio Data Set for Channel 0 ............................................................................ 138 Volume Values............................................................................................................... 140 DMA and Audio Channel Enable Bits............................................................................ 144 Data Interpretation in Attach Mode................................................................................ 150 Channel Attachment for Modulation.............................................................................. 151 Sampling Rate and Frequency Relationship.................................................................... 157 Equal-tempered Octave for a 16 Byte Sample................................................................. 158 Five Octave Even-tempered Scale.................................................................................. 160 Decibel Values and Volume Ranges............................................................................... 163 Table of Common Minterm Values................................................................................ 177 Typical Blitter Cycle Sequence....................................................................................... 188 BLTCON1 Code Bits for Octant Line Drawing.............................................................. 190 Bits in BPLCON2.......................................................................................................... 210 Priority of Playfields Based on Values of Bits PF1P2-PF1P0.......................................... 210 CLXDAT Bits................................................................................................................ 214 CLXCONBits................................................................................................................ 215 IX Table 7-5 Table 7-6 Table 8-1 Table 8-2 Table 8-3 Table 8 4 Table 8-5 Table 8-6 Table 8-7 Table 8-8 Table 8-9 Table K-l Contents of the Beam Position Counter.......................................................................... 216 Contents of DMA Control Register................................................................................ 222 Typical Controller Connections..................................................................................... 228 Determining the Direction of the Mouse........................................................................ 231 Interpreting Data from JOYODAT and JOY1DAT.......................................................... 232 POTGO ($DFF034) and POTDMP (SDFF016) Registers................................................. 240 Disk Subsystem............................................................................................................. 244 DSKLEN Register (SDFF024)....................................................................................... 246 DSKBYTR Register....................................................................................................... 248 ADKCON and ADKCONR Register.............................................................................. 249 SERDATR / ADKCON Registers.................................................................................. 256 Memory Space Type Codes........................................................................................... 414 x Preface The Amiga Technical Reference Series is the official guide to programming Commodore’s Amiga computers. This revised edition of the Amiga Hardware Reference Manual provides detailed information abou