Datasheet · 2022

TI BQ769x0 (BQ76920/30/40) 3S–15S Battery Monitor Family — Datasheet (SLUSBK2I)

Monitor alternative considered.

Author: Texas Instruments
Year: 2022
Type: Datasheet
Credit: Texas Instruments (ti.com)

battery monitor
afe
bms

BQ76920, BQ76930, BQ76940 SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 BQ769x0 3-Series to 15-Series Cell Battery Monitor Family for Li-Ion and Phosphate Applications 1 Features 3 Description • The BQ769x0 family of robust analog front-end (AFE) devices serves as part of a complete pack monitoring and protection solution for next-generation, high-power systems, such as light electric vehicles, power tools, and uninterruptible power supplies. The BQ769x0 is designed with low power in mind: Subblocks within the IC may be enabled or disabled to control the overall chip current consumption, and a SHIP mode provides a simple way to put the pack into an ultra-low power state. • • AFE monitoring features – Pure digital interface – Internal ADC measures cell voltage, die temperature, and external thermistor – A separate, internal ADC measures pack current (coulomb counter) – Directly supports up to three thermistors (103AT) Hardware protection features – Overcurrent in Discharge (OCD) – Short Circuit in Discharge (SCD) – Overvoltage (OV) – Undervoltage (UV) – Secondary protector fault detection Additional features – Integrated cell balancing FETs – Charge, discharge low-side NCH FET drivers – Alert interrupt to host microcontroller – 2.5-V or 3.3-V output voltage regulator – No EEPROM programming necessary – High supply voltage absolute maximum (up to 108 V) – Simple I2C compatible interface (CRC option) – Random cell connection tolerant The BQ76920 device supports up to 5-series cells or typical 18-V packs, the BQ76930 handles up to 10-series cells or typical 36-V packs, and the BQ76940 works for up to 15-series cells or typical 48-V packs. A variety of battery chemistries may be managed with these AFEs, including Li-ion, Li-iron phosphate, and more. Through I2C, a host controller can use the BQ769x0 to implement many battery pack management functions, such as monitoring (cell voltages, pack current, pack temperatures), protection (controlling charge/discharge FETs), and balancing. Integrated A/D converters enable a purely digital readout of critical system parameters, with calibration handled in TI’s manufacturing process. 2 Applications • • • • Device Information PART NUMBER1 Light electric vehicles (LEV): eBikes, eScooters, pedelec, and pedal-assist bicycles Power tools and garden tools Battery backup units (BBUS), energy storage systems (ESS), and uninterruptible power supply (UPS) systems Other industrial battery packs (≥10S) PACKAGE BODY SIZE (NOM) BQ76920 TSSOP (20) 6.50 mm × 4.40 mm BQ76930 TSSOP (30) 7.80 mm × 4.40 mm BQ76940 TSSOP (44) 11.00 mm × 4.40 mm PACK + PACK – Rf BAT Rc Cc Rc Cc Rc VC 5 REGSRC VC 4 REGOUT VC 3 CAP 1 VC 2 TS 1 VC 1 SCL VC 0 10 kΩ 1 µF 1 µF Cf 4.7 µF 10 k SDA Cc Rc SRP VSS SRN CHG ALERT DSG PUSH - BUTTON FOR BOOT Cc VCC Rc Cc SCL SDA Cc Companion Controller GPIO 1M Rc VSS 0 .1 µF 0 .1 µF 100 0 .1 µF 100 1M 1M Rsns Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................3 6.1 Versions...................................................................... 3 6.2 BQ76920 Pin Diagram................................................ 4 6.3 BQ76930 Pin Diagram................................................ 5 6.4 BQ76940 Pin Diagram................................................ 6 7 Specifications.................................................................. 8 7.1 Absolute Maximum Ratings........................................ 8 7.2 ESD Ratings............................................................... 8 7.3 Recommended Operating Conditions.........................9 7.4 Thermal Information..................................................10 7.5 Electrical Characteristics...........................................10 7.6 Timing Requirements................................................ 14 7.7 Typical Characteristics.............................................. 15 8 Detailed Description......................................................16 8.1 Overview................................................................... 16 8.2 Functional Block Diagram......................................... 16 8.3 Feature Description...................................................17 8.4 Device Functional Modes..........................................27 8.5 Register Maps...........................................................29 9 Application and Implementation.................................. 38 9.1 Application Information............................................. 38 9.2 Typical Applications ................................................. 41 10 Power Supply Recommendations..............................46 11 Layout........................................................................... 47 11.1 Layout Guidelines................................................... 47 11.2 Layout Example...................................................... 47 12 Device and Documentation Support..........................49 12.1 Third-Party Products Disclaimer............................. 49 12.2 Documentation Support.......................................... 49 12.3 Related Links.......................................................... 49 12.4 Receiving Notification of Documentation Updates..49 12.5 Trademarks............................................................. 49 13 Mechanical, Packaging, and Orderable Information.................................................................... 49 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (March 2019) to Revision I (March 2022) Page • Changed the formatting throughout ................................................................................................................... 1 • Added VCn rows in Absolute Maximum Ratings table....................................................................................... 8 • Changed tablenote for POR and referenced entries........................................................................................ 10 • Changed the scale in the VCx and OV Protection plots .................................................................................. 15 • Updated 16-Bit Pack Voltage ...........................................................................................................................21 • Changed "OV Trip" to "UV Trip" in the description of undervoltage protection................................................. 21 • Changed the LSB bit count from 2 to 4 for the OV_TRIP register.................................................................... 30 • Updated Application Information ......................................................................................................................38 • Added Device Timing .......................................................................................................................................38 • Added Random Cell Connection ..................................................................................................................... 38 • Added Power Pin Diodes .................................................................................................................................38 • Added Alert Pin ................................................................................................................................................38 • Added Sense Inputs ........................................................................................................................................ 38 • Added TSn Pins ...............................................................................................................................................38 • Updated Unused Pins ......................................................................................................................................39 • Updated Step-by-Step Design Procedure ....................................................................................................... 45 Changes from Revision G (April 2016) to Revision H (March 2019) Page • Changed Applications ........................................................................................................................................1 • Changed the Description ................................................................................................................................... 1 • Added High-Side FET Driving ..........................................................................................................................23 • Added the link to the BQ769x0 Boot Switch Alternatives Application Report ..................................................27 • Added the link to the BQ769x0 Family Top Design Considerations Application Report .................................. 38 • Added Figure 9-4 to provide an example of a high-side FET configuration......................................................41 • Added BQ769x0 Family Top Design Considerations Application Report link................................................... 46 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 5 Device Comparison Table TUBE (1) TAPE & REEL CELLS BQ7692000PW BQ7692000PWR BQ7692001PW(1) BQ7692001PWR(1) BQ7692002PW(1) BQ7692002PWR(1) BQ7692003PW BQ7692003PWR BQ7692006PW BQ7692006PWR BQ7693000DBT BQ7693000DBTR BQ7693001DBT BQ7693001DBTR BQ7693002DBT BQ7693002DBTR BQ7693003DBT BQ7693003DBTR BQ7693006DBT BQ7693006DBTR BQ7693007DBT BQ7693007DBTR BQ7694000DBT BQ7694000DBTR BQ7694001DBT BQ7694001DBTR BQ7694002DBT BQ7694002DBTR BQ7694003DBT BQ7694003DBTR BQ7694006DBT BQ7694006DBTR I2C ADDRESS (7Bit) LDO (V) CRC No 2.5 3–5 Yes 0x08 No 3.3 20-TSSOP (PW) Yes 0x18 No No 2.5 Yes 0x08 No 6–10 Yes 3.3 30-TSSOP (DBT) No 0x18 Yes No 2.5 9–15 PACKAGE Yes 0x08 No 3.3 44-TSSOP (DBT) Yes 0x18 No Product Preview only Texas Instruments preconfigures the BQ769x0 devices for a specific I2C address, LDO voltage, and more. These settings are permanently stored in EEPROM and cannot be further modified. Contact Texas Instruments for other options not listed above, as well as any options noted as “Product Preview only.” 6 Pin Configuration and Functions 6.1 Versions DSG 1 20 ALERT DSG 1 30 ALERT DSG 1 44 ALERT CHG 2 19 SRN CHG 2 29 SRN CHG 2 43 SRN VSS 3 18 SRP VSS 3 28 SRP VSS 3 42 SRP SDA 4 17 VC0 SDA 4 27 VC0 SDA 4 41 VC0 16 VC1 SCL 5 26 VC1 SCL 5 40 VC1 15 VC2 TS1 6 25 VC2 TS1 6 39 VC2 24 VC3 CAP1 7 38 VC3 23 VC4 REGOUT 8 37 VC4 SCL 5 TS1 6 CAP 1 7 14 VC3 CAP1 7 REGOUT 8 13 VC4 REGOUT 8 REGSRC 9 12 VC5 REGSRC 9 22 VC5 REGSRC 9 36 VC5 BAT 10 11 NC VC5x 10 21 VC5B VC5x 10 35 VC5B NC 11 20 VC6 NC 11 34 VC6 NC 12 33 VC7 20-TSSOP 30-TSSOP 44-TSSOP NC 12 19 VC7 TS2 13 18 VC8 TS2 13 32 VC8 CAP2 14 17 VC9 CAP2 14 31 VC9 BAT 15 16 VC10 VC10x 15 30 VC10 NC 16 29 VC10B NC 17 28 VC11 TS3 18 27 VC12 CAP3 19 26 VC13 BAT 20 25 VC14 NC 21 24 VC15 NC 22 23 NC BQ76920: 3–5 Series Cells (20-TSSOP) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 3 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 • 6.5 mm x 4.4 mm x 1.2 mm BQ76930: 6–10 Series Cells (30-TSSOP) • 7.8 mm x 4.4 mm x 1.2 mm BQ76940: 9–15 Series Cells (44-TSSOP) • 11.3 mm x 4.4 mm x 1.2 mm 6.2 BQ76920 Pin Diagram DSG 1 20 ALERT CHG 2 19 SRN VSS 3 18 SRP SDA 4 17 VC0 SCL 5 16 VC1 TS1 6 15 VC2 CAP 1 7 14 VC3 REGOUT 8 13 VC4 REGSRC 9 12 VC5 11 NC BAT 20-TSSOP 10 Table 6-1. BQ76920 Pin Functions PIN NAME TYPE 1 DSG O Discharge FET driver DESCRIPTION 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 BAT P Battery (top-most) terminal 11 NC — No connect 12 VC5 I Sense voltage for 5th cell positive terminal 13 VC4 I Sense voltage for 4th cell positive terminal 14 VC3 I Sense voltage for 3rd cell positive terminal 15 VC2 I Sense voltage for 2nd cell positive terminal 16 VC1 I Sense voltage for 1st cell positive terminal 17 VC0 I Sense voltage for 1st cell negative terminal 18 SRP I Negative current sense (nearest VSS) 19 SRN I Positive current sense 20 ALERT I/O Alert output and override input (1) If not used, pull down to VSS with a 10-kΩ nominal resistor. 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 6.3 BQ76930 Pin Diagram DSG 1 30 ALERT CHG 2 29 SRN VSS 3 28 SRP SDA 4 27 VC0 SCL 5 26 VC1 TS1 6 25 VC2 CAP1 7 24 VC3 30-TSSOP REGOUT 8 23 VC4 REGSRC 9 22 VC5 VC5x 10 21 VC5B NC 11 20 VC6 NC 12 19 VC7 TS2 13 18 VC8 CAP2 14 17 VC9 BAT 15 16 VC10 Table 6-2. BQ76930 Pin Functions PIN NAME TYPE 1 DSG O Discharge FET driver DESCRIPTION 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 VC5X P Thermistor #2 negative terminal 11 NC — No connect (short to CAP2) 12 NC — No connect (short to CAP2) 13 TS2 I Thermistor #2 positive terminal(1) 14 CAP2 O Capacitor to VC5X 15 BAT P Battery (top-most) terminal 16 VC10 I Sense voltage for 10th cell positive terminal 17 VC9 I Sense voltage for 9th cell positive terminal 18 VC8 I Sense voltage for 8th cell positive terminal 19 VC7 I Sense voltage for 7th cell positive terminal 20 VC6 I Sense voltage for 6th cell positive terminal 21 VC5B I Sense voltage for 6th cell negative terminal 22 VC5 I Sense voltage for 5th cell positive terminal 23 VC4 I Sense voltage for 4th cell positive terminal 24 VC3 I Sense voltage for 3rd cell positive terminal 25 VC2 I Sense voltage for 2nd cell positive terminal 26 VC1 I Sense voltage for 1st cell positive terminal 27 VC0 I Sense voltage for 1st cell negative terminal Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 5 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 Table 6-2. BQ76930 Pin Functions (continued) (1) PIN NAME TYPE 28 SRP I Negative current sense (nearest VSS) DESCRIPTION 29 SRN I Positive current sense 30 ALERT I/O Alert output and override input If not used, pull down to group ground reference (VSS for TS1 and VC5X for TS2) with a 10-kΩ nominal resistor. 6.4 BQ76940 Pin Diagram DSG 1 44 ALERT CHG 2 43 SRN VSS 3 42 SRP SDA 4 41 VC0 SCL 5 40 VC1 TS1 6 39 VC2 CAP1 7 38 VC3 REGOUT 8 37 VC4 REGSRC 9 36 VC5 VC5x 10 35 VC5B NC 11 34 VC6 NC 12 33 VC7 TS2 13 32 VC8 CAP2 14 31 VC9 VC10x 15 30 VC10 NC 16 29 VC10B NC 17 28 VC11 44-TSSOP TS3 18 27 VC12 CAP3 19 26 VC13 BAT 20 25 VC14 NC 21 24 VC15 NC 22 23 NC BQ76940 Pin Functions 6 PIN NAME TYPE 1 DSG O Discharge FET driver DESCRIPTION 2 CHG O Charge FET driver 3 VSS — Chip VSS 4 SDA I/O I2C communication to the host controller 5 SCL I I2C communication to the host controller 6 TS1 I Thermistor #1 positive terminal(1) 7 CAP1 O Capacitor to VSS 8 REGOUT P Output LDO 9 REGSRC I Input source for output LDO 10 VC5X P Thermistor #2 negative terminal 11 NC — No connect (short to CAP2) 12 NC — No connect (short to CAP2) 13 TS2 I Thermistor #2 positive terminal(1) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 BQ76940 Pin Functions (continued) (1) PIN NAME TYPE 14 CAP2 O Capacitor to VC5X DESCRIPTION 15 VC10X P Thermistor #3 negative terminal 16 NC — No connect (short to CAP3) 17 NC — No connect (short to CAP3) 18 TS3 I Thermistor #3 positive terminal(1) 19 CAP3 O Capacitor to VC10X 20 BAT P Battery (top-most) terminal 21 NC — No connect 22 NC — No connect 23 NC — No connect 24 VC15 I Sense voltage for 15th cell positive terminal 25 VC14 I Sense voltage for 14th cell positive terminal 26 VC13 I Sense voltage for 13th cell positive terminal 27 VC12 I Sense voltage for 12th cell positive terminal 28 VC11 I Sense voltage for 11th cell positive terminal 29 VC10B I Sense voltage for 11th cell negative terminal 30 VC10 I Sense voltage for 10th cell positive terminal 31 VC9 I Sense voltage for 9th cell positive terminal 32 VC8 I Sense voltage for 8th cell positive terminal 33 VC7 I Sense voltage for 7th cell positive terminal 34 VC6 I Sense voltage for 6th cell positive terminal 35 VC5B I Sense voltage for 6th cell negative terminal 36 VC5 I Sense voltage for 5th cell positive terminal 37 VC4 I Sense voltage for 4th cell positive terminal 38 VC3 I Sense voltage for 3rd cell positive terminal 39 VC2 I Sense voltage for 2nd cell positive terminal 40 VC1 I Sense voltage for 1st cell positive terminal 41 VC0 I Sense voltage for 1st cell negative terminal 42 SRP I Negative current sense (nearest VSS) 43 SRN I Positive current sense 44 ALERT I/O Alert output and override input If not used, pull down to group ground reference (VSS for TS1, VC5X for TS2, and VC10X for TS3) with a 10-kΩ nominal resistor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 7 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7 Specifications 7.1 Absolute Maximum Ratings Over-operating free-air temperature range (unless otherwise noted) (1) VBAT Supply voltage VI Input voltage (BAT–VSS) BQ76920 (BAT–VC5x), (VC5x–VSS) BQ76930 (BAT–VC10x), (VC10x–VC5x), (VC5x–VSS) BQ76940 (VCn–VSS) where n = 1..5 BQ76920, BQ76930, BQ76940 (VCn-VC5x) where n = 6..10 BQ76930, BQ76940 (VCn–VC10x) where n = 11..15 BQ76940 Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5 (BQ76940/BQ76930/BQ76920, respectively) Output voltage (VC0–VSS), (CAP1–VSS), (TS1–VSS)(2) BQ76920 (VC0–VSS), (VC5b–VC5x), (CAP2–VC5x), (CAP1– VSS), (TS2–VC5x), (TS1–VSS)(2) BQ76930 (VC0–VSS), (VC5b–VC5x), (VC10b–VC10x), (CAP3– VC10x), (CAP2–VC5x), (CAP1–VSS), (TS3–VC10x), (TS2–VC5x), (TS1–VSS)(2) BQ76940 UNIT –0.3 36 V (n × 7.2) –0.3 (n–5) × 7.2 V (n–10) × 7.2 –0.3 9 –0.3 3.6 REGSRC –0.3 36 REGOUT, ALERT –0.3 3.6 DSG –0.3 20 CHG –0.3 VCHGCLAMP ICB Cell balancing current (per cell) IDSG Discharge pin input current when disabled (measured into terminal) V V V BQ76920 70 mA BQ76930, BQ76940 5 mA Storage temperature TSTG (2) MAX SRN, SRP, SCL, SDA VO (1) MIN 7 mA –65 150 Lead temperature (soldering, 10 s) 300 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The Absolute Maximum Ratings for (TS1–VSS) apply after the device completes POR and should be observed after tBOOTREADY (10 ms), following the application of the boot signal on TS1. Prior to completion of POR, TS1 should not exceed 5 V. 7.2 ESD Ratings V(ESD) Electrostatic discharge VALUE UNIT Human body model (HBM) ESD stress voltage(1) ±2 kV Charged device model (CDM) ESD stress voltage(2) ±500 V (1) (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.3 Recommended Operating Conditions Over-operating free-air temperature range (unless otherwise noted). See Section 9.1.8 for more information on cell configurations. All voltages are relative to VSS, except "Cell input differential." MIN VBAT Supply voltage MAX UNIT 6 25 V 2 5 V 0 5×n V –10 10 mV –200 200 mV 0 3.6 REGSRC 6 25 CHG, DSG 0 16 V 0 3.6 V (BAT–VSS) BQ76920 (BAT–VC5x), (VC5x–VSS) BQ76930 (BAT–VC10x), (VC10x–VC5x), (VC5x–VSS) BQ76940 Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5 (BQ76940/BQ76930/BQ76920, respectively), in-use cells only (VCn–VSS) where n = 1..5 BQ76920 (VCn–VSS) where n = 1..5, (VCn– VC5x) where n = 6..10 BQ76930 (VCn–VSS) where n = 1..5, (VCn– VC5x) where n = 6..10, (VCn– VC10x) where n = 11..15 BQ76940 TYP SRP VIN Input voltage (VC0–VSS) BQ76920 (VC0–VSS), (VC5b–VC5x) BQ76930 (VC0–VSS), (VC5b–VC5x), (VC10b–VC10x) BQ76940 SRN SCL, SDA (TS1–VSS) BQ76920 (TS1–VSS), (TS2–VC5x) BQ76930 (TS1–VSS), (TS2–VC5x), (TS3– VC10x) BQ76940 V REGOUT, ALERT VOUT Output voltage (CAP1–VSS) BQ76920 (CAP1–VSS), (CAP2–VC5x) BQ76930 (CAP1–VSS), (CAP2–VC5x), (CAP3–VC10x) BQ76940 Cell balancing current (internal, per cell) BQ76920 0 50 mA ICB BQ76930, BQ76940 0 5 mA RC External cell input resistance BQ76920 40 100 1K Ω BQ76930, BQ76940 500 1K 1K Ω CC External cell input capacitance 0.1 1 10 µF Rf External supply filter resistance 40 100 1K Ω Cf External supply filter capacitance 1 10 40 µF RFILT Sense resistor filter resistance 100 1K RALERT ALERT pin to VSS resistor 1M Ω CL REGOUT loading capacitance 1 4.7 µF CCAP REGSRC, CAP1, CAP2, and CAP3 output capacitance 1 µF RTS External thermistor nominal resistance (103AT) at 25°C 10K Ω TOPR Operating free-air temperature –40 Ω 85 °C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 9 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.4 Thermal Information Over-operating free-air temperature range (unless otherwise noted) TSSOP THERMAL METRIC(1) BQ76920xy 20 PINS (PW) BQ76930xy 30 PINS (DBT) BQ76940xy 44 PINS (DBT) UNIT RθJA, High K Junction-to-ambient thermal resistance 93.7 86.5 70.1 °C/W RθJC(top) Junction-to-case(top) thermal resistance 28.7 19.4 17.5 °C/W RθJB Junction-to-board thermal resistance 44.6 41.3 33.9 °C/W ψJT Junction-to-top characterization parameter 1.3 0.5 0.5 °C/W ψJB Junction-to-board characterization parameter 44.1 40.6 33.4 °C/W RθJC(bottom) Junction-to-case(bottom) thermal resistance n/a n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application Report (SPRA953). 7.5 Electrical Characteristics Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX 40 60 60 90 110 165 NORMAL mode: ADC on, CC on 130 195 NORMAL mode: ADC off 30 45 50 75 10 15 80 120 0.6 1.8 –5 ±2.5 5 –1.0 ±0.1 1.0 15 25 ±0.1 0.3 UNIT SUPPLY CURRENTS NORMAL mode: ADC off, CC off NORMAL mode: ADC on, CC off IDD Sum of ICC_BAT and ICC_REGSRC currents NORMAL mode: ADC off, CC on ICC_BAT ICC_REGSRC ISHIP Into BAT pin NORMAL mode: ADC on NORMAL mode: CC off Into REGSRC pin NORMAL mode: CC on Device in full shutdown, only VSTUP/BG and BOOT detector on SHIP/SHUTDOWN mode µA LEAKAGE AND OFFSET CURRENTS dINOM NORMAL mode supply current offset dISHIP SHIP mode supply current offset dIALERT Supply current when ALERT active dICELL Cell measurement input current ILKG Measured into VC5x (BQ76930, BQ76940) and VC10x (BQ76940) Measured into VC5x (BQ76930, BQ76940) or added to BAT (BQ76920) Measured into VC0–VC15 except VC5, VC10, VC15 –0.3 Measured into VC5, VC10, VC15 µA 0.5 Terminal input leakage 1 INTERNAL POWER CONTROL (STARTUP and SHUTDOWN) VPORA Analog POR threshold VBAT rising. See (4). VSHUT Shutdown voltage VBAT falling. See (4). tI2CSTARTUP Time delay after boot signal on TS1 before I2C communications allowed Delay after boot sequence when I2C communication is allowed 10 Submit Document Feedback 4 1 5 V 3.6 V ms Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP Delay after boot signal when device has completed full boot-up sequence tBOOTREADY Device boot startup delay TSHUTD Thermal shutdown voltage 100 MAX UNIT 10 ms 150 °C MEASUREMENT SCHEDULE tVCELL Cell voltage measurement interval tINDCELL Individual cell measurement time tCB_RELAX Cell balancing relaxation time before cell voltage measured 12.5 tTEMP_DEC Temperature measurement Measurement duration for temperature decimation time reading 12.5 tBAT Pack voltage calculation interval 250 tTEMP Temperature measurement Period of measurement of either interval TS1/TS2/TS3 or internal die temp BQ76920, BQ76930, BQ76940 250 Per cell, balancing off 50 Per cell, balancing on 12.5 ms 2 s 14-BIT ADC FOR CELL VOLTAGE AND TEMPERATURE MEASUREMENT ADCRANGE ADC measurement recommend operation range ADCLSB ADC LSB value VCELL measurements TS/Temp measurements 5 V 0.3 3 V 382 ADC cell voltage accuracy at 25°C ADC 2 ADC cell voltage accuracy 0°C to 60°C ADC cell voltage accuracy –40°C to 85°C VCELL = 3.6 V – 4.3 V ±10 VCELL = 3.2 V – 4.6 V ±15 VCELL = 2.0 V – 5.0 V ±25 VCELL = 3.6 V – 4.3 V ±20 VCELL = 3.2 V – 4.6 V ±25 VCELL = 2.0 V – 5.0 V ±35 µV mV VCELL = 3.6 V – 4.3 V –40 40 VCELL = 3.2 V – 4.6 V –40 40 VCELL = 2.0 V – 5.0 V –50 50 16-BIT CC FOR PACK CURRENT MEASUREMENT CCRANGE CC input voltage range –200 200 mV CCFSR CC full scale range –270 270 mV CCLSB CC LSB value CC running constantly 8.44 µV tCCREAD Conversion time Single conversion 250 ms CCINL Integral nonlinearity 16-bit, best fit over input voltage range ± 200 mV ±2 ± 40 LSB CCOFFSET Offset error ±1 ±3 LSB CCGAIN Gain error Over input voltage range ± 0.5% ± 1.5% FSR CCGAINDRIFT Gain error drift Over input voltage range CCRIN Effective input resistance 150 PPM / °C 2.5 MΩ THERMISTOR BIAS RTS Pull-up resistance TA = 25°C 9.85 RTSDRIFT Pull-up resistance across temp TA = –40°C to 85°C 9.7 10 10.15 kΩ 10.3 kΩ Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 11 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX UNIT DIETEMP VDIETEMP25 Die temperature voltage VDIETEMPDRIFT Die temperature voltage drift TA = 25°C 1.20 V –4.2 mV/°C INTEGRATED HARDWARE PROTECTIONS OVRANGE OV threshold range 0x2008 0x2FF8 ADC UVRANGE UV threshold range 0x1000 0x1FF0 ADC OVUVSTEP OV and UV threshold step size UVMINQUAL UV minimum value to qualify OVDELAY UVDELAY OCDRANGE OV delay timer options UV delay timer options OCD threshold options Below UVMINQUAL, the cell is shorted (unused) ADC 0.7 1 1.75 1.6 2 2.75 OV delay = 4 s 3.5 4 5 OV delay = 8 s 7 8 10 UV delay = 1 s 0.7 1 1.75 UV delay = 4 s 3.5 4 5 UV delay = 8 s 7 8 10 UV delay = 16 s 14 16 20 Measured across (SRP–SRN)(2) 8 RSNS = 0 100 2.78 OCDDELAY OCD delay options See Note(3) 8 SCD threshold options Measured across (SRP–SRN)(2) 22 SCD threshold step size 0x0518 OV delay = 2 s OCD threshold step size SCDSTEP LSB OV delay = 1 s OCDSTEP SCDRANGE 16 RSNS = 1 mV 1280 ms 200 mV 11.1 RSNS = 1 mV mV 5.56 RSNS = 0 s mV 22.2 mV 35 70 105 µs 50 100 150 µs 140 200 260 µs 280 400 520 µs SCDDELAY SCD delay options tPROTACC Delay accuracy for OCD –20% 20% OCOFFSET OCD and SCD voltage offset –2.5 2.5 OCSCALEERR OCD and SCD scale accuracy –10% 10% mV CHARGE AND DISCHARGE DRIVERS VFETON CHG and DSG on REGSRC ≥ 12 V with load resistance of 10 MΩ 10 12 14 V REGSRC < 12 V with load resistance of 10 MΩ REGSRC – 2 REGSRC – 1 REGSRC V tFET_ON CHG and DSG ON rise time CHG/DSG driving an equivalent load capacitance of 10 nF, measured from 10% to 90% of VFETON 200 250 µs tDSG_OFF DSG pull-down OFF fall time DSG driving an equivalent load capacitance of 10 nF, measured from 90% to 10% 60 90 µs 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.5 Electrical Characteristics (continued) Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940) with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to +85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections. PARAMETER TEST CONDITION MIN TYP MAX UNIT RCHG_OFF CHG pull-down OFF resistance to VSS When CHG disabled, CHG held at 12 V 750 1000 1250 kΩ RDSG_OFF DSG pull-down OFF resistance to VSS When DSG disabled, DSG held at 12 V 1.75 2.50 4.25 kΩ VLOAD_DETECT Load detection threshold 0.4 0.7 1.0 V 18 20 22 V VCHG_CLAMP If the CHG pin externally pulled high (through PACK–, if load applied), 500µA max sink current into CHG pin. With CHG_ON bit cleared. CHG clamp voltage ALERT PIN VALERT_OH ALERT output voltage high IOL = 1 mA VALERT_OL ALERT output voltage low Unloaded VALERT_IH ALERT input high ALERT externally forced high when internally driven low. See note (1). RALERT_PD ALERT pin weak pulldown Measured into ALERT pin with ALERT = resistance when driven low REGOUT REGOUT x 0.75 V 1 REGOUT x 0.25 V 1.5 V 0.8 2.5 8 MΩ 1 5 10 Ω CELL BALANCING DRIVER RDSFET Internal cell balancing driver resistance VCELL = 3.6 V XBAL Cell balancing duty cycle when enabled Every 250 ms 70% EXTERNAL REGULATOR 2.45 2.50 2.55 V 3.20 3.30 3.40 V 100 mV External LDO voltage options Nominal values, TI factory programmed, unloaded, across temp VEXTLDO_LN Line regulation REGSRC pin stepped from 6 to 25 V, with 10-mA load, in 100 µs VEXTLDO_LD Load regulation IREGOUT = 0 mA to 10 mA –4% REGOUT = 10-mA DC, 2.5-V version 2.4 V REGOUT = 20-mA DC, 2.5-V version 2.3 V REGOUT = 10-mA DC, 3.3-V version 3.15 V REGOUT = 20-mA DC, 3.3-V version 3.05 V VEXTLDO VEXTLDO_DC IEXTLDO_LIMIT External LDO minimum voltage under DC load External LDO current limit REGOUT = 0 V 30 4% 38 45 mA BOOT DETECTOR VBOOT Boot threshold voltage Measured at TS1 pin with device in SHIP mode. Below MIN, the device does not boot up. Above MAX, the device boots up. 300 1000 mV tBOOT_max Boot threshold application time Measured at TS1 pin. Below MIN, the device does not boot up. Above MAX, the device boots up. 10 2000 µs (1) (2) (3) (4) MIN specifies the threshold below which the device will never register that an external alert has occurred. MAX specifies the minimum threshold above which the device will always register that an external alert has occurred. Values indicate nominal thresholds only. For min and max variation, apply OCOFFSET and OCSCALERR. Values indicate nominal thresholds only. For min and max variation, apply tPROTACC. Measured at each VBAT Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 13 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.6 Timing Requirements I2C COMPATIBLE INTERFACE MIN TYP MAX REGOUT x 0.25 UNIT VIL Input low logic threshold VIH Input high logic threshold VOL Output low logic drive 0.20 tf SCL, SDA fall time 0.40 VOH Output high logic drive (not applicable due to open-drain outputs) N/A tHIGH SCL pulse width high 4.0 µs tLOW SCL pulse width low 4.7 µs tSU;STA Setup time for START condition 4.7 µs tHD;STA START condition hold time after which first clock pulse is generated 4.0 µs tSU;DAT Data setup time 250 ns tHD;DAT Data hold time 0 µs tSU;STO Setup time for STOP condition 4.0 µs tBUF Time the bus must be free before new transmission can start 4.7 tVD;DAT Clock low to data out valid tHD;DAT Data out hold time after clock low 0 fSCL Clock frequency 0 REGOUT x 0.75 V V N/A V V µs 900 ns 100 kHz ns SCL SDA SCL SDA SCL SDA Figure 7-1. I2C Timing 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 7.7 Typical Characteristics 0.020 0.016 VC2 Error 0.014 VC3 Error 0.012 VC4 Error 0.010 VC5 Error 25 Gain Error (PPM) VCx Error (V) 30 VC1 Error 0.018 0.008 0.006 0.004 0.002 0.000 20 15 10 5 0 ±0.002 ±5 ±0.004 2.00 2.30 2.60 2.90 3.20 3.50 3.80 4.10 4.40 4.70 5.00 VCx Input (V) ±40 35 60 Temperature (ƒC) 85 C005 Figure 7-3. Coulomb Counter Gain Error Temperature Drift (from –0.2 V to 0.2 V) Figure 7-2. BQ76930 VCx Error Across Input Range at 25°C with VIN at 3.6 V 0.0 0.0 ±0.1 ±0.2 ±0.4 ±0.2 Offset (uV) Gain Error (%FSR) 10 ±15 C001 ±0.3 ±0.4 ±0.5 ±0.6 ±0.8 ±1.0 ±1.2 ±0.6 ±1.4 ±0.7 ±1.6 ±40 ±15 10 35 60 85 Temperature (ƒC) ±40 10 ±15 35 60 Temperature (ƒC) C003 Figure 7-4. Coulomb Counter Gain Error (from –0.2 V to 0.2 V) 85 C002 Figure 7-5. Coulomb Counter Offset 0.01 OV Detection Error (V) 0.005 0 -0.005 -0.01 -0.015 -0.02 -40 -15 10 35 Temperature (°C) 60 85 Figure 7-6. OV Protection Detection Error (0xFF Setting) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 15 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8 Detailed Description 8.1 Overview In the BQ769x0 family of analog front-end (AFE) devices, the BQ76920 device supports up to 5-series cells, the BQ76930 device supports up to 10-series cells, and the BQ76940 device supports up to 15-series cells. Through I2C, a host controller can use the BQ769x0 to implement battery pack management functions, such as monitoring (cell voltages, pack current, pack temperatures), protection (controlling charge/discharge FETs), and balancing. Integrated A/D converters enable a purely digital readout of critical system parameters including cell voltages and internal or external temperature, with calibration handled in TI’s manufacturing process. For an additional degree of pack reliability, the BQ769x0 includes hardware protections for voltage (OV, UV) and current (OCD, SCD). The BQ769x0 provides two low-side FET drivers, charge (CHG) and discharge (DSG), which may be used to directly manipulate low-side power NCH FETs, or as signals that control an external circuit that enables high-side PCH or NCH FETs. A dedicated ALERT input/output pin serves as an interrupt signal to the host microcontroller, quickly informing the microcontroller of an updated status in the AFE. This may include a fault event or that a coulomb counter sample is available for reading. An available ALERT pin may also be driven externally by a secondary protector to provide a redundant means of disabling the CHG and DSG signals and higher system visibility. 8.2 Functional Block Diagram REG SRC CAP Bandgap IBIAS VSTUP/POR BAT Cell Balance Drivers/FETs BOOT Internal 3.3-V LDO ALERT 256 kHz Digital core Die temp REG OUT 14-bit ADC Modulator V2I VCx Inputs External 2.5/3.3-V LDO CC VREF FET DRIVER and LOAD DETECT CHG DSG TS SCL 16-bit ACC Modulator I2C SDA TS BOOT SCD comp To POR OCD comp VSS EEPROM SRP SRN Copyright © 2016, Texas Instruments Incorporated 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BQ76920 BQ76930 BQ76940 BQ76920, BQ76930, BQ76940 www.ti.com SLUSBK2I – OCTOBER 2013 – REVISED MARCH 2022 8.3 Feature Description 8.3.1 Subsystems BQ769x0 consists of three major subsystems: Measurement, Protection, and Control. These work together to ensure that the fundamental battery pack parameters—voltage, current and temperature—are accurately captured and easily available to a host controller, while ensuring a baseline or secondary level of hardware protection in the event that a host controller is unable or unavailable to manage certain fault conditions. Note The BQ769x0 is intended to serve as an analog front-end (AFE) as part of a chipset system solution: A companion microcontroller is required to oversee a