Datasheet · 2021
TI BQ76952 3S–16S High Accuracy Battery Monitor and Protector — Datasheet (SLUSE13B)
The high-side protector step-up option.
- battery monitor
- protector
- high-side
Datasheet · 2021
The high-side protector step-up option.
BQ76952 SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 BQ76952 3-Series to 16-Series High Accuracy Battery Monitor and Protector for Li-Ion, Li-Polymer, and LiFePO4 Battery Packs 1 Features 2 Applications • • • • • • FUSE 5V BREG LD PDSG PCHG NC DSG PACK DSG + VC15 REGIN + VC14 REG1 + VC13 REG2 + VC12 RST_SHUT + VC11 DDSG + VC10 DCHG + VC9 DFETOFF + VC8 CFETOFF + VC7 HDQ + VC6 SDA + VC5 SCL + VC4 ALERT COMMUNICATIONS TRANSCEIVER COMM TO SYSTEM COMM VDD 3.3V REG18 TS3 TS2 MCU TS1 • + SRN • CHG NC • PACK+ SRP • BODY SIZE (NOM) 7 mm × 7 mm See the Device Comparison Table for information on the device family. For all available devices, see the orderable addendum at the end of the data sheet. CP1 • (1) PACKAGE PFB (48-pin) VSS • BQ76952xx BAT • Device Information PART NUMBER(1) CHG • • VC0 • The Texas Instruments BQ76952 device is a highly integrated, high-accuracy battery monitor and protector for 3-series to 16-series Li-ion, Lipolymer, and LiFePO4 battery packs. The device includes a high-accuracy monitoring system, a highly configurable protection subsystem, and support for autonomous or host controlled cell balancing. Integration includes high-side charge-pump NFET drivers, dual programmable LDOs for external system use, and a host communication peripheral supporting 400-kHz I2C, SPI, and HDQ one-wire standards. The BQ76952 device is available in a 48-pin TQFP package. VC1 • 3 Description VC16 • VC2 • Battery backup unit (BBU) E-bike, e-scooter, and LEV Cordless power tools and garden tools Non-military drones Other industrial battery pack (≥10S) VC3 • Battery monitoring capability for 3-series to 16series cells Integrated charge pump for high-side NFET protection with optional autonomous recovery Extensive protection suite including voltage, temperature, current, and internal diagnostics Two independent ADCs – Support for simultaneous current and voltage sampling – High-accuracy coulomb counter with input offset error < 1 µV (typical) – High accuracy cell voltage measurement < 10 mV (typical) Wide-range current applications (±200-mV measurement range across sense resistor) Integrated secondary chemical fuse drive protection Autonomous or host-controlled cell balancing Multiple power modes (typical battery pack operating range conditions) – NORMAL mode: 286 µA – Multiple SLEEP mode options: 24 µA to 41 µA – Multiple DEEPSLEEP mode options: 9 µA to 10 µA – SHUTDOWN mode: 1 µA High-voltage tolerance of 85 V on cell connect and select additional pins Tolerant of random cell attach sequence on production line Support for temperature sensing using internal sensor and up to nine external thermistors Integrated one-time-programmable (OTP) memory programmable by customers on production line Communication options include 400-kHz I2C, SPI, and HDQ one-wire interface Dual-programmable LDOs for external system usage 48-pin TQFP package (PFB) GND + + + PACK- Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 3 5 Device Comparison Table...............................................4 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 7 7.1 Absolute Maximum Ratings ....................................... 7 7.2 ESD Ratings .............................................................. 8 7.3 Recommended Operating Conditions ........................9 7.4 Thermal Information BQ76952 .................................10 7.5 Supply Current ......................................................... 10 7.6 Digital I/O ................................................................. 11 7.7 LD Pin ...................................................................... 12 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive ................................................................... 12 7.9 FUSE Pin Functionality ............................................ 12 7.10 REG18 LDO ...........................................................12 7.11 REG0 Pre-regulator ............................................... 13 7.12 REG1 LDO .............................................................13 7.13 REG2 LDO .............................................................14 7.14 Voltage References ................................................14 7.15 Coulomb Counter ...................................................15 7.16 Coulomb Counter Digital Filter (CC1) .................... 15 7.17 Current Measurement Digital Filter (CC2) ............. 16 7.18 Current Wake Detector .......................................... 16 7.19 Analog-to-Digital Converter ....................................16 7.20 Cell Balancing ........................................................ 18 7.21 Cell Open Wire Detector ........................................ 18 7.22 Internal Temperature Sensor ................................. 18 7.23 Thermistor Measurement .......................................18 7.24 Internal Oscillators ................................................. 19 7.25 High-side NFET Drivers ......................................... 20 7.26 Comparator-Based Protection Subsystem .............21 7.27 Timing Requirements - I2C Interface, 100kHz Mode .......................................................................... 23 7.28 Timing Requirements - I2C Interface, 400kHz Mode .......................................................................... 23 7.29 Timing Requirements - HDQ Interface ...................24 7.30 Timing Requirements - SPI Interface ..................... 24 7.31 Interface Timing Diagrams...................................... 25 7.32 Typical Characteristics............................................ 27 8 Device Description........................................................ 32 8.1 Overview................................................................... 32 8.2 Functional Block Diagram......................................... 33 8.3 BQ76952 Device Versions........................................ 33 8.4 Diagnostics............................................................... 33 9 Device Configuration.................................................... 34 9.1 Commands and Subcommands................................34 9.2 Configuration Using OTP or Registers......................34 9.3 Device Security......................................................... 34 9.4 Scratchpad Memory..................................................34 10 Measurement Subsystem........................................... 35 10.1 Voltage Measurement............................................. 35 10.2 General Purpose ADCIN Functionality................... 37 10.3 Coulomb Counter and Digital Filters....................... 37 10.4 Synchronized Voltage and Current Measurement.. 38 10.5 Internal Temperature Measurement........................38 2 10.6 Thermistor Temperature Measurement...................38 10.7 Factory Trim of Voltage ADC.................................. 39 10.8 Voltage Calibration (ADC Measurements).............. 39 10.9 Voltage Calibration (COV and CUV Protections).... 40 10.10 Current Calibration................................................41 10.11 Temperature Calibration........................................41 11 Primary and Secondary Protection Subsystems......42 11.1 Protections Overview.............................................. 42 11.2 Primary Protections.................................................42 11.3 Secondary Protections............................................ 43 11.4 High-Side NFET Drivers..........................................44 11.5 Protection FETs Configuration and Control.............45 11.6 Load Detect Functionality........................................45 12 Device Hardware Features..........................................46 12.1 Voltage References.................................................46 12.2 ADC Multiplexer...................................................... 46 12.3 LDOs.......................................................................46 12.4 Standalone Versus Host Interface.......................... 47 12.5 Multifunction Pin Controls....................................... 47 12.6 RST_SHUT Pin Operation...................................... 48 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality................................................................ 48 12.8 ALERT Pin Operation............................................. 48 12.9 DDSG and DCHG Pin Operation............................ 49 12.10 Fuse Drive.............................................................49 12.11 Cell Open Wire......................................................50 12.12 Low Frequency Oscillator..................................... 50 12.13 High Frequency Oscillator.....................................50 13 Device Functional Modes........................................... 51 13.1 Overview................................................................. 51 13.2 NORMAL Mode.......................................................51 13.3 SLEEP Mode.......................................................... 52 13.4 DEEPSLEEP Mode.................................................52 13.5 SHUTDOWN Mode.................................................53 13.6 CONFIG_UPDATE Mode........................................54 14 Serial Communications Interface...............................54 14.1 Serial Communications Overview........................... 54 14.2 I2C Communications............................................... 54 14.3 SPI Communications.............................................. 56 14.4 HDQ Communications............................................ 62 15 Cell Balancing..............................................................63 15.1 Cell Balancing Overview......................................... 63 16 Application and Implementation................................ 64 16.1 Application Information........................................... 64 16.2 Typical Applications................................................ 64 16.3 Random Cell Connection Support.......................... 70 16.4 Startup Timing.........................................................71 16.5 FET Driver Turn-Off................................................ 72 16.6 Unused Pins............................................................74 17 Power Supply Requirements......................................75 18 Layout...........................................................................75 18.1 Layout Guidelines................................................... 75 18.2 Layout Example...................................................... 76 19 Device and Documentation Support..........................79 19.1 Documentation Support.......................................... 79 19.2 Support Resources................................................. 79 19.3 Trademarks............................................................. 79 19.4 Electrostatic Discharge Caution..............................79 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 19.5 Glossary..................................................................79 20 Mechanical, Packaging, Orderable Information....... 79 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2021) to Revision B (November 2021) Page • Updated the simplified schematic....................................................................................................................... 1 • Updated the Absolute Maximum Ratings, Recommended Operating Conditions, ESD Ratings, and Analog-toDigital Converter tables...................................................................................................................................... 7 • Added Cell 1 Voltage Validation During SLEEP Mode .................................................................................... 36 • Updated the voltage..........................................................................................................................................37 • Updated the nominal value of VREF1 and the ADC counts calculations based on that value......................... 39 • Updated the simplified schematic. Denoted capacitors on sense resistor inputs to VSS as optional.............. 64 • Updated Documentation Support .................................................................................................................... 79 Changes from Revision * (November 2020) to Revision A (February 2021) Page • Updated devices from PRODUCT PREVIEW to Production Data......................................................................4 • Updated the SPI Interface table and SCD threshold detection accuracy in the Comparator-Based Protection Subsystem table in Specifications ..................................................................................................................... 7 • Updated the REG18 voltage plot to show data over temperature and with different BAT levels...................... 27 • Updated approximate ADC saturation level when measuring cell voltages..................................................... 35 • Updated I2C Communications ......................................................................................................................... 54 • Updated SPI Communications .........................................................................................................................56 • Updated SPI Protocol ...................................................................................................................................... 57 • Updated HDQ Communications ...................................................................................................................... 62 • Updated Application and Implementation ........................................................................................................ 64 • Updated Documentation Support .................................................................................................................... 79 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 3 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 5 Device Comparison Table BQ76952 Device Family PART NUMBER Communications Interface CRC Enabled REG1 LDO Default BQ76952 I2C N Disabled BQ7695201 SPI Y Disabled BQ7695202 I2C Y Enabled, set to 3.3 V BQ7695203 SPI Y Enabled, set to 5 V BQ7695204 SPI Y Enabled, set to 3.3 V VC16 BAT CP1 CHG NC DSG PACK LD PCHG PDSG FUSE BREG 48 47 46 45 44 43 42 41 40 39 38 37 6 Pin Configuration and Functions VC12 4 33 RST_SHUT VC11 5 32 DDSG VC10 6 31 DCHG VC9 7 30 DFETOFF VC8 8 29 CFETOFF VC7 9 28 HDQ VC6 10 27 SDA VC5 11 26 SCL VC4 12 25 ALERT Not to scale REG18 TS3 TS2 TS1 SRN NC SRP VSS VC0 VC1 VC2 VC3 24 REG2 23 34 22 3 21 VC13 20 REG1 19 35 18 2 17 VC14 16 REGIN 15 36 14 1 13 VC15 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions PIN 4 I/O TYPE DESCRIPTION VC15 I IA Sense voltage input pin for the fifteenth cell from the bottom of the stack, balance current input for the fifteenth cell from the bottom of the stack, and return balance current for the sixteenth cell from the bottom of stack 2 VC14 I IA Sense voltage input pin for the fourteenth cell from the bottom of the stack, balance current input for the fourteenth cell from the bottom of the stack, and return balance current for the fifteenth cell from the bottom of the stack 3 VC13 I IA Sense voltage input pin for the thirteenth cell from the bottom of the stack, balance current input for the thirteenth cell from the bottom of the stack, and return balance current for the fourteenth cell from the bottom of the stack NO. NAME 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions (continued) PIN I/O TYPE DESCRIPTION VC12 I IA Sense voltage input pin for the twelfth cell from the bottom of the stack, balance current input for the twelfth cell from the bottom of the stack, and return balance current for the thirteenth cell from the bottom of the stack 5 VC11 I IA Sense voltage input pin for the eleventh cell from the bottom of the stack, balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell from the bottom of the stack 6 VC10 I IA Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell from the bottom of the stack 7 VC9 I IA Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack 8 VC8 I IA Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack 9 VC7 I IA Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell from the bottom of the stack 10 VC6 I IA Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack 11 VC5 I IA Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack 12 VC4 I IA Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack 13 VC3 I IA Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack 14 VC2 I IA Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack 15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack 16 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack 17 VSS — P Device ground 18 SRP I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. 19 NC — — This pin is not connected to silicon. 20 SRN I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN. 21 TS1 I/O OD, I/OA Thermistor input, or general purpose ADC input 22 TS2 I/O OD, I/OA Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input 23 TS3 I/O OD, I/OA Thermistor input, or general purpose ADC input 24 REG18 O P Internal 1.8-V LDO output (only for internal use) 25 ALERT I/O I/OD, I/OA 26 SCL I/O I/OD NO. NAME 4 Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output Multifunction pin, can be SCL or SPI_SCLK Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 5 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 Table 6-1. BQ76952 TQFP Package (PFB) Pin Functions (continued) PIN 6 I/O TYPE SDA I/O I/OD 28 HDQ I/O I/OD, I/OA Multifunction pin, can be HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output 29 CFETOFF I/O I/OD, I/OA Multifunction pin, can be CFETOFF, SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output 30 DFETOFF I/O I/OD, I/OA Multifunction pin, can be DFETOFF, BOTHOFF, thermistor input, general purpose ADC input, or general purpose digital output 31 DCHG I/O OD, I/OA Multifunction pin, can be DCHG, thermistor input, general purpose ADC input, or general purpose digital output 32 DDSG I/O OD, I/OA Multifunction pin, can be DDSG, thermistor input, general purpose ADC input, or general purpose digital output 33 RST_SHUT I ID Digital input pin for reset or shutdown 34 REG2 O P Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. 35 REG1 O P First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. 36 REGIN I IA Input pin for REG1 and REG2 LDOs 37 BREG O OA Base control signal for external preregulator transistor 38 FUSE I/O I/OA Fuse sense and drive 39 PDSG O OA Predischarge PFET control 40 PCHG O OA Precharge PFET control 41 LD I/O I/OA Load detect pin 42 PACK I IA Pack sense input pin 43 DSG O OA NMOS Discharge FET drive output pin 44 NC — — This pin is not connected to silicon. 45 CHG O OA NMOS Charge FET drive output pin 46 CP1 I/O I/OA Charge pump capacitor 47 BAT I P Primary power supply input pin 48 VC16 I IA Sense voltage input pin for the sixteenth cell from the bottom of the stack, balance current input for the sixteenth cell from the bottom of the stack, and top-of-stack measurement point NO. NAME 27 DESCRIPTION Multifunction pin, can be SDA or SPI_MISO Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) DESCRIPTION PINS MIN MAX UNIT Supply voltage range BAT VSS–0.3 VSS+85 V Input voltage range, VIN PACK, LD VSS–0.3 VSS+85 V Input voltage range, VIN PCHG, PDSG the maximum of VBAT-10 or VLD-10 VSS+85 V Input voltage range, VIN REGIN the maximum of VSS–0.3 or VBREG-5.5 the minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 V Input voltage range, VIN FUSE(2) the minimum VSS–0.3 of VSS+20 or VBAT+0.3 V Input voltage range, VIN BREG Input voltage range, VIN the maximum of VSS–0.3 or VREGIN-0.3 VREGIN+5.5 V REG1, REG2 VSS–0.3 minimum of VSS+6 or VREGIN+0.3 V Input voltage range, VIN ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, RST_SHUT (3) VSS–0.3 VSS+6 V Input voltage range, VIN TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG (when used as thermistor or general purpose ADC input) VSS–0.3 VREG18 + 0.3 V Input voltage range, VIN SRP, SRN VSS–0.3 VREG18 + 0.3 V VSS+85 V Input voltage range, VIN VC16 maximum of VSS-0.3 and VC15–0.3 Input voltage range, VIN VC15 maximum of VSS-0.3 and VC14–0.3 VSS+85 V Input voltage range, VIN VC14 maximum of VSS-0.3 and VC13–0.3 VSS+85 V Input voltage range, VIN VC13 maximum of VSS-0.3 and VC12–0.3 VSS+85 V Input voltage range, VIN VC12 maximum of VSS-0.3 and VC11–0.3 VSS+85 V Input voltage range, VIN VC11 maximum of VSS-0.3 and VC10–0.3 VSS+85 V Input voltage range, VIN VC10 maximum of VSS-0.3 and VC9–0.3 VSS+85 V Input voltage range, VIN VC9 maximum of VSS-0.3 and VC8–0.3 VSS+85 V Input voltage range, VIN VC8 maximum of VSS-0.3 and VC7–0.3 VSS+85 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 7 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.1 Absolute Maximum Ratings (continued) over operating free-air temperature range (unless otherwise noted)(1) DESCRIPTION PINS MIN MAX Input voltage range, VIN VC7 maximum of VSS-0.3 and VC6–0.3 VSS+85 V Input voltage range, VIN VC6 maximum of VSS-0.3 and VC5–0.3 VSS+85 V Input voltage range, VIN VC5 maximum of VSS-0.3 and VC4–0.3 VSS+85 V Input voltage range, VIN VC4 maximum of VSS-0.3 and VC3–0.3 VSS+85 V Input voltage range, VIN VC3 maximum of VSS-0.3 and VC2–0.3 VSS+85 V Input voltage range, VIN VC2 maximum of VSS-0.3 and VC1–0.3 VSS+85 V Input voltage range, VIN VC1 maximum of VSS-0.3 and VC0–0.3 VSS+85 V Input voltage range, VIN VC0 VSS–0.3 VSS+6 V Output voltage range, VO CP1 the minimum VBAT–0.3 of VSS+85 or VBAT+15 V Output voltage range, VO CHG VSS–0.3 VSS+85 V Output voltage range, VO DSG VSS–0.3 VSS+85 V Output voltage range, VO REG1, REG2, TS2 (for wakeup function), ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG, when configured to drive a digital output VSS–0.3 VSS+6 V Output voltage range, VO REG18 VSS–0.3 VSS+2 V 100 mA Maximum cell balancing current through a single cell VC0 – VC16 Maximum VSS current, ISS UNIT 75 mA Functional temperature, TFUNC –40 85 °C Junction temperature, TJ –55 150 °C Storage temperature, TSTG –55 150 °C (1) (2) (3) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. The current allowed to flow into the FUSE pin must be limited (such as by using external series resistance) to 2 mA or less. When the ALERT, HDQ, CFETOFF, DFETOFF, DCHG, or DDSG pins are selected for thermistor input or general purpose ADC–input, their voltage is limited to VREG18 + 0.3 V. These pins can accept up to 6 V when configured for other uses, such as a digital input. 7.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±1000 V V(ESD) Electrostatic discharge Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins(2) ±250 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com (2) SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN VBAT Supply voltage Voltage on BAT pin (normal operation) VBAT Supply voltage(4) Voltage on BAT pin (OTP programming) TOTP OTP programming temperature(4) VPORA Power-on reset Rising threshold on BAT VPORA_HYS Power-on reset hysteresis Device shuts down when BAT < VPORA - VPORA_HYS VWAKEONLD Wake on LD voltage Rising edge on LD, with BAT already in valid range 0.8 VWAKEONTS2 Wake on TS2 voltage Falling edge on TS2, with BAT already in valid range. TS2 will be weakly driven with a ≈ 5 V level during shutdown. VIN Input voltage range(4) PACK, LD VIN Input voltage range(4) PCHG, PDSG TYP MAX UNIT 4.7 80 V 10 12 V -40 45 °C 3 4 V 180 2.25 V 0.7 1.1 V 0 80 V the maximum of VBAT-9 or VLD-19 80 V Input voltage range(4) REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when the pin is being used for general purpose ADC input or thermistor measurement. 0 5.5 V VIN Input voltage range(4) TS1, TS2, TS3, CFETOFF, DFETOFF, DCHG, DDSG, ALERT, HDQ, when the pin is configured for general purpose ADC input or thermistor measurement. 0 VREG18 V VIN Input voltage range(4) SRP, SRN, SRP-SRN (while measuring current) –0.2 0.2 V VIN Input voltage range(4) SRP, SRN (without measuring current) –0.2 0.75 V VIN Input voltage range(4) (5) VVC(0) VIN 1.45 mV –0.2 0.5 V VVC(x), 1 ≤ x ≤ 4 maximum of VVC(x–1) – 0.2 or VSS–0.2 minimum of VVC(x– 1)+5.5 or VSS+80 V VVC(x), x ≥ 5 maximum of VVC(x–1) – 0.2 or VSS + 2.0 minimum of VVC(x–1) + 5.5 or VSS + 80 V (7) 20 100 Ω CC External cell input capacitance(4) (7) 0.1 1 µF VO Output voltage range LD 80 V VO Output voltage range(6) CHG, DSG, CP1 85 V TOPR Operating temperature(6) 85 °C VIN Input voltage range(4) VIN Input voltage range(4) RC External cell input resistance(4) –40 0.22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 9 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.3 Recommended Operating Conditions (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MAX UNIT –5 5 mV 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 16(2) (3) –10 10 mV Cell voltage measurement accuracy(6) –0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 16(2) (3) –15 15 mV VSTACK(ACC) Stack voltage (VC16 - VSS) measurement accuracy(6) 0 V < VVC16 - VVSS < 80 V, TA = -40°C to 85°C(2) –0.5 0.5 V VPACK(ACC) PACK pin voltage measurement 0 V < VPACK < 80 V, TA = -40°C to accuracy(6) 85°C(2) –0.5 0.5 V VLD(ACC) LD pin voltage measurement accuracy(6) –0.5 0.5 V VCELL(ACC) Cell voltage measurement accuracy 2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 16(2) (3) VCELL(ACC) Cell voltage measurement accuracy(6) VCELL(ACC) (1) (2) (3) (4) (5) (6) (7) 0 V < VLD < 80 V, TA = -40°C to 85°C(2) MIN TYP Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Cell voltage accuracy is specified after completion of board offset calibration While in SLEEP mode, it is important that the cell 1 voltage measurement be validated before being considered valid. For further information and details, see Cell 1 Voltage Validation during SLEEP Mode. Specified by design Voltage on VC0 can extend higher (limited by absolute maximum specification) during cell balancing. Specified by characterization Values may need to be optimized during system design and evaluation for best performance 7.4 Thermal Information BQ76952 BQ76952 THERMAL METRIC(1) PFB (TQFP) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 66.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19.6 °C/W RθJB Junction-to-board thermal resistance 29.3 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 29.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Supply Current Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER INORMAL ISLEEP_1 10 TEST CONDITIONS MIN TYP MAX UNIT Normal Mode Regular measurements and protections active, REG1 = 3.3 V with no load, REG2 = OFF, CHG = ON in 11V overdrive mode, DSG = ON in 11V overdrive mode, Settings:Configuration:Power Config[FASTADC] = 0, no communication 286 µA SLEEP Mode Periodic protections and monitoring, no pack current, REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = ON in 11V overdrive mode, no communication, Power:Sleep:Voltage Time = 5 s 41 µA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 7.5 Supply Current (continued) Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS ISLEEP_2 SLEEP Mode Periodic protections and monitoring, no pack current, REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = source follower mode, no communication, Power:Sleep:Voltage Time = 5 s IDEEPSLEEP_1 DEEPSLEEP Mode IDEEPSLEEP_2 ISHUTDOWN (1) MIN TYP MAX UNIT 24 µA No monitoring or protections, REG1 = 3.3 V with no load, REG2 = OFF, LFO = ON, no communication 10.7 µA DEEPSLEEP Mode No monitoring or protections, REG1 = 3.3 V with no load, REG2 = OFF, LFO = OFF, no communication 9.2 µA SHUTDOWN Mode All blocks powered down, with the exception of the TS2 wakeup circuit, no monitoring or protections, no communication 1 3.1 µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.6 Digital I/O Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN 0.66 x VREG18 TYP MAX UNIT 5.5 V 0.33 x VREG18 V VIH High-level input ALERT (configured as HDQ), SCL, SDA, HDQ, CFETOFF, DFETOFF, RST_SHUT VIL Low-level input ALERT (configured as HDQ), SCL, SDA, HDQ, CFETOFF, DFETOFF, RST_SHUT VOH Output voltage high, TS2 TS2 during SHUTDOWN mode, VBAT > 6 V 4.5 6 V VOH Output voltage high, TS2 low voltage TS2 during SHUTDOWN mode, 4.7 V ≤ VBAT ≤ 6 V 3 6 V Output voltage high, 5 V case ALERT, SDA (configured as SPI_MISO), SCL (configured as SPI_SCLK), CFETOFF (configured as GPO), DFETOFF (configured as GPO), DCHG, DDSG, pins driving from REG1, VREG1 set to 5 V nominal setting, VBAT > 8 V, IOH = -5.0 mA, 10 pF load 0.9 x VREG1 VREG1 V VOL Output voltage low, 5 V case ALERT, SCL, SDA, HDQ, DCHG, DDSG, CFETOFF (configured as GPO), DFETOFF (configured as GPO), pins driving from REG1, VREG1 set to 5 V nominal setting, VBAT > 8 V, IOL = 5 mA, 10 pF load 0.77 V ROH Output weak high resistance TS2 during SHUTDOWN mode CIN Input capacitance(2) ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, REGIN, TS1, TS2, TS3 ILKG Input leakage current ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, REGIN, device in SHUTDOWN mode VOH (1) 4600 kΩ 2 pF 1 µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: BQ76952 11 BQ76952 www.ti.com SLUSE13B – JANUARY 2020 – REVISED NOVEMBER 2021 (2) Specified by design 7.7 LD Pin Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS I(PULLUP) Internal pullup current from BAT pin to LD VBAT ≥ 4.7 V, VLD = VSS pin, used for load detect functionality RPD Internal pulldown resistance on LD pin in SHUTDOWN mode (1) MIN TYP MAX UNIT 35 100 172 µA VBAT ≥ 4.7 V 80 kΩ Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(PCHG_ON) Output voltage, PCHG on max(VPACK, VBAT) - VPCHG, VPACK ≥ 8 V, VBAT ≥ 4.7 V 7.5 8.4 9.7 V V(PCHG_ON) Output voltage, PCHG on VPACK - VPCHG, 4.7 V ≤ VPACK < 8 V, VBAT ≥ 4.7 V, VPACK > VBAT VPACK V V(PDSG_ON) Output voltage, PDSG on max(VLD, VBAT) - VPDSG, VBAT ≥ 8 V 9.7 V V(PDSG_ON) Output voltage, PDSG on VBAT - VPDSG, 4.7 V ≤ VBAT < 8 V, VBAT ≥ VLD VBAT V I(PULLDOWN) Current sink capability, PCHG and PDSG PCHG and PDSG enabled, VBAT = 59.2 V (1) VPACK – 0.5 V 7.47 8.4 VBAT – 0.5 V 30 µA Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.9 FUSE Pin Functionality Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAMETER V(OH) Output voltage high (when driving fuse) TEST CONDITIONS MIN TYP MAX VBAT ≥ 8 V, CL = 1 nF, 5 kΩ load. 6 7 9 V(OH) Output voltage high (when driving fuse) 4.7 V ≤ VBAT < 8 V, CL = 1 nF, 5 kΩ load. VBAT – 1.75 V(IH) High-level input (for fuse detection) Current into device pin must be limited to maximum 2 mA 2 V(IL) Low-level input (for fuse detection) t(RISE) Output rise time (when driving fuse) (1) VBAT ≥ 8 V, CL = 1 nF, RLOAD = 5 kΩ, V(OH) = 10% to 90% of final settled voltage UNIT V V 12 V 0.7 V 0.5 µs Operation with VBAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on VBAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage. 7.10 REG18 LDO Typical values stated where TA = 25°C and VBAT = 59.2 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 80 V (unless otherwise noted)(1) PARAM