Manual / Guide · 1980
ANTIC's PENH/PENV light-pen registers, the trigger line on controller pin 6, the jack pinout and calibration advice.
ATARI® PERSONAL COMPUTER SYSTEM OPERATING SYSTEM USER'S MANUAL AND HARDWARE MANUAL NOVEMBER 1980 C016555 Every effort has been made to ensure that this manual is an accurate document. However, due to the ongoing improvement and update of the computer software and hardware, ATARI, INC. cannot guarantee the accuracy of printed material after the date of publication, nor can ATARI, INC. accept responsibility for errors or omissions. 4 TABLE OF CONTENTS I. II. INTRODUCTION DESCRIPTION OF HARDWARE A. B. C. D. E. III. I# x ANTIC and CTIA POKEY SERIAL PORT INTERRUPT SYSTEM CONTROLLERS ••!!.Il!"28 ..!!!! II ! 30 HARDWARE REGISTERS A# B. C. D. E. F. G. H. I. III.l III.l !lll!3 ..•III! AUDIO KEYBOARD and SPEAKER SERIAL PORT CONTROLLER PORTS IIl!l2 !!!lll!l5 ...IIl!l7 ••!!!lll!l9 SAMPLE DISPLAY PROGRAM V. HARDWARE REGISTER LISTS A. B. III.l PAL INTERRUPT CONTROL TV LINE CONTROL GRAPHICS CONTROL PLAYERS AND MISSILES IV. VI. # !!!!!ll. 23 ...!!!!! !ll!25 III! 9 v. 1 ADDRESS ORDER ALPHABETICAL ORDER v# i !!!!!!!v!5 FIGURES A. B. C. VI#1 MEMORY MAP NTSC and PAL DISPLAY SCHEMATICS APPENDIX A: VI#1 ..!!!!! !vi!2 !vi!3 USE OF PLAYER/MISSILE GRAPHICS WITH BASIC APPENDIX B: MIXING GRAPHICS MODES APPENDIX PINOUTS C: ii • I. INTRODUCTION The ATARI (R) 800™ and ATARI 400™ Personal Computer Systems contain a 6502 microprocessor, 4 1/0 chips, operating system ROM, expandable RAM, and several MSI chips for address decoding and data bus buffering. This manual is primarily intended to describe the 4 1/0 chips in sufficent detail to allow experienced programmers to create assembly language programs, such as video games. All four Input /Output chips are controlled by the microprocessor by writing directly into their registers which are decoded to exist in microprocessor memory space just as RAM does. These I/O chips can also be interrogated by the microprocessor by reading similar registers. Many registers are write only and cannot be read after they are written. In some cases, reading from the same address gives the value contained in a separate read only register. Some write only registers are strobes. No data bits are needed in this case since the presence of the address on the bus is what triggers the requested action. The usual convention is to use the STA (Store Accumulator) instruction for such registers. For example, STA WSYNC performs the wait for Sync function. STX (Store X) or STY (Store Y) would work just as well. In BASIC, a POKE could be used (the data could be anything). Reading a register is accomplished by using any of the load instructions (LDA, LDX etc.). In BASIC a PEEK would be used. When the hardware register names are defined in an equate list, the programmer can refer to the registers by name rather than using the addresses directly. It is really not necessary for the programmer to know which I/O functions are performed by which of the 4 chips, however it does help in learning these functions. This manual should be used in conjunction with the Operating System (OS) Manual, a 6502 programming manual, and the ATARI 400/800 Basic Reference Manual . CHIP NAME FUNCTION ANTIC DMA (Direct Memory Access) control NMI (Non-Maskable Interrupt) control Vertical and Horizontal fine scrolling Light pen position registers Vertical line counter WSYNC (wait for horizontal sync) CTIA Priority control (display of overlapping objects) Color-Lumimance control (colors and brightness assigned to all objects including DMA objects from ANTIC) PLAYER-MISSILE objects (4 players and 4 missiles) Graphics registers Size control Horizontal position control Collision detection between all objects Switches and triggers (miscellaneous I/O functions) 1.1 CHIP NAME FUNCTION POKEY Keyboard scan and control Serial communications port (bidirectional) Pot scan (digitizes position of 8 independent pots) Audio generation (4 channels) Timers IRQ (maskable interrupt) control from peripherals Random number generator PIA Controller (Joystick) jacks read or write Peripheral control and interrupt lines IRQ (maskable) interrupt control from peripherals Section II describes the hardware in some detail, including the various graphics modes. Section III lists the hardware registers one at a time, describing what each bit is used for. It is organized by functional groups (interrupts, graphics, audio, etc.). Section IV contains a sample display program. Section V contains various figures and block diagrams of the system. Sections VI and VII list the hardware registers in address order and alphabetical order. Section VII includes hex and decimal addresses, the OS shadow registers and the page numbers where more information can be found. \ 1.2 0 DESCRIPTION OF HARDWARE A. ANTIC AND CTIA A? VP JO II. \ 4 4 05 TV Display The AN' :C and CTIA chips gei the television display at the rate of j60 frames per second on the NTSC (US) system, The PAL (European) sys/tem is different and Is described in the section on NTSC vs PAL. Each^ frame consists of 262 horizontal TV lines and each up of (22§ color clocks, as shown in figure VI-3. The 6502 microprocessor runsv~al 1.79 MHz. This rate was chosen so that one machine cycle is equivalent in length to two color clocks. One clock is approximately equal in width to two TV lines. : In any graphics mode, the display is divided up into small squares or rectangles called pixels (picture elements). The highest resolution graphics mode has a pixel size of 1/2 color clock by 1 TV line. A sample display list is given in section IV. The current TV line may be determined by reading the vertical counter (VCOUNT) This gives the line count divided by 2. There are 262 lines per frame so VCOUNT runs from 0 to 130 (0 to 155 on the PAL system). The 0 point occurs near the end of vertical blank (see figure VI. 5). Vertical blank (VBLANK) is the time during which the electron beam returns back to the top of the screen in preparation for the next frame. The Atari 800 does not do interlacing, so each frame is identical unless the program which is being executed changes the display. Vertical sync (VSYNC) occurs during the fourth through sixth lines of vertical blank (VCOUNT = hex 7D through 7F) . This tells the TV set where each frame starts. After VSYNC, there are 16 more lines of VBLANK for a total of 22 lines of VBLANK. The display list jump and wait instruction (to be described later) causes the display list graphics to start at the end of VBLANK. VCOUkjT O -ISO 22. I**** <t>-2.nn ; Operating System (OS) The ATARI 400/800 comes with a 10K Operating ! System (OS) in ROM. The OS affects some of the hardware registers, so it will be mentioned from time to time in this manual. Refer to the OS manual for more details. The OS descriptions in this manual apply to the version that was being distributed when this manual was written. : The OS supports most of the hardware graphics modes (BASICS, GRAPHICS, PLOT, and DRAWTO commands). The OS always displays 24 background lines after the end of vertical blank. This convention is used at Atari to compensate for television sets which overscan. Most TV's are designed so that the edges of the picture are cut off. This is fine for ordinary broadcasts, but with a computer it is essential for all important information to be displayed on the screen. It is fairly common for four to eight color clocks at the right or left edge of the picture to overscan. A TV set that has excessive overscan may have to readjusted to obtain a satisfactory display. II. s-n>. The OS uses 192 TV lines for its display and devotes the remaining 24 lines to overscan. It uses the standard display width of 160 color clocks. The hardware will allow displays of any length, but it is recommended that the standards be followed. The exception might be a border or other information which is merely decorative and not essential to use of the program. OS Shadowing Since many of the hardware registers are write-only and cannot be read^ the OS has a number of "shadow registers in RAM. Every TV frame(during vertical blank) the OS takes the values in some of its shadow registers, and writes them out to the corresponding hardware register. The OS does attract color shifting on all of the color registers if ATRACT (on OS register) is negative. This is to prevent damage to the TV screen phosphors which can occur if the brightness is turned up too high and the same high- luminance display is left on for a long time. The OS also reads the joysticks and other controllers during vertical blank and stores t he results i n sha dow registers, so that user programs do not nave to include code to unpack thlfdata. There are a few interrupt-related registers which the OS changes or reads during interrupt processing. Programs usually access the OS shadow registers instead of accessing the hardware directly. However, the OS shadowing can be disabled by changing the vertical blank and interrupt vectors (see OS manual). : 11 WSYNC: In addition to a Vertical Blank Interrupt, which allows the Microprocessor to synchronize jto the vertical TV display, this system also provides a Wait for (Horizontals/Sync (WSYNC ) command that allows the microprocessor to synchronize itself to the TV horizontal line rate. This sync takes effect when the processor writes to an I/O location called WSYNC, whenever it desires horizontal synchronization. Writing to this address sets a latch which pulls (to zero) a pin on the microprocessor called READY. When READY goes to zero the microprocessor stops and waits. The latch is automatically reset (returning READY true) at the beginning of the next horizontal blank interval, releasing the microprocessor to resume program execution. The primary function of the Antic Object DMA (Direct Memory Access) chip is to fetch data from memory (independent of the microprocessor) for display on the TV screen. It does this with a technique called "Direct Memory Access" or DMA. It requests the use of the memory address and data bus by sending a signal called HALT to the microprocessor, causing the processor to become "TRI-STATE" (open circuit) all during the next computer The ANTIC chip then takes over the address bus and reads any data cycle. Another name for this type of DMA is "cycle stealing". it wishes from memory. Once initiated, this DMA is completely and automatically controlled by the Antic chip without need for futher microprocessor intervention. : There are two types of DMA: Playfield and PJ^ayer-Missile (see Figure II. 2). The playfield DMA control circuit on the Antic chip resembles a small dumb microprocessor. By halting the main microprocessor it can fetch its own instructions from memory (the display list) addressed by its program counter (display list pointer). Each instruction defines the type (alpha character or memory map) and the resolution (size of bits on the screen) and the location of the data in memory which is to be displayed on the next group of lines. , , II. 3 In order to begin this DMA the main microprocessor must store a display list of instructions in memory, store data to be displayed in memory, tell the ANTIC where the display list is (initialize the display list pointer) and enable the DMA control flags on the ANTIC (DMACTL register). In addition to the playfield DMA described above, the ANTIC chip simultaneously controls another DMA channel. This type of DMA addresses PLAYER-MISSILE graphics data stored in memory and passes the graphics data on to the CTIA chip graphics registers. This type of DMA (if enabled) occurs automatically, interspersed with the playfield DMA described previously. This PLAYER-MISSILE DMA has no display list or instructions, and is therefore much simpler than the PLAYFIELD DMA. In addition to the two types of display DMA, the ANTIC chip also generates DMA addresses for the refresh of the dynamic memory RAM used in this system. This is also completely automatic and need be consider-^ ^300^0^ /~zrv ()^ * ed by the programmer only if he is concerned with real-time programming h CrwX^ (LAffUU* is important. cycles computer the of count where an exact 1 A color-luminance register is used on the CTIA chip Color-luminance Each color-lum register is for each Player-Missile and Playfield type. loaded by the microprocessor with a code representing the desired color As and luminance of its corresponding Player-Missile or Playfield type. the serial data passes through the CTIA chip it is "impressed" with the color and luminance values contained in these registers, before being sent In areas of the screen where there are no objects the to the TV display. background color (COLBK) is displayed. The CTIA also does collision detection (to be described later). : When moving objects, such as players and missiles, Priority overlap on the TV screen (with each other or with Playfield) a decision must be made as to which object shows in front of the other. Objects which appear to pass in front of others are said to have Priority over them. Priority is assigned to all objects by the CTIA chip before the serial data from each object is combined with the other objects and sent to the TV screen. ; The priority of objects can be controlled by the microprocessor by writing into the control register PRIOR. The functions of the bits in this register are given in the table in the PRIOR register description in section III. The players and missiles are small objects Players and Missiles which can be moved quickly in the horizontal direction by changing their position registers. They are called players and missiles because they were originally designed to be used in games for objects such as airplanes and bullets. However, there are many other possible applications for The four player-missile color registers, in conjunction with the them. four playfield color registers and the background color register, make it possible to display 9 different colors at the same time. : II. OBJECTS (no objects - background) n I GRAPHICS 4 PLAY ERS ~$ A PLAYFIELD MISSILES MEMORY MAP CHARACTERS controlled by Display list instructions vP-^Qr<GRACTL) (DMACTL) 6 Player •Missile DMA Enable Playfield DMA Enable 1 MICRO PROCESSOR Figure II. 2 OBJECT DISPLAY II. SOURCES There are a total of four players and four missiles. The four missiles may be grouped together and used as a 5th player. These objects are positioned horizontally by 8 horizontal position registers These registers may be reloaded at any time by the proces(HPOS (X)). sor, allowing an object to be replicated many times across a horizontal TV line. The shape of a player-missile is determined by the data in its graphics register (GRAF (X)). Players have independent 8 bit graphics registers. The four missiles have 2 bit registers (located within one address). These registers may also be reloaded at any time by the processor, although they are usually changed during horizontal blank The data in each graphics register is placed on the display time. whenever the horizontal sync counter equals the corresponding horizonunless tal position register. The same data will be displayed every line the graphic registers are reloaded with new data. The player-missile graphic registers may be reloaded by the microprocessor (GRAF (X))f^or automatically from memory with direct memory access (DMA) (see figure II. 3). The programmer must place the object graphics in memory, write the player-missile base address (PMBASE) , and enable player-missile DMA (DMACTL, GRACTL) «\ The transfer of object / graphics from memory to display is then fullV automatic. g p v^w^b^ uf^ PMBASE specifies the mo/t significant byte (MSB) of the address of the player-missile graphics!' The location of the graphics for each object is determined by adding an offset to PMBASE *256 (decimal). The bytes between the base address and the missile data are not used by Antic, so they are available to the programmer. Only the five most significant bits of PMBASE are used with single-line resolution and the six most significant bits are used with two-line resolution. This means that the location of the graphics resoluin memory is restricted to certain page boundaries.. Two-line (see lines. two tion means that each byte of data is repeated for two-line for required 640 (decimal) bytes (5X128) are DMACTL, bit 4). resolution and 1280 bytes (5x256) for one-line resolution. which Each byte in the player graphics area represents eight pixels A screen. TV the of line(s) corresponding are to be displayed on the pixel. that in displayed be to is color-lum player's 1 indicates that the figure The graphics may be anything, not just rectangles like the ones in or screen the of height entire the fill may graphics player The II. 3. is data display the of they may be only a couple of lines high if the rest pixels, eight represents also Each byte in the missile display all 0's. Each pixel may be 1, 2, or 4 color clocks, two pixels for each missile. registers. SIZE and is determined by the Playfield is always generated by DMA. There are four Playfield playfields, each identified by its own color-lum register and collision detection. Playfield is generated by two different DMA techniques: in memory map and character. Both methods provide lists of instructions generation. memory, independent of the player-missile : II. 5 Player-Missile Base Address (PMBASE) - MSB of address. Resolution is controlled by bit 4 of DMACTL. PMBASE*100(hex) ADDRESS Two-line resolution OFFSET One-line resolution (hex) (hex) i Key +180 Ct>,) (3^ +300 rfc-r 3 2 10 Missile Number TV SCREEN FT T I 1 i +400 O**) f>$( +200 (S\Z) i M2 I I I I I I l y 0oHo~) P3I P2 y 1 I M0 I P0 +280 I i P0l PI L Ml M3 +300 Ct(of) PI Horizontal position "for each object is set +380 Otk) independently by 8 horizontal position registers. f3 +400 (>2.h) +800 Each section of memory maps directly onto total height of TV screen. Object vertical position is determined only by its location in its section of memory. One byte of memory equals 1 or 2 television lines vertically. Player-Missile Vertical screen map in memory Figure II. PLAYER-MISSILE II. DMA 7 Unlike players and missiles, there are no horizontal position registers (Each player can only have one byte of display per line.) playfield. for Playfield, on the other" hand, may require up to 48 bytes per line because it can fill the entire width of the screen. There are three different playfield widths: narrow (128 color clocks), standard (160 color clocks), and wide (192 color clocks). The width is selected by storing into DMACTL. The advantage of a narrower width is that less RAM is required and fewer machine cycles are stolen for The OS graphics modes use the standard screen width. DMA. The display list is a sequence of display instructions Display List stored in memory. These instructions are either one (1) byte or three (3) bytes long. The display list can be considered a display program, and the Display List Counter that fetches these instructions can be thought of as (10 bit counter plus 6 bit base register.) a display program counter. ; The display list counter can be initialized by writing to DLISTH and Once initialized, (or OS shadow registers SDLSTH and SDLSTL). DL1STL. this counter value is used to address the display list, fetch the instruction, display one (1) to sixteen (16) lines of data on the TV screen, increment the Display List Counter, fetch the next display instruction, and so on automatically without microprocessor control (see DL1STL and ffDLISTH). DLISTL and DLISTH should be altered only during vertical blank For when DMA is disabled (see DMACTL). Each instruction defines the type (alpha character or memory map) and (size of bits on screen) and the location of data in memory resolution the Each group of lines is to be displayed for a group (1 to 16) of lines. called a display block. THE DISPLAY LIST CANNOT CROSS A IK BYTE MEMORY BOUNDARY UNLESS A JUMP INSTRUCTION IS USED. DLISTL (LSB) DLISTH (MSB) Fixed (6 bits) Counter (10 bits) DISPLAY LIST COUNTER II. 8 Display Instruction Format Each instruction consists of either an opcode only, or of an opcode followed by two (2) bytes of operand. : lOpcodel Single Byte Display Instruction lOpcodel I Operand I Triple Byte Display Instruction ) foperand"! The opcode is always fetched first and placed in the Instruction Register. This opcode defines the type of instruction (1 or 3 bytes) and will cause two more bytes to be fetched if needed. If fetched, these next two (2) bytes will be placed in the Memory Scan Counter ! or in the Display List Counter (if the instruction is a Jump). Display Instruction Register (IR) ; This register is loaded with the opcode of the current display list instruction. It cannot be accessed directly by the programmer. There are three basic types of display list instructions: blank, jump, and display. Blank r> (1-byte) 0 O ° |P7lD6lD5lD4l 01 01 0| Q| This instruction is used to create Jx> t^^isplay (blackground color). color 4- # to 8 blank lines on the €ir 07 D6 - D4 D3 - DO Jump (3-bytes) 1 m display list instruction interrupt I 0-7 = 1-8 blank lines - blank 0 /*>» 1 Id7ID6I XI Xl 01 01 01 1| i This instruction is used to reload the Display List Counter. The next two bytes specify the address to be loaded (LSB first) D7 D6 1 0 1 D5-D4 D3-D0 X 1 display list instruction interrupt jump (creates one blank line on display) jump and wait until end of next vertical blank 0 * 1 don't care jump & Display (1 p Oft or 3 bytes) I c -en b t 7 I |D7iD6lD5lD4lD3lD2lDlTD0l 1 This instruction specifies the type of display for the next display block *wky\*x0 D7 D6 1 0 1 4 D5 D4 D3-D0 1 1 2-F display list instruction interrupt 1 byte instruction 3 byte instruction (reload Memory Scan Counter using address in next two bytes, LSB first). vertical scroll enable horizontal scroll enable display mode (memory or character map see following pages). II. > 3 0 cO o 0 rH O PQ a) CD 4-) •H 4-» O 0 U CO M CD > O CO 00 a CO •H rH c rH •H O rH V-i rH a O O M 0 CD O 0 •H •H o CD CD 3 rH CO c O *H •H *H X! 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The display list intirrup? code can change the colors or graphics during the middle of the TV display? yPe interru Pt is determined by checking NMIST. NMIRES clears NMIST. T? The current OS will vector through VDSLST (Hex 200 and 201) to P 8 the ° S *anual for m^ P«£~ " ^ ^details l8play type ° f dis P la l^t instructions are y used tn ! t to enable vertical and horizontal scrolling. The amount of scrolling depends on the values in the VSCROL and HSCROL registers (to be descrribed ^\ Memory Scan Counter; This counter is not directly accessible by the programmer. It is loaded with the value in the last 2 bytes of a 3 y byte (non-Jump) instruction. l8 er P° ints the location (address) in memory of data be ^^M directly ^°T displayed (memory map display) or the location of character name strings be indirectly displayed (character display). mtre $q A.... single byte instruction does not reload this counter. to to to to d<5pl*yf«f fK, tyfrjC , T^iis implies^ a continuation in memory of data to be displayed from that displayed by X the previous instruction. Since this counter really consists of bits of A f Ct al COUnter a continuous m emory block cannot cross ! ? Ikw! 4K byte ™ memory K° boundaries, unless the counter is repositioned with a 3 1 » byte Load Memory Scan Counter instruction. MSB third byte of 3-byte byte instruction LSB Second byte of 3byte instruction I I \ \~ 716151 41312(1 in I I7I6I5I4I3I2I1I0 Fixed (4 bits) i I Counter (12 bits) \ Memory Map Display Instructions; Data in memory (addressed by the Memory Scan Counter) is displayed directly when executing a memory (bit) map display instruction. As data is being displayed it is also stored in a shift register so that it can be redisplayed for as many TV lines as required by the instruction. 11.10 if Memory Scan Counter Addresses each byte Memory One line worth of memory is loaded into the shift register Shift Register r i i i i i i i * \ i i i i 1 1 1 1 1 1 1 Til Shift register data is displayed for four TV scan lines in this example. In Instruction Register (IR) display modes 8 through F, one or two bits of memory are used to specify what is to be displayed on each pixel Pixel sizes range from 1/2 clock by 1 TV line to 4 clocks of the screen. The OS and BASIC support most of these graphics modes lines. by 8 TV Two modes, C and E, are not supported by the (BASIC GRAPHICS command). These modes have rectangular pixels, which are approximately twice as OS. wide as they are high. can be displayed. Two different In IR mode F, only one color (C0LPF2) luminances are available. If a bit is a zero, then the luminance of the corresponding pixel comes from C0LPF2. If the bit is a one, them the luminance is determined by the contents of C0LPF1 (abbreviated to PF1). In IR modes 9,B, and C, two different colors can be displayed. zero indicates background color and a one indicates PFO color. The difference between the various modes is in the size of the pixels. A In IR modes 8,A,D, and E, two bits are used to specify the color This allows four different colors to be displayed. of each pixel. However, only four pixels can be packed into each byte, instead of eight The bit assignments are shown below. as in the previous modes. SHIFT REGISTER I 7 6 I 5 4 j 3 2 I 1 0 I 7 6 1 5 4 I 3 2 I 2 11.11 1 0 I bits form one pixel Memory Map Display Modes | | | | 1 OS IColors and llnst. per BASIC Reg. Mode Modes HEX 1 1 I 3 1 4 1 1 8 1 I 4 I 1 9 1 1 Pixels Bytes Scan Color Bit per per Lines Clocks |Bits lvalues Color Std. IStd. per per per in Reg. Line Line Pixel Pixel Pixel Pixel Select 00 BAR 40 10 8 4 2 01 PF0 10 PF1 11 PF2 I I I 1 | | 1 1 1 1 1 1 1 1 I 1 I I 1 I | 1 1 I 1 1 2 I 80 1 10 1 4 1 1 2 I 1 1 1 1 0 | I 1 I 00 1 5 1 1 A 1 1 4 I 80 I 20 1 1 4 1 1 2 1 2 1 1 1 01 io I 1 11 1 6 j 1 B | 1 2 I 160 1 20 ! 2 1 - | 1 1 ! 1 f 1 c 1 2 1 1 I 160 | 20 ! 1 1 | 1. 1 ! 1 l 1 1 1 | 1 o 1 00 7 I D 1 | 4 I 160 2 | I 1 1 2 I 1 1 1 r 1 oi io 11 1 1 I 00 - 1 1 E I 4 I 160 | 40 | 1 1 1 l | 2 I 1 oi 10 1 • | 11 8 iH I 1 1 1 1 | 320 | 40 | 1 1 1 1 h | 1 | BAR PF0 PF1 PF2 BAR PF0 0 1 1 BAR PF0 0 1 1 1 1 BAR PF0 BAR PF0 PF1 PF2 BAR PF0 PF1 PF2 PF2 PF1 (LUM) ! | | | i . The first step in using the character Character Display Instructions map mode is to create a character set in memory (or the built-in OS character set at hex E000 may be used) . The character set contains eight bytes of data for the graphics for each character. The meaning of the data depends on the mode. The character set can contain 64 or 128 characters, of the also depending on the mode. The MSB (Most Significant Byte) address of the character set is stored in CHBASE (or the OS Shadow CHBAS) Only the most significant six or seven bits of CHBAS are used (see CHBASE description in section III). The other one or two bits and the LSB of the address are assumed to be zero, so the character set must start at an acceptable page boundary. : The next step is to set up the display list for the desired mode. Then the actual display is set up. This consists of a string of character names or codes. Each name takes one byte. The last 6 or 7 bits of the name selects a character. For a 64 character set, the name would range from 0 through 63 (decimal). For a 128 character set, the range would be The upper one or two bits of the name byte are 0 through 127 (decimal). used to specify the color or other special information, depending on the mode. Character names (codes) are fetched by the memory scan counter, and are placed in a shift register. On any given line of display the shift register rotates, changing only the name portion of the character address as shown below. £u>y^~ J After a full /lin^) of character data has been displayed the 3-ine^ counter will increment. The next line again addresses all characters by name for that line number. In 20 character per line modes the seven most significant bits of CHBASE are used. This requires that the character set to start upon a 512 byte memory boundary. The set must contain 64 charcters, 8 bytes each, giving a total of 512 bytes for the set. The 40 character per line modes use the six most significant bits of CHBASE, forcing the character set to start on a IK byte memory boundary. The set must have 128 characters of 8 bytes each. This gives a total of 1024 bytes for the set. | j Graphics Mode Hex Code Chars. Per Line 1 Number of j Bytes per Char. I Colors | | Number of Char. in set Bytes in Char Set j | | 1 1 2 0 40 2 8 128 1024 40 2 8 128 1024 4 8 128 1024 4 Q 128 | 1 3 - 4 40 15 1-1 1 +— *— 1 1 7 1 40 1 1024 1 1 I 1 1 2 1 1 20 20 5 1 11.13 5 ! 8 64 512 8 64 512 | Character Display Internal codes for characters in memory (20 Character per line mode example) Codes (names) Stored in Shift Reg Shift 1 1 1 1 1 1 1 1 1 1 1 1 Register Color Register Select Address portion of Character name CHBASE Character Set in Memory Addresses data in character set and displays on the TV TV Scan Lines Color assigned by color register selected 11.14 There are six charcter map modes, IR modes 2 through 7. Modes 2,6 and 7 are supported by the OS and BASIC (GRAPHICS 0,1 and 2). In IR modes 6 and 7, the upper two bits of each character name select one of four playfield colors. For each data bit that contains a one, the selected playfield color is displayed. For each zero data bit, the background color is displayed. The four character colors plus the background color gives a total of five different colors, the mode 6 characters are eight lines high and the mode 7 characters are sixteen lines high (each data byte is displayed for two lines). In IR modes 4 and 5, each character is only four pixels wide instead Two bits per pixel of data are used to of eight (as in the other modes) . Seven name bits are or background. ld colors, playfie three of one select used to select the character. If the most significant name bit is a zeroj PF-?. If the name bit 7 is one. then data (binary) selects PFl. then data of ^select PFl.^r This makes it possible to display two characters bits of th different colors, using the same data but different name bytes. ^Jgge and 3, each pixel is half of a color clock in width. CoOr^erJ is makes it possible to have forty (4ight-pixel-wide)characters in a standard width line. These modes are similar to memory mode F in that two luminances can be displayed, but only one color is available at a time. This makes it possible to In IR mode 3, each character is 10 lines high. define lower case characters with descenders. The last fourth of the character set (name bits 5 and 6 equal to one) is lowered. The hardware takes the first two data bytes and moves them to the bottom of the character, displaying two blank lines at the top of the character (see next page). In IR modes 2 In IR modes 2 and 3, bit 7 of the character name is used for inverse video or blanking. This is controlled by CHACTL (Character Control). If bit 2 of CHACTL is a one then all of the characters will be displayed upside down, regardless of mode. If CHACTL bit 1 is set, then each character which has bit 7 of its name set will be displayed in inverse video (the luminances will be reversed). If CHACTL bit 0 is set, then each character which has bit 7 set will be blanked (only background wil be Characters can be blinked on and off by setting name bit 7 to displayed). Inverse video and blank apply only to IR 1 and toggling CHACTL bit 0. modes 2 and 3. If both inverse video and blank are set then the character will appear as an inverse video blank character (solid square). 60 bits of collision register are Hardware Collision Detection (hits) between players, missiles and overlap store and detect provided to playfield. These collisions can be read by the microprocessor from addresses D000 through DOOF. There are no bits for missile to missile collisions. : 16 16 16 12 bits bits bits bits for Missile to Playfield for Player to Playfield for Missile to Player for Player to Player (PO to PO always reads as zero, etc.) NOTE: The 1/2 clock memory map mode (IR code 1111) and the 1/2 clock Character mode (IR codes 0011 and 0010) are both playfield type 2 collisions and will be stored in bit 2 of the playfield collision registers. pu^faM>fc \% tA** ****** , le.vi^x my 11.15 IR Mode 3-Upper and Lower Case Upper Case Lower Case Data Actual Display 11.16 c jz c co «c o ~ »- o <o > ^5 CD cc jz CM OJ oo CD c5o.tr * E * o O c r C£ o -C CD CO o — o CO CO LU d CL 5 z E~ n >s CD a) -Q D CD O at>- O 3 "O £ g E o w— « jS a! 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