Datasheet · 2014
Three-axis ±200 g digital (SPI/I2C) accelerometer with a FIFO and shock detection; the digital alternative for recoil measurement.
3-Axis, ±200 g Digital MEMS Accelerometer ADXL375 Data Sheet FEATURES GENERAL DESCRIPTION Low power: as low as 35 µA in measurement mode and 0.1 µA in standby mode at VS = 2.5 V Power consumption scales automatically with bandwidth Embedded, 32-level FIFO buffer minimizes processor load Bandwidth of up to 1 kHz Bandwidth selectable via serial command Shock event detection Activity/inactivity monitoring Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to VS SPI (3- or 4-wire) and I2C digital interfaces Wide temperature range: −40°C to +85°C 10,000 g shock survival Pb free/RoHS compliant Small and thin: 3 mm × 5 mm × 1 mm LGA package The ADXL375 is a small, thin, 3-axis accelerometer that provides low power consumption and high resolution measurement up to ±200 g. The digital output data is formatted as 16-bit, twos complement data and is accessible through a SPI (3- or 4-wire) or I2C digital interface. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL375 is supplied in a small, thin, 3 mm × 5 mm × 1 mm, 14-lead LGA. APPLICATIONS Concussion and head trauma detection High force event detection FUNCTIONAL BLOCK DIAGRAM VS ADXL375 VDD I/O POWER MANAGEMENT ADC 3-AXIS SENSOR DIGITAL FILTER 32-LEVEL FIFO CONTROL AND INTERRUPT LOGIC INT1 INT2 SDA/SDI/SDIO SERIAL I/O SDO/ALT ADDRESS SCL/SCLK CS GND 11669-001 SENSE ELECTRONICS Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADXL375 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Communications ................................................................. 15 Applications ....................................................................................... 1 SPI Mode ..................................................................................... 15 General Description ......................................................................... 1 I2C Mode...................................................................................... 18 Functional Block Diagram .............................................................. 1 Register Map ................................................................................... 20 Revision History ............................................................................... 2 Register Descriptions ................................................................. 21 Specifications..................................................................................... 3 Applications Information .............................................................. 26 Absolute Maximum Ratings ............................................................ 4 Power Supply Decoupling ......................................................... 26 Thermal Resistance ...................................................................... 4 Mechanical Considerations for Mounting .............................. 26 ESD Caution .................................................................................. 4 Shock Detection ......................................................................... 26 Soldering Profile ........................................................................... 5 Threshold Detection and Bandwidth ...................................... 27 Pin Configuration and Function Descriptions ............................. 6 Link Mode ................................................................................... 27 Typical Performance Characteristics ............................................. 7 Sleep Mode vs. Low Power Mode............................................. 28 Theory of Operation ...................................................................... 10 Offset Calibration ....................................................................... 28 Power Sequencing ...................................................................... 10 Current Consumption and Output Data Rate ........................ 10 Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz ................................................................................ 28 Power Saving Modes .................................................................. 11 Using Self-Test ............................................................................ 29 FIFO Buffer ................................................................................. 11 Axes of Acceleration Sensitivity ............................................... 30 Self-Test........................................................................................ 12 Layout and Design Recommendations ................................... 31 Interrupts ......................................................................................... 13 Package Information .................................................................. 31 Enabling and Disabling Interrupts ........................................... 13 Outline Dimensions ....................................................................... 32 Clearing Interrupts ..................................................................... 13 Ordering Guide .......................................................................... 32 Bits in the Interrupt Registers ................................................... 13 REVISION HISTORY 4/14—Rev. A to Rev. B Changes to Figure 24 ...................................................................... 15 Changes to Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Section .............................................. 21 9/13—Rev. 0 to Rev. A Added MEMS to Product Title ....................................................... 1 8/13—Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet ADXL375 SPECIFICATIONS TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unless otherwise noted. Table 1. Parameter SENSOR INPUT Measurement Range2 Nonlinearity Cross-Axis Sensitivity3 SENSITIVITY Sensitivity at XOUT, YOUT, ZOUT2, 4 Scale Factor at XOUT, YOUT, ZOUT2, 4 Sensitivity Change Due to Temperature 0 g OFFSET 0 g Output for XOUT, YOUT, ZOUT 0 g Offset vs. Temperature NOISE OUTPUT DATA RATE AND BANDWIDTH5 Output Data Rate (ODR)4, 6 SELF-TEST7 Output Change in Z-Axis POWER SUPPLY Operating Voltage Range (VS) Interface Voltage Range (VDD I/O) Supply Current Measurement Mode Standby Mode Turn-On and Wake-Up Time8 TEMPERATURE Operating Temperature Range WEIGHT Device Weight Test Conditions/Comments Each axis Min Typ1 ±180 ±200 ±0.25 ±2.5 18.4 44 20.5 49 ±0.02 22.6 54 LSB/g mg/LSB %/°C −6000 ±400 ±10 5 +6000 mg mg/°C mg/√Hz 3200 Hz Percentage of full scale Each axis ODR ≤ 800 Hz ODR ≤ 800 Hz Max Unit g % % Each axis X-, y-, and z-axes User selectable 0.1 g 6.4 2.0 1.7 ODR ≥ 100 Hz ODR ≤ 3 Hz 2.5 1.8 3.6 VS 145 35 0.1 1.4 ODR = 3200 Hz −40 µA µA µA ms +85 30 V V °C mg Typical specifications are for at least 68% of the population of parts and are based on the worst case of mean ± 1 σ distribution, except for sensitivity, which represents the target value. 2 Minimum and maximum specifications represent the worst case of mean ± 3 σ distribution and are not guaranteed in production. 3 Cross-axis sensitivity is defined as coupling between any two axes. 4 The output format for the 1600 Hz and 3200 Hz output data rates is different from the output format for the other output data rates. For more information, see the Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz section. 5 Bandwidth is the −3 dB frequency and is half the output data rate: bandwidth = ODR/2. 6 Output data rates < 6.25 Hz exhibit additional offset shift with increased temperature. 7 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). For the self-test to operate correctly, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C). 8 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 ms, where τ = 1/(data rate). 1 Rev. B | Page 3 of 32 ADXL375 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Acceleration, Any Axis Unpowered Powered VS VDD I/O Digital Pins Output Short-Circuit Duration (Any Pin to Ground) Temperature Range Powered Storage θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating 10,000 g 10,000 g −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to VDD I/O + 0.3 V or 3.9 V, whichever is less Indefinite Table 3. Package Characteristics Package Type 14-Terminal LGA ESD CAUTION −40°C to +105°C −40°C to +105°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 4 of 32 θJA 150 θJC 85 Unit °C/W Data Sheet ADXL375 SOLDERING PROFILE Figure 2 and Table 4 provide information about the recommended soldering profile. CRITICAL ZONE TL TO TP tP TP tL TSMAX TSMIN tS RAMP-DOWN PREHEAT 11669-015 TEMPERATURE RAMP-UP TL t25°C TO PEAK TIME Figure 2. Recommended Soldering Profile Table 4. Recommended Soldering Profile Limits1, 2 Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time from TSMIN to TSMAX (tS) Ramp-Up Rate (TSMAX to TL) Liquidous Temperature (TL) Time Maintained Above TL (tL) Peak Temperature (TP) Time Within 5°C of Actual TP (tP) Ramp-Down Rate Time 25°C (t25°C) to Peak Temperature 1 2 Sn63/Pb37 3°C/sec maximum Pb-Free 3°C/sec maximum 100°C 150°C 60 sec to 120 sec 3°C/sec maximum 183°C 60 sec to 150 sec 240°C +0°C/−5°C 10 sec to 30 sec 6°C/sec maximum 6 minutes maximum 150°C 200°C 60 sec to 180 sec 3°C/sec maximum 217°C 60 sec to 150 sec 260°C +0°C/−5°C 20 sec to 40 sec 6°C/sec maximum 8 minutes maximum Based on JEDEC Standard J-STD-020D.1. For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. B | Page 5 of 32 ADXL375 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADXL375 TOP VIEW (Not to Scale) SCL/SCLK VDD I/O 1 GND 2 RESERVED 3 14 13 SDA/SDI/SDIO 12 SDO/ALT ADDRESS 11 RESERVED 10 NC 9 INT2 8 INT1 +X GND 4 GND 5 VS 6 +Y +Z 7 11669-002 CS NOTES 1. NC = NOT INTERNALLY CONNECTED. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic VDD I/O GND RESERVED GND GND VS CS INT1 INT2 NC RESERVED SDO/ALT ADDRESS SDA/SDI/SDIO SCL/SCLK Description Digital Interface Supply Voltage. Ground. This pin must be connected to ground. Reserved. This pin must be connected to VS or left open. Ground. This pin must be connected to ground. Ground. This pin must be connected to ground. Supply Voltage. Chip Select. Interrupt 1 Output. Interrupt 2 Output. Not Internally Connected. Reserved. This pin must be connected to ground or left open. SPI 4-Wire Serial Data Output (SDO)/I2C Alternate Address Select (ALT ADDRESS). I2C Serial Data (SDA)/SPI 4-Wire Serial Data Input (SDI)/SPI 3-Wire Serial Data Input and Output (SDIO). I2C Serial Communications Clock (SCL)/SPI Serial Communications Clock (SCLK). Rev. B | Page 6 of 32 Data Sheet ADXL375 TYPICAL PERFORMANCE CHARACTERISTICS 25 1.0 0.6 OFFSET DRIFT (g) 20 15 10 0.4 0.2 0 –0.2 –0.4 –0.8 –1.0 –50 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1.4 –1.8 –2.2 –2.6 –3.0 0 11669-203 –0.6 5 11669-200 PERCENT OF POPULATION (%) 0.8 –35 –20 –5 10 25 40 55 TEMPERATURE (°C) 70 85 100 OFFSET (g) Figure 7. X-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.5 V 25 1.0 OFFSET DRIFT (g) 0.6 15 10 0.4 0.2 0 –0.2 –0.4 –0.8 –1.0 –50 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1.4 –1.8 –2.2 –2.6 –3.0 0 11669-204 –0.6 5 11669-201 PERCENT OF POPULATION (%) 0.8 20 –35 –20 –5 10 25 40 55 TEMPERATURE (°C) 70 85 100 OFFSET (g) Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.5 V Figure 8. Y-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V 16 1.0 0.8 0.6 OFFSET DRIFT (g) 12 10 8 6 0.4 0.2 0 –0.2 –0.4 4 11669-202 –0.8 –1.0 –50 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 –0.2 –0.6 –1.0 –1.4 –1.8 –2.2 –2.6 0 11669-205 –0.6 2 –3.0 PERCENT OF POPULATION (%) 14 –35 –20 –5 10 25 40 55 TEMPERATURE (°C) 70 85 100 OFFSET (g) Figure 6. Z-Axis Zero g Offset at 25°C, VS = 2.5 V Figure 9. Z-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V Rev. B | Page 7 of 32 ADXL375 Data Sheet 25 23.0 SENSITIVITY (LSB/g) 22.0 15 10 5 21.5 21.0 20.5 20.0 19.5 18.5 18.0 –50 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 0 11669-209 19.0 11669-206 PERCENT OF POPULATION (%) 22.5 20 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) SENSITIVITY (LSB/g) Figure 10. X-Axis Sensitivity at 25°C, VS = 2.5 V Figure 13. X-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V 25 23.0 20 SENSITIVITY (LSB/g) 22.0 15 10 5 21.5 21.0 20.5 20.0 19.5 18.5 18.0 –50 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 0 11669-210 19.0 11669-207 PERCENT OF POPULATION (%) 22.5 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) SENSITIVITY (LSB/g) Figure 14. Y-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V Figure 11. Y-Axis Sensitivity at 25°C, VS = 2.5 V 23.0 16 22.5 22.0 SENSITIVITY (LSB/g) 12 10 8 6 21.5 21.0 20.5 20.0 19.5 4 11669-208 0 11669-211 19.0 2 18.5 18.0 –50 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 PERCENT OF POPULATION (%) 14 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) SENSITIVITY (LSB/g) Figure 12. Z-Axis Sensitivity at 25°C, VS = 2.5 V Figure 15. Z-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V Rev. B | Page 8 of 32 Data Sheet ADXL375 200 SUPPLY CURRENT (µA) 20 15 10 150 100 50 5 11669-212 0 2.0 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 0 2.4 2.8 11669-215 PERCENT OF POPULATION (%) 25 3.6 3.2 SUPPLY VOLTAGE (V) SELF-TEST RESPONSE (LSB) Figure 19. Supply Current vs. Supply Voltage (VS) at 25°C Figure 16. Z-Axis Self-Test Response at 25°C, VS = 2.5 V 200 X-AXIS, DUT1 X-AXIS, DUT2 Y-AXIS, DUT1 Y-AXIS, DUT2 Z-AXIS, DUT1 Z-AXIS, DUT2 20 150 OUTPUT (g) 15 10 100 0 100 110 120 130 140 150 160 170 180 190 11669-216 50 5 11669-213 PERCENT OF POPULATION (%) 25 0 200 0 50 CURRENT CONSUMPTION (µA) 100 150 200 REFERENCE ACCELERATION (g) Figure 20. Output Linearity over the Dynamic Range Figure 17. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V 160 1.2 1.0 NORMALIZED SENSITIVITY 120 100 80 60 40 0.8 X-AXIS Y-AXIS Z-AXIS 0.6 0.4 0 0 10 1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200 OUTPUT DATA RATE (Hz) 11669-217 0.2 20 11669-214 CURRENT CONSUMPTION (µA) 140 100 FREQUENCY (Hz) Figure 21. Frequency Response Figure 18. Current Consumption vs. Output Data Rate at 25°C, 10 Parts Soldered to PCB, VS = 2.5 V Rev. B | Page 9 of 32 1000 ADXL375 Data Sheet THEORY OF OPERATION The ADXL375 is a complete 3-axis acceleration measurement system with a measurement range of ±200 g. It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity. When the device is in standby mode, any register can be written to or read from. It is recommended that the device be configured in standby mode before enabling measurement mode. Clearing the measure bit returns the device to standby mode. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide resistance against forces due to applied acceleration. CURRENT CONSUMPTION AND OUTPUT DATA RATE Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation is used to determine the magnitude and polarity of the acceleration. POWER SEQUENCING Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL375. Table 7 provides a description of all the power modes. The interface voltage level is set using the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL375 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than or equal to VDD I/O. After VS is applied, the device enters standby mode. In standby mode, power consumption is minimized; the device waits for VDD I/O to be applied and for the command to enter measurement mode. This command can be initiated by setting the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). The ADXL375 automatically modulates its current consumption in proportion to its output data rate (see Table 6). The device bandwidth and output data rate are specified using the rate bits (Bits[D3:D0]) in the BW_RATE register (Address 0x2C). Table 6. Typical Current Consumption vs. Data Rate (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) Rate Bits 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Output Data Rate (Hz) 3200 1600 800 400 200 100 50 25 12.5 6.25 3.13 1.56 0.78 0.39 0.20 0.10 Bandwidth (Hz) 1600 800 400 200 100 50 25 12.5 6.25 3.13 1.56 0.78 0.39 0.20 0.10 0.05 IDD (µA) 145 90 140 140 140 140 90 60 50 40 35 35 35 35 35 35 Table 7. Power Modes Power Mode Power Off VS Off VDD I/O Off Bus Disabled On Off Bus Enabled Standby or Measurement Off On On On Description The device is completely off, but it is still possible for the device to create a conflict on the communication bus. The device is on in standby mode, but communication is unavailable and the device can create a conflict on the communication bus. Minimize the duration of the bus disabled state during power-up to prevent a conflict on the communication bus. No functions are available, but the device does not create a conflict on the communication bus. At power-up, the device is in standby mode, awaiting a command to enter measurement mode, and all sensor functions are off. After the device is instructed to enter measurement mode, all sensor functions are available. Rev. B | Page 10 of 32 Data Sheet ADXL375 POWER SAVING MODES FIFO BUFFER Low Power Mode The ADXL375 contains patented technology for an embedded memory management system with a 32-level FIFO buffer that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger. Each mode can be selected by setting the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register (Address 0x38; see Table 9). A low power mode is available for additional power savings. In low power mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). Table 8 shows the current consumption in low power mode for output data rates where there is an advantage to using low power mode. Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) Rate Bits 1100 1011 1010 1001 1000 0111 Output Data Rate (Hz) 400 200 100 50 25 12.5 Bandwidth (Hz) 200 100 50 25 12.5 6.25 IDD (µA) 90 60 50 45 40 35 Table 9. FIFO Modes (FIFO_CTL Register, Address 0x38) Setting D7 D6 0 0 0 1 FIFO Mode Bypass FIFO 1 0 Stream 1 1 Trigger Description FIFO buffer is bypassed. FIFO buffer collects up to 32 samples and then stops collecting data, collecting new data only when the buffer is not full. FIFO buffer holds the last 32 samples. When the buffer is full, the oldest data is overwritten with newer data. FIFO buffer holds the last samples before the trigger event and continues to collect data until full. New data is collected only when the buffer is not full. For data rates not shown in Table 8, the use of low power mode does not provide any advantage over normal power mode. Therefore, it is recommended that low power mode be used only for the data rates shown in Table 8. For an in-depth description of the FIFO buffer and FIFO modes, see the AN-1025 Application Note, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers. Autosleep Mode In bypass mode, the FIFO buffer is not operational and, therefore, remains empty. Additional power can be saved if the ADXL375 automatically switches to sleep mode during periods of inactivity. To enable the autosleep mode feature, 1. 2. Set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) to values that signify inactivity. The appropriate values depend on the application. Set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). Current consumption at the sub-12.5 Hz data rates that are used in autosleep mode is typically 35 µA for VS = 2.5 V. For information about the advantages of using low power mode vs. autosleep mode, see the Sleep Mode vs. Low Power Mode section. Standby Mode For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1 µA (typical). In this mode, no measurements are made, but the contents of the FIFO buffer are preserved. To enter standby mode, clear the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). Bypass Mode FIFO Mode In FIFO mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After the FIFO buffer stops collecting data, the device continues to operate; therefore, features such as shock detection can be used after the FIFO buffer is full. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. Stream Mode In stream mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples; the buffer stores the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. Rev. B | Page 11 of 32 ADXL375 Data Sheet Trigger Mode When SPI operation is enabled at a frequency of 1.6 MHz or lower, the register addressing portion of the transmission provides a sufficient delay to ensure that the FIFO buffer has completely emptied. When SPI operation is enabled at a frequency higher than 1.6 MHz, the CS pin must be deasserted to ensure a total delay of 5 µs; otherwise, the delay is not sufficient. When SPI operation is enabled at 5 MHz, the total delay necessary is at most 3.4 µs. In trigger mode, the FIFO buffer accumulates samples, storing the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs, an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), and the FIFO_TRIG bit (Bit D7) is set in the FIFO_STATUS register (Address 0x39). The FIFO buffer keeps the last n samples (n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when the FIFO buffer is not full. A delay of at least 5 µs must elapse between the occurrence of the trigger event and the start of data readback from the FIFO buffer to allow the buffer to discard and retain the necessary samples. Additional trigger events cannot be recognized until the part is reset to trigger mode. To reset the part to trigger mode, 1. 2. 3. If desired, read data from the FIFO buffer (see the Retrieving Data from the FIFO Buffer section). Before resetting the part to trigger mode, read back the FIFO data; placing the device into bypass mode clears the FIFO buffer. Configure the device for bypass mode by setting Bits[D7:D6] at Address 0x38 to 00. Configure the device for trigger mode by setting Bits[D7:D6] at Address 0x38 to 11. Retrieving Data from the FIFO Buffer When the FIFO buffer operates in FIFO, stream, or trigger mode, FIFO data can be read from the data registers (Address 0x32 to Address 0x37). Each time data is read from the FIFO buffer, the oldest x-, y-, and z-axis data is moved into the DATAX, DATAY, and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, data for all axes of interest must be read in a burst (multiple-byte) read operation. To ensure that the FIFO buffer is empty (that is, all new data has moved into the data registers), an interval of at least 5 µs must elapse between the end of the readback from the data registers and the start of a new read of the data registers or the FIFO_STATUS register (Address 0x39). The end of a read operation from the data registers is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. When I2C mode is enabled on the part, the communication rate is low enough to ensure a sufficient delay between FIFO reads. SELF-TEST The ADXL375 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the external acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS2, the output change varies with VS. The self-test response in the x- and y-axes exhibits bimodal behavior and, therefore, is not always a reliable indicator of sensor health or potential shift in device sensitivity. For this reason, perform the self-test check in the z-axis. Use of the self-test feature at data rates of less than 100 Hz or at 1600 Hz may yield values outside the limits shown in Figure 16. For the self-test function to operate correctly, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) and be configured for a data rate from 100 Hz to 800 Hz, or for a data rate of 3200 Hz (see Table 6). For more information about the self-test feature, see the Using Self-Test section. Rev. B | Page 12 of 32 Data Sheet ADXL375 INTERRUPTS The ADXL375 provides two output pins for driving interrupts: INT1 and INT2. Both interrupt pins are push-pull, low impedance pins (see Table 10 for output specifications). The default configuration of the interrupt pins is active high. The polarity can be changed to active low by setting the INT_INVERT bit (Bit D5) in the DATA_FORMAT register (Address 0x31). All interrupt functions can be enabled simultaneously, but some functions may need to share the same interrupt pin. ENABLING AND DISABLING INTERRUPTS Interrupts are enabled by setting the appropriate bits in the INT_ENABLE register (Address 0x2E); the interrupt is mapped to the INT1 pin or the INT2 pin based on the contents of the INT_MAP register (Address 0x2F). When the user configures the interrupt pins for the first time, it is recommended that the functions and interrupt mapping be configured before the interrupts are enabled. BITS IN THE INTERRUPT REGISTERS This section describes the interrupts that can be set in the INT_ENABLE register (Address 0x2E) and monitored in the INT_SOURCE register (Address 0x30). For an in-depth description of the FIFO buffer and the interrupt bits, see the AN-1025 Application Note, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers. DATA_READY Bit The DATA_READY bit is set when new data is available and is cleared when no new data is available. SINGLE_SHOCK Bit When changing the configuration of an interrupt, follow this procedure. The SINGLE_SHOCK bit is set when a single acceleration event that is greater than the value in the THRESH_SHOCK register (Address 0x1D) occurs for less time than is specified by the DUR register (Address 0x21). For more information, see the Shock Detection section. 1. DOUBLE_SHOCK Bit Disable the interrupt by clearing the bit corresponding to the function in the INT_ENABLE register. Reconfigure the interrupt function. Reenable the interrupt in the INT_ENABLE register. CLEARING INTERRUPTS The DOUBLE_SHOCK bit is set when two acceleration events that are greater than the value in the THRESH_SHOCK register (Address 0x1D) occur for less time than is specified by the DUR register (Address 0x21). The second shock event starts after the time specified by the latent register (Address 0x22) but within the time specified by the window register (Address 0x23). For more information, see the Shock Detection section. The interrupt functions are latched and can be cleared as follows: Activity Bit 1. The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced on any participating axis. Participating axes are specified by the ACT_INACT_CTL register (Address 0x27). 2. 3. Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt. 2. Read the data registers (Address 0x32 to Address 0x37) to clear the data-related interrupts. Read the INT_SOURCE register (Address 0x30) to clear the remaining interrupts. Table 10. Interrupt Pin Digital Output Specifications Parameter DIGITAL OUTPUT Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) PIN CAPACITANCE RISE/FALL TIME Rise Time (tR)2 Fall Time (tF)3 Test Conditions/Comments IOL = 300 µA IOH = −150 µA VOL = VOL, MAX VOH = VOH, MIN fIN = 1 MHz, VS = 2.5 V CLOAD = 150 pF Limits based on characterization results; not production tested. Rise time is measured as the transition time from VOL, MAX to VOH, MIN of the interrupt pin. 3 Fall time is measured as the transition time from VOH, MIN to VOL, MAX of the interrupt pin. 1 2 Rev. B | Page 13 of 32 Min Limit1 Max 0.2 × VDD I/O Unit −150 8 V V µA µA pF 210 150 ns ns 0.8 × VDD I/O 300 ADXL375 Data Sheet Inactivity Bit Overrun Bit The inactivity bit is set when acceleration less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified by the TIME_INACT register (Address 0x26) on all participating axes. Participating axes are specified by the ACT_INACT_CTL register (Address 0x27). The maximum value for TIME_INACT is 255 sec. The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode (see the FIFO Buffer section). Watermark Bit • The watermark bit is set when the number of samples in the FIFO buffer equals the value stored in the samples bits (Bits[D4:D0]) of the FIFO_CTL register (Address 0x38). The watermark bit is cleared automatically when the FIFO buffer is read and the FIFO contents return to a value below the value specified by the samples bits. • In bypass mode, the overrun bit is set when new data replaces unread data in the data registers (Address 0x32 to Address 0x37). In FIFO mode, stream mode, and trigger mode, the overrun bit is set when the FIFO buffer is full. The overrun bit is automatically cleared when the FIFO buffer contents are read. Rev. B | Page 14 of 32 Data Sheet ADXL375 SERIAL COMMUNICATIONS The ADXL375 supports I2C and SPI digital communications. In both cases, the ADXL375 operates as a slave device. When the CS pin is tied high to VDD I/O, I2C mode is enabled. The CS pin must be tied high to VDD I/O or be driven by an external controller. If the CS pin is left unconnected, the user may not be able to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I2C modes of operation, ignore data transmitted from the ADXL375 to the master device during writes to the ADXL375. SPI MODE The ADXL375 can be configured for 3-wire SPI mode or 4-wire SPI mode, as shown in Figure 22 and Figure 23. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode; setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading. The timing scheme requires clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to the ADXL375 before the clock polarity and phase of the host processor are configured, take the CS pin high before changing the clock polarity and phase. When using 3-wire SPI mode, it is recommended that the SDO pin be either pulled up to VDD I/O or pulled down to GND via a 10 kΩ resistor. PROCESSOR D OUT SDIO D IN/OUT SDO SCLK D OUT PROCESSOR D OUT SDI D OUT SDO D IN SCLK D OUT 11669-003 CS Use of the 3200 Hz and 1600 Hz output data rates is recommended only with SPI communication speeds greater than or equal to 2 MHz. The 800 Hz output data rate is recommended only with communication speeds greater than or equal to 400 kHz, and the remaining data rates scale proportionally. For example, the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz. Operation at an output data rate above the recommended maximum value may result in undesirable effects on the acceleration data, including missing samples or additional noise. Preventing Bus Traffic Errors Figure 22. 3-Wire SPI Connection Diagram ADXL375 Figure 25 and Figure 26 show the timing diagrams for 4-wire SPI writes and reads, respectively. Figure 27 shows the timing diagram for 3-wire SPI reads or writes. For correct operation of the part, the logic thresholds and timing parameters in Table 11 and Table 12 must be met at all times. Figure 23. 4-Wire SPI Connection Diagram CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 25 to Figure 27. SCLK is the serial port clock and is supplied by the SPI master. SCLK should idle high during a period of no transmission. In 4-wire SPI mode, SDI and SDO are the serial data input and output, respectively. In 3-wire SPI mode, SDIO functions as both the serial data input and output. Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK. The ADXL375 CS pin is used both for initiating SPI transactions and for enabling I2C mode. When the ADXL375 is used on a SPI bus with multiple devices, its CS pin is held high while the master communicates with the other devices. There may be conditions where a SPI command transmitted to another device looks like a valid I2C command. In this case, the ADXL375 interprets this command as an attempt to communicate in I2C mode and may interfere with other bus traffic. Unless bus traffic can be adequately controlled to ensure that such a condition never occurs, it is recommended that a logic gate be added in front of Pin 13 (SDA/SDI/SDIO), as shown in Figure 24. This OR gate holds the SDA line high when CS is high to prevent SPI bus traffic at the ADXL375 from appearing as an I2C start command. Rev. B | Page 15 of 32 ADXL375 CS SDA/SDI/SDIO PROCESSOR D OUT D IN/OUT SDO D IN SCLK D OUT 11669-104 CS 11669-004 ADXL375 To read or write multiple bytes in a single transmission, the multiple-byte bit (MB in Figure 25 to Figure 27), located after the R/W bit in the first byte transfer, must be set. After the register address byte and the first byte of data, each subsequent set of eight clock pulses causes the ADXL375 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions and the new register must be addressed separately. Figure 24. Recommended SPI Connection Diagram When Using Multiple SPI Devices on a Single Bus ADXL375 Data Sheet CS tM tSCLK tDELAY tS tQUIET tCS, DIS SCLK MB W SDI A5 tSDO X SDO A0 ADDRESS BITS X X D7 D0 DATA BITS tDIS X X X 11669-017 tHOLD tSETUP Figure 25. SPI 4-Wire Write Timing Diagram CS tM tSCLK tDELAY tS tCS, DIS tQUIET SCLK tHOLD R SDI MB A5 tSDO X SDO A0 X X tDIS ADDRESS BITS X X X D7 D0 11669-018 tSETUP DATA BITS Figure 26. SPI 4-Wire Read Timing Diagram CS tDELAY tM tSCLK tS tQUIET tCS, DIS SCLK tSETUP SDIO tHOLD R/W tSDO MB A5 A0 D0 DATA BITS 11669-019 ADDRESS BITS D7 NOTES 1. tSDO IS ONLY PRESENT DURING READS. Figure 27. SPI 3-Wire Read/Write Timing