Datasheet · 2022
Ratiometric analogue linear Hall sensors; 4.5–5.5 V supply, which is why the light-gun trigger design rejected them for a 3.3 V board.
A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output FEATURES AND BENEFITS • Temperature-stable quiescent output voltage and sensitivity • Output voltage proportional to magnetic flux density • Low-noise output increases accuracy • Precise recoverability after temperature cycling • Ratiometric rail-to-rail output • Wide ambient temperature range: –40°C to 150°C • Immune to mechanical stress • Solid-state reliability • Enhanced EMC performance for stringent automotive applications PACKAGES 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) DESCRIPTION New applications for linear output Hall-effect devices, such as displacement, angular position, and current measurement, require high accuracy in conjunction with small package size. The Allegro™ A1324, A1325, and A1326 linear Hall-effect sensor ICs are designed specifically to achieve both goals. This temperature-stable device is available in a miniature surface mount package (SOT23W) and an ultra-mini through-hole single in-line package. These ratiometric Hall effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. They feature a quiescent voltage output of 50% of the supply voltage. The A1324/25/26 feature factory programmed sensitivities of 5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively. The features of these linear devices make them ideal for use in automotive and industrial applications requiring high accuracy, and operate through an extended temperature range, –40°C to 150°C. Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. These devices are available in a 3-pin ultra-mini SIP package (UA), and a 3-pin surface mount SOT-23 style package (LH). Both are lead (Pb) free, with 100% matte tin leadframe plating. Approximate footprint Functional Block Diagram V+ To All Subcircuits Tuned Filter Dynamic Offset Cancellation VCC Sensitivity and Sensitivity TC VOUT Offset Trim Control GND A1324-DS, Rev. 9 MCO-0000598 June 16, 2022 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output SELECTION GUIDE Sensitivity (Typ.) (mV/G) Part Number Packing [1] Package A1324LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount A1324LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount A1324LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount 3-pin SOT-23W surface mount A1325LLHLT-T 3,000 pieces per reel A1325LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount A1325LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount A1326LLHLT-T 3,000 pieces per reel 3-pin SOT-23W surface mount A1326LLHLX-T 10,000 pieces per reel 3-pin SOT-23W surface mount A1326LUA-T [2] 500 pieces per bag 3-pin ultramini SIP through hole mount 5.000 3.125 2.500 [1] Contact Allegro™ for additional packing options. [2] Contact factory for availability. ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 8 V Reverse Supply Voltage VRCC –0.1 V Forward Output Voltage VOUT 15 V Reverse Output Voltage VROUT –0.1 V Output Source Current IOUT(SOURCE) VOUT to GND 2 mA Output Sink Current IOUT(SINK) VCC to VOUT 10 mA Operating Ambient Temperature TA –40 to 150 °C Maximum Junction Temperature TJ(max) 165 °C Tstg –65 to 170 °C Storage Temperature L temperature range Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Value Unit Package LH, on 4-layer PCB with copper limited to solder pads 228 °C/W 110 °C/W 165 °C/W Package LH, on 2-layer PCB with 0.463 in.2 of copper area each RθJA Package Thermal Resistance Test Conditions* side, connected by thermal vias Package UA, on 1-layer PCB with copper limited to solder pads *Additional thermal information available on the Allegro website. Pinout Diagrams Terminal List Table Name 3 1 2 LH Package 1 2 3 Number Function LH UA VCC 1 1 Input power supply; tie to GND with bypass capacitor VOUT 2 3 Output signal; also used for programming GND 3 2 Ground UA Package Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output OPERATING CHARACTERISTICS: Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit [1] 4.5 5.0 5.5 V ELECTRICAL CHARACTERISTICS Supply Voltage VCC Supply Current ICC No load on VOUT – 6.9 9 mA Power-On Time [2] tPO TA = 25°C, CL (PROBE) = 10 pF – 32 – µs Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 12 mA 6 8.3 – V Internal Bandwidth BWi Small signal, –3 dB – 17 – kHz Chopping Frequency [3] fC TA = 25°C – 400 – kHz 2.425 2.500 2.575 V A1324, TA = 25°C, CBYPASS = 0.1 µF – 7.0 – mV(p-p) A1325, TA = 25°C, CBYPASS = 0.1 µF – 4.4 – mV(p-p) A1326, TA = 25°C, CBYPASS = 0.1 µF – 3.5 – mV(p-p) TA = 25°C, CBYPASS = open, no load on VOUT, f << BWi – 1.3 – mG/√Hz – <1 – Ω VOUT to VCC 4.7 – – kΩ VOUT to GND 4.7 – – kΩ VOUT to GND – – 10 nF VOUT(sat)HIGH RPULLDOWN = 4.7 kΩ, VCC = 5 V 4.7 – – V VOUT(sat)LOW RPULLUP = 4.7 kΩ, VCC = 5 V – – 0.30 V A1324, TA = 25°C 4.750 5.000 5.250 mV/G A1325, TA = 25°C 2.969 3.125 3.281 mV/G A1326, TA = 25°C 2.375 2.500 2.625 mV/G LH package; programmed at TA = 150°C, calculated relative to Sens at 25°C – 0 – %/°C UA package; programmed at TA = 150°C, calculated relative to Sens at 25°C – 0.03 – %/°C LH package; from hot to room temperature –5 – 5 % UA package; from hot to room temperature –2.5 – 7.5 % LH package; from cold to room temperature –3.5 – 8.5 % UA package; from cold to room temperature –6 – 4 % OUTPUT CHARACTERISTICS Quiescent Voltage Output VOUT(Q) Output Referred Noise VN Input Referred RMS Noise Density VNRMS DC Output Resistance ROUT Output Load Resistance RL Output Load Capacitance CL Output Saturation Voltage B = 0 G, TA = 25°C MAGNETIC CHARACTERISTICS Sensitivity Sensitivity Temperature Coefficient Sens TCSens ERROR COMPONENTS Sensitivity Drift at Maximum Ambient Operating Temperature ∆Sens(TAmax) Sensitivity Drift at Minimum Ambient Operating Temperature ∆Sens(TAmin) Continued on the next page… Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output OPERATING CHARACTERISTICS (continued): Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit [1] –10 – 10 G –1.5 – 1.5 % ERROR COMPONENTS (continued) Quiescent Voltage Output Drift Through Temperature Range ∆VOUT(Q) Linearity Sensitivity Error LinERR Symmetry Sensitivity Error SymERR Ratiometry Quiescent Voltage Output Error [4] Ratiometry Sensitivity Error [4] Sensitivity Drift Due to Package Hysteresis RatVOUT(Q) RatSens ∆SensPKG Defined in terms of magnetic flux density, B –1.5 – 1.5 % Throughout supply voltage range (relative to VCC = 5 V) –1.3 – 1.3 % Throughout supply voltage range (relative to VCC = 5 V), TA = 25°C and 150°C –1.5 – 1.5 % Throughout supply voltage range (relative to VCC = 5 V), TA = –40°C –2 – 2 % TA = 25°C, after temperature cycling – ±2 – % [1] 1 G (gauss) = 0.1 mT (millitesla). [2] See Characteristic Definitions section. [3] f varies up to approximately ±20% over the full operating ambient temperature range and process. C [4] Percent change from actual value at V CC = 5 V, for a given temperature. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output CHARACTERISTIC DEFINITIONS Power-On Time. When the supply is ramped to its operating voltage, the device output requires a finite time to react to an input magnetic field. Power-On Time is defined as the time it takes for the output voltage to begin responding to an applied magnetic field after the power supply has reached its minimum specified operating voltage, VCC(min). V VOUT 90% VOUT t2 tPO t1= time at which power supply reaches minimum specified operating voltage where B(+) and B(–) are two magnetic fields with opposite polarities. SensIDEAL(TA) = SensT1 × (100% + TCSENS(TA –T1) ) +t Quiescent Voltage Output. In the quiescent state (that is, with no significant magnetic field: B = 0), the output, VOUT(Q) , equals a ratio of the supply voltage, VCC , throughout the entire operating range of VCC and the ambient temperature, TA . Quiescent Voltage Output Drift Through Temperature Range. Due to internal component tolerances and thermal considerations, the quiescent voltage output, VOUT(Q) , may drift from its nominal value through the operating ambient temperature range, TA . For purposes of specification, the Quiescent Voltage Output Drift Through Temperature Range, ∆VOUT(Q) (mV), is defined as: ∆VOUT(Q) = VOUT(Q)TA – VOUT(Q)25°C (2) B(+) – B(–) The ideal value of sensitivity through the temperature range, SensIDEAL(TA), is defined as: t2= time at which output voltage settles within ±10% of its steady state value under an applied magnetic field 0 VOUT(B+) – VOUT(B–) 1 SensT2 – SensT1 TCSens = 100% × (3) SensT1 T2–T1 where T1 is the nominal Sens programming temperature of 25°C, and T2 is the TCSENS programming temperature of 150°C. VCC(min.) t1 Sens = Sensitivity Temperature Coefficient. The device sensitivity changes with temperature, with respect to its sensitivity temperature coefficient, TCSENS . TCSENS is programmed at 150°C, and calculated relative to the nominal sensitivity programming temperature of 25°C. TCSENS (%/°C) is defined as: VCC VCC(typ.) defined as: (1) Sensitivity. The presence of a south-polarity magnetic field perpendicular to the branded surface of the package increases the output voltage from its quiescent value toward the supply voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north polarity field will decrease the output voltage from its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is (4) Sensitivity Drift Through Temperature Range. Second order sensitivity temperature coefficient effects cause the magnetic sensitivity to drift from its ideal value through the operating ambient temperature, TA. For purposes of specification, the sensitivity drift through temperature range, ∆SensTC , is defined as: ∆SensTC = SensTA – SensIDEAL(TA) SensIDEAL(TA) × 100% (5) Sensitivity Drift Due to Package Hysteresis. Package stress and relaxation can cause the device sensitivity at TA = 25°C to change during or after temperature cycling. This change in sensitivity follows a hysteresis curve. For purposes of specification, the Sensitivity Drift Due to Package Hysteresis, ∆SensPKG , is defined as: ∆SensPKG = Sens(25°C)2 – Sens(25°C)1 × 100% Sens(25°C)1 (6) where Sens(25°C)1 is the programmed value of sensitivity at TA = 25°C, and Sens(25°C)1 is the value of sensitivity at TA = 25°C after temperature cycling TA up to 150°C, down to –40°C, and back to up 25°C. Linearity Sensitivity Error. The 132x is designed to provide Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally the sensitivity of a device is the same for both fields for a given supply voltage and temperature. Linearity sensitivity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity Sensitivity Error is calculated separately for the positive (LINERR+) and negative (LINERR– ) applied magnetic fields. Linearity Sensitivity Error (%) is measured and defined as: SensB(++) × 100% LinERR+ = 1– SensB(+) SensB(– –) × 100% LinERR– = 1– SensB(–) (7) and where: LinERR = max(| LinERR+| , |LinERR–| ) (8) |V – VOUT(Q)| SensBx = OUT(Bx) (9) BX and B(++), B(+), B(– –), and B(–) are positive and negative magnetic fields with respect to the quiescent voltage output such that |B(++)| > |B(+)| and |B(– –)| > |B(– )| . Symmetry Sensitivity Error. The magnetic sensitivity of a device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. Symmetry Error (%), is measured and defined as: SensB(+) × 100% SymERR = 1– SensB(–) (11) where SensBx is defined as in equation 9, and B(+), B(–) are positive and negative magnetic fields such that |B(+)| = |B(–)|. Ratiometry Error. The A132x features a ratiometric output. This means that the quiescent voltage output, VOUT(Q) , magnetic sensitivity, Sens, and clamp voltages, VCLPHIGH and VCLPLOW , are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage, relative to 5 V, and the measured change in each characteristic. The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as: VOUT(Q)VCC ⁄ VOUT(Q)5V × 100% RatVOUT(Q) = 1– VCC ⁄ 5 V (12) The ratiometric error in magnetic sensitivity, RatSENS (%), for a given supply voltage, VCC, is defined as: SensVCC ⁄ Sens5V × 100% RatVOUT(Q) = 1– VCC ⁄ 5 V Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com (13) 7 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Typical Characteristics (30 pieces, 3 fabrication lots) Average Supply Current versus Ambient Temperature VCC = 5 V 12 11 ICCav (mA) 10 9 8 7 6 5 4 – 40 25 150 TA (°C) Average Negative Linearity versus Ambient Temperature VCC = 5 V 105 105 104 104 103 103 102 102 Lin–av (%) Lin+av (%) Average Postive Linearity versus Ambient Temperature VCC = 5 V 101 100 99 101 100 99 98 98 97 97 96 96 95 – 40 25 95 150 – 40 TA (°C) Average Quiescent Voltage Output Ratiometry versus Ambient Temperature 102.0 100.6 VCC 5.5 to 5.0 V 100.4 4.5 to 5.0 V 100.2 100.0 99.8 99.6 VCC 5.5 to 5.0 V 101.5 RatSens(av) (%) RatVOUTQ(av) (%) 150 Average Sensitivity Ratiometry versus Ambient Temperature 101.0 100.8 101.0 4.5 to 5.0 V 100.5 100.0 99.5 99.0 99.4 98.5 99.2 99.0 25 TA (°C) – 40 25 TA (°C) 150 98.0 – 40 25 150 TA (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Typical Characteristics, continued (30 pieces, 3 fabrication lots) Average Absolute Quiescent Voltage Output versus Ambient Temperature VCC = 5 V Quiescent Voltage Output versus Supply Voltage TA = 25°C 3.0 2.565 2.525 2.9 A1324 A1325 2.8 A1325 A1326 2.7 A1326 2.505 2.485 VOUT(Q) (V) VOUT(Q)av (V) 2.545 A1324 2.6 2.5 2.4 2.3 2.465 2.2 2.445 2.1 2.0 2.425 – 40 25 150 4.5 TA (°C) 6.0 5.5 A1324 Sensav (mV/G) Sensav (mV/G) 6.0 5.5 4.5 4.0 3.5 A1325 3.0 2.0 A1324 5.0 4.5 4.0 3.5 A1325 3.0 A1326 2.5 2.0 A1326 2.5 1.5 – 40 25 1.0 150 4.5 TA (°C) 10 8 8 6 6 4 4 ∆Sensav (%) 10 2 0 -2 -4 5 VCC (V) 5.5 Average Sensitivity Drift versus Ambient Temperature ∆Sensav values relative to 25°C, VCC = 5 V Average Quiescent Voltage Output Drift versus Ambient Temperature ∆VOUT(Q)av values relative to 25°C, VCC = 5 V ∆VOUT(Q)av (G) 5.5 Average Sensitivity versus Supply Voltage TA = 25°C Average Absolute Sensitivity versus Ambient Temperature VCC = 5 V 5.0 5 VCC (V) 2 0 -2 -4 -6 -6 -8 -8 -10 -10 – 40 25 TA (°C) 150 – 40 25 150 TA (°C) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output V+ 1[1] VCC VOUT 2[3] VOUT A132x CBYPASS 0.1 µF GND 3[2] Pin numbers in brackets refer to the UA package Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switch point accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the Hall IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-Aliasing LP Filter Tuned Filter Concept of Chopper Stabilization Technique Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Package LH, 3-Pin SOT23W For Reference Only – Not for Tooling Use (Reference Allegro DWG-0000628, Rev. 1) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown +0.125 2.975 –0.075 1.49 4°±4° Active Area Depth 0.28 ±0.04 mm 3 +0.020 0.180–0.053 0.96 +0.10 2.90 –0.20 +0.19 1.91 –0.06 Hall element (not to scale) 0.25 MIN 0.38 NOM 1.00 0.95 2 1 PCB Layout Reference View 0.55 REF 0.25 BSC Seating Plane Gauge Plane 8× 10° ±5° 0.41 ±0.04 C 0.95 BSC All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branded Face 0.57 ±0.04 3× 0.10 2.40 0.70 +0.10 0.05 –0.05 0.40 ±0.10 1.00 ±0.13 SEATING PLANE C XXX 1 Standard Branding Reference View 1 Line 1 = Three digit assigned brand number Branding scale and appearance at supplier discretion Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Package UA, 3-Pin SIP For Reference Only – Not For Tooling Use (Reference DWG-0000404, Rev. 1) NOT TO SCALE Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown Mold gate and tie bar protrusion zone Ejector pin flash protrusion R0.25 MAX (2×) 5° (2×) 0.56 MAX 45° (2×) 0.10 MAX 1.52 ±0.05 5° (2×) 1 Standard Branding Reference View +0.08 4.09 –0.05 3.00 ±0.05 Mold gate and tie bar protrusion zone Ejector pin (far side) Including gate and tie bar burrs +0.08 3.02 –0.05 3.10 MAX XXX 1.68 MAX Line 1 = Logo A Line 2 = Three digit assigned brand number Branding scale and appearance at supplier discretion 0.15 MAX +0.05 0.08 –0.00 2.04 0.50 ±0.08 Active Area Depth Ejector pin flash protrusion 1.44 Hall Element (not to scale) 10° (3×) 1.02 MAX 45° 0.79 REF 0.51 REF 0.05 NOM 0.05 NOM 14.99 ±0.25 +0.03 0.41 –0.06 0.10 MAX 0.10 MAX Dambar Trim Detail 1.27 NOM (2×) +0.05 0.43 –0.07 (3×) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A1324, A1325, and A1326 Low-Noise Linear Hall-Effect Sensor ICs with Analog Output Revision History Number Date Description 3 September 16, 2013 Update product selection 4 September 26, 2013 Fixed UA package drawing 5 February 14, 2019 Minor editorial updates 6 February 21, 2020 Minor editorial updates 7 June 8, 2020 Added variant with 3-pin ultramini SIP through hole mount with 2.54 mm lead spacing to Selection Guide (page 2) 8 June 11, 2020 Removed leadform variant (page 2) 9 June 16, 2022 Updated package drawings (pages 11-12) and minor editorial updates Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13